JPH0828888B2 - PLL circuit synchronization method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method of synchronizing a PLL circuit, and more particularly to a method of synchronizing a PLL circuit that generates a clock synchronized with a reproduced video signal.

BACKGROUND ART In a video signal player such as a video disc player or a VTR, a rotation system such as a spindle motor is controlled on the basis of a reference horizontal synchronizing signal generated in the device, so that a playback obtained from a recording medium is performed. Although the video signal includes jitter (time-axis fluctuation), it is synchronized with the reference horizontal sync signal on average. Therefore, if you synchronize the PLL circuit that generates the clock synchronized with the playback video signal with the reference horizontal synchronization signal before synchronizing with the playback video signal,
Synchronous pulling in to the reproduced video signal becomes easy, and it is possible to pull in reliably in a short time. In addition, since the color burst signal can detect the phase error with higher accuracy than the playback horizontal synchronization signal during stable playback of the video signal, the PLL
The circuit should be synchronized with the color burst signal.

However, even when the PLL circuit is synchronized with the color burst signal, the synchronization target is selected in the vertical blanking period, track jump, during the search period, or during the reproduction of the section in which the reproduced video signal does not include the color burst signal. It may be switched to the playback horizontal sync signal. When switching the synchronization target from the color burst signal to the playback horizontal sync signal or from the playback horizontal sync signal to the color burst signal, if the phase difference between the color burst signal and the playback horizontal sync signal is large, a large phase error will occur immediately after switching. Occurs, the VCO (voltage controlled oscillator) clock of the PLL fluctuates greatly, and the PLL becomes unstable. In particular, when a signal obtained by FM-modulating a video signal is AD-converted by a VCO clock, the clock fluctuation causes a level fluctuation of the FM-detected video signal, which adversely affects the separation of the sync signal.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and when switching a synchronization target between a color burst signal and a reproduction horizontal synchronization signal, suppresses the occurrence of a large phase error and stabilizes the VCO clock. By doing so, it is an object of the present invention to provide a synchronization method for a PLL circuit that eliminates the disturbance of synchronization after switching.

A method of synchronizing a PLL circuit according to the present invention generates a clock synchronized with a reproduction horizontal synchronization signal extracted from a reproduction video signal reproduced from a recording medium, while a color burst signal is extracted from the reproduction video signal. Is a method of synchronizing a PLL circuit for generating a clock synchronized with the color burst signal, wherein a phase difference between the color burst signal and the reproduction horizontal synchronization signal is generated during an operation of generating a clock synchronized with the color burst signal. Obtained from the clock generation operation in synchronization with the color burst signal,
When switching to a clock generation operation synchronized with the reproduction horizontal synchronization signal, a phase error of the reproduction horizontal synchronization signal with respect to a predetermined phase comparison signal is corrected by the phase difference.

Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a video signal reproducing apparatus having a PLL circuit according to the present invention and having a configuration for digitally performing signal processing, for example. In the figure, the FM video signal read from a recording medium such as a video disc is an analog LPF.
It is supplied to the A / D converter 2 via the (low-pass filter) 1. LPF1 is for removing aliasing distortion in A / D conversion. The digitized FM video signal output from the A / D converter 2 is supplied to a digital BPF (bandpass filter) 3. This digital BPF 3 extracts only the components necessary for the detection of the video signal from the A / D conversion output that also includes the FM audio signal and supplies it to the FM detection circuit 4 in the next stage.
As the FM detection circuit 4, for example,
The configuration proposed in No. 59-262481 can be used. FM
From the detection output of the detection circuit 4, only the baseband component of the video signal is extracted in the video LPF 5.

A dropout detection circuit 6 for detecting a dropout of a video signal is provided. The dropout detection circuit 6 has, for example, a level comparator configuration, and detects that the signal level of the squared signal of the envelope component of the digitized FM video signal in the FM detection circuit 4 becomes a predetermined value or less and drops out. Output the detection signal. The digitized video signal that has passed through the video LPF 5 is supplied to the dropout correction circuit 7 and the signal comprehension path 8. The dropout correction circuit 7 responds to the dropout detection signal supplied from the dropout detection circuit 6 to correct the dropout.

The signal separation circuit 8 separates signals such as a horizontal synchronizing signal and a color burst signal included in the digitized video signal and supplies them to the PLL circuit 9. The PLL circuit 9 generates a clock synchronized with the reproduced video signal, and the synchronization of the reproduced horizontal synchronizing signal from the signal separating circuit 8, the color burst signal and the reference horizontal synchronizing signal from the reference signal generating circuit 10 3 signals are input and 4f _sc based on these signals
(F _sc is a color subcarrier frequency) and 4N ₁ f _sc (N ₁ is an integer of 2 or more, for example, 3). The 4f _sc and 4N ₁ f _sc clocks are used as clocks for digital signal processing, and the sampling clock of the A / D converter 2 and the signal processing clock up to the video LPF 5 are used as 4N ₁ clocks.
and f _sc, downsampling the output of the video LPF5 the clock 4f _sc. In the signal separation circuit 8, 4f _sc
Is used as a sampling clock for the reproduction horizontal synchronizing signal and the color burst signal.

The digitized video signal output from the dropout correction circuit 7 is written in the buffer memory 11 by the 4f _sc clock generated by the PLL circuit 9. The reading of data from the buffer memory 11 is performed by the reference signal generation circuit 10
This is done by a 4f _sc reference clock generated at. As described above, by reading the data from the buffer memory 11 with a stable reference clock that is not related to the reproduced video signal, it is possible to absorb the jitter of the reproduced video signal. The digitized video signal read from the buffer memory 11 is analogized by the D / A converter 12 and becomes a reproduced video output.

FIG. 2 is a block diagram showing a concrete configuration of the PLL circuit 9 in FIG. In the figure, the signal separation circuit 8
Playback horizontal sync signal (PB
H) and the reference horizontal synchronizing signal (REF H) generated by the reference signal generating circuit 10 become two inputs of the selector 21 which is switched and controlled by the PLL control circuit 20. The reproduction horizontal synchronizing signal or the reference horizontal synchronizing signal selected by the selector 21 is supplied to the control circuit 20 and also serves as one input of the first phase comparator 22. The comparison output of the phase comparator 22 is supplied to the control circuit 20 and also becomes one input of each of the adder 23 and the selector 24. The selector 24 is switching-controlled by the control circuit 20. The selection output of the selector 24 is supplied to the limiter 25. The limiter 25 is configured to selectively perform an amplitude limiting operation on the input signal, and the selection control is performed by the control circuit 20. The output of the limiter 25 becomes one input of the selector 26.

On the other hand, the color burst signal (CB) separated from the reproduced video signal by the signal separation circuit 8 becomes one input of the second phase comparator 27. The comparison output of the phase comparator 27 is supplied to the control circuit 20 and becomes the other input of the selector 26.
The selector 26 is switched and controlled by the control circuit 20. The selection output of the selector 26 is supplied to the loop filter 28 for determining the loop characteristic of the PLL. The loop filter 28 is a digital filter configured to realize desired characteristics, and its output is converted into an analog voltage by the D / A converter 29 and becomes a control voltage of the VCO 30. VCO30
The oscillation frequency is controlled by the output voltage of the D / A converter 29,
The output becomes the master clock f _M of this circuit,
It is supplied to the N ₂ frequency divider 33, the N ₃ frequency divider 33 and the control circuit 20 via the N ₁ frequency divider 31. The output of the N ₂ frequency divider 32 is the other input of the phase comparator 22, and the output of the N ₃ frequency divider 33 is the other input of the phase comparator 27, thus forming a PLL.

The N ₁ frequency divider 31 is for dividing the master clock f _{M up} to the sampling clock 4f _sc of the reproduction horizontal synchronizing signal and the color burst signal. For example, when f _M = 16f _sc , N ₁ = 4. The N ₂ divider 32 outputs the output of the N ₁ divider 31 (f _M / N
_{This is} for dividing ₁ ) up to the horizontal scanning frequency f _H , and N ₂ = 910 in the NTSC system. N ₃ frequency divider 33 is for frequency dividing the output of the N ₁ frequency divider 31 (f _M / N ₁₎ to the color subcarrier frequency f _sc, when _{f M / N 1 = 4f sc} , N ₃ = 4.

The PLL control circuit 20 includes a flip-flop and a PLA (Pr
grammable Logic Array) or an initial reset signal (IRST) that is configured by a microcomputer or the like and is issued when the power is turned on, a vertical blanking signal (VBLK) that indicates a vertical blanking period,
The scan signal (SCAN) indicating that a search or visual scan is in progress, the jump signal (JUMP) indicating that a jump to an adjacent track in special playback such as a still image is used as control signals, and the selectors 21, 24, 26 Switching, selection of limiter 25 amplitude limit operation, loop filter
Controls such as setting 28 to the initial state and resetting the frequency dividers 32 and 33 are performed. The loop filter 28 is set to the initial state by setting each register in the digital filter to a predetermined value.

The PLL control circuit 20 further determines the color burst signal and the reproduction horizontal synchronization signal based on the output of the phase comparator 27 and the output of the phase comparator 22 in a state where the PLL synchronizes with the color burst signal. Is calculated and averaged, and this is used as the other input of the adder 23 to correct the output of the phase comparator 22, that is, the phase error of the reproduced horizontal synchronizing signal. The reason why the phase difference between the color burst signal and the reproduction horizontal synchronizing signal is obtained when the color burst signal is synchronized with the color burst signal instead of the reproducing horizontal synchronizing signal is as follows.

Since the phase error of the color burst signal can be obtained more accurately, the clock fluctuation during synchronization is small.

Since the cycle of the color burst signal (1 / f _sc ) is short and the synchronization accuracy of the playback horizontal sync signal is poor, the phase fluctuation f
_It may be more than ± 180 ° of _sc . If the phase fluctuation exceeds this value, the phase difference between the reproduced horizontal synchronizing signal and the color burst signal cannot be accurately obtained.

When the phase comparator 27 approximates sin θ = θ with the sin type phase comparison characteristic, the output value of the phase comparator 27 is 0.
There is an error outside the neighborhood. When synchronized with the reproduction horizontal synchronizing signal, the output value of the phase comparator 27 is not always near 0. Further, the averaging of the phase difference in the PLL control circuit 20 may be a moving average or a low pass filter.

 Next, the operation of this configuration will be described.

When the power is turned on or the video signal is not input, PL
The L control circuit 20 selects the reference horizontal synchronizing signal with the selector 21 on the a side and the phase comparator 22 with the selector 24 on the a side by a control signal such as an initial reset signal (IRST).
The output of the limiter 25 is selected by setting the selector 26 to the side a without switching the limiter 25 to the amplitude limiting state. In addition, VCO30
The loop filter 28 is set so that the initial frequency of is set to the center value when the PLL is locked, and the N ₂ frequency divider 32 is controlled by the control circuit so that the initial phase error of the two inputs of the phase comparator 22 becomes zero. Reset by reference horizontal sync signal via 20. After these sets and resets are released, the PLL starts the synchronization pull-in to the reference horizontal synchronization signal selected by the selector 21.

The phase comparator 22 detects a phase error between the clock of the horizontal scanning frequency f _H obtained by dividing the output of the VCO 30 and the reference horizontal synchronizing signal as a digital value. The detected value is the selector 24,
It is input to the loop filter 28 via the limiter 25 and the selector 26. The output of the loop filter 28 is analogized by the D / A converter 29 and becomes the control voltage of the VCO 30. The control circuit 20 monitors the output of the phase comparator 22 and detects that the phase error is n ₂ within n ₁ · H (for example, n ₁ = 16) from the start of the synchronization pull-in.
A predetermined range W ₁ (for example, +1.
If the video signal is being reproduced at this time, the control circuit 20 immediately switches the selector 21 to the b side to select the reproduction horizontal synchronizing signal and N ₂ minutes. The frequency divider 32 is reset by the reproduced horizontal synchronizing signal so that the initial phase error of the phase comparator 22 with respect to the reproduced horizontal synchronizing signal becomes zero.

As with the reference horizontal sync signal, the control circuit 20 releases the reset of the N ₂ frequency divider 32 to start the sync pull-in to the playback horizontal sync signal, and also monitors the output of the phase comparator 22 to lock it. It is determined whether or not the condition of is satisfied. As a result of the determination, if the lock condition is not satisfied, the lock is disabled, and the control circuit 20 switches the selector 21 to the a side again to select the reference horizontal synchronizing signal and the N ₂ frequency divider 32.
Reset. At this time, the loop filter 28 may also be set to the initial state. After that, the lock determination is performed again with respect to the reference horizontal synchronizing signal, but when the lock is impossible again, the initial state after the power is turned on is returned to and the setting / resetting of each unit is performed. It should be noted that the lock / unlock determination condition may be the same or different between the reference horizontal sync signal and the reproduction horizontal sync signal (for example,
Change the values of n ₁ and n ₂ and the range W ₁ . ) In the case of the reference horizontal sync signal, there is no jitter in the signal itself and it is stable, so there is no problem with a simpler judgment condition, but if it is the same as the playback horizontal sync signal, the control in the control circuit 20 will be easier. Become.

When it is determined that the playback horizontal synchronizing signal is locked when the selector 21 is set to the b side, the control circuit 20 determines the limiter.
25 is subjected to amplitude limiting operation, and the output of the phase comparator 22 is continuously monitored. Here, instead of always performing the amplitude limiting operation in a state of being locked to the reproduction horizontal synchronizing signal, the amplitude limiting operation may be performed only during operations such as vertical blanking period, video disk player scanning and searching, and track jump. . When the output of the phase comparator 22 exceeds the predetermined range W ₂ after locking to the playback horizontal sync signal, from that time
If the phase error does not fall within the predetermined range W ₃ consecutively within n ₃ · H times n ₄ times, it is considered to be out of lock, and in this case also, the selector 21 is switched to the a side to set the reference horizontal synchronizing signal as the synchronization target.
These ranges W ₁ , W ₂ , W ₃ (including the case of the reference horizontal synchronizing signal) may be different from each other, but the same value is set, and
n ₃ and n ₄ have the same values as n ₁ and n ₂ , respectively.
Control within 20 becomes easy.

In the state of being locked to the reproduction horizontal synchronizing signal, a predetermined range W ₄ (for example, ± 0.1 °) in which the color burst signal is input and the output of the phase comparator 22 is narrower than the predetermined range W ₁ used for the lock determination. ), The control circuit 20 switches the selector 26 to the b side to switch the phase comparator.
The phase comparator before switching the selector 26 so that the phase error between the color burst signal and the clock of the color subcarrier frequency f _sc obtained by dividing the output of the VCO 30 is selected while the output of 27 is selected. The output phase of the N ₃ divider 33 is selected according to the value of 27. It should be noted that the selector 26 may be left at the side a without switching during the vertical blanking period, the search of the video disc player, or immediately after the track jump.

After setting the selector 26 to the b side, the control circuit 20 monitors the output of the phase comparator 27, and after switching the selector 26,
If the phase error n ₆ continues within a predetermined range W ₅ (for example, + 21 ° to −22.5 ° at the phase of f _sc ) within n ₅ · H, it is considered as lock, and if it does not enter, it is considered as lock impossible. Selector
Switch 26 to the a side, and try again from the state locked to the playback horizontal sync signal. When locked to the color burst signal, the output of the phase comparator 27 is continuously monitored and
If the output of 27 exceeds the predetermined range W ₆ and the phase error does not fall within the predetermined range W ₇ n ₈ times continuously within n ₇ · H from that point, it is regarded as unlocked, and the same as when lock is impossible. , The selector 26 is switched to the side a. Further, the control circuit 20 monitors the output of the phase comparator 22 even when the selector 26 is on the b side, and also switches the selector 26 to the a side when it is determined that the lock is disengaged with respect to the reproduction horizontal synchronizing signal.

Here, n _{5 to} n ₈ may have different values, but as described above, it is preferable that n ₅ and n ₇ have the same value as n ₁ and n ₆ and n ₈ have the same value as n ₂ . Also, it is better that W ₅ , W ₆ , and W ₇ have the same value, but W ₃ is different.
This is because the reproduction horizontal synchronization signal and the color burst signal have the same period (= 1H) for phase comparison, but the frequency of the phase comparison signal is different.

In the normal reproduction state, it remains locked to the color burst signal, but as described above, the vertical blanking period,
When searching the video disc player, immediately after a track jump, or when reproducing a portion without a color burst, the selector 26 may be returned to the side a and the object of locking may be switched to the reproduction horizontal synchronizing signal. Further, when locked to the color burst signal, the selector 24 is switched to the b side to select the output of the adder 23. At this time, the control circuit 20 calculates and averages the phase difference between the output of the phase comparator 27 and the output of the phase comparator 22, and then uses this as the other input of the adder 23. As a result, the output of the adder 23 becomes a value approximately equal to the phase error of the color burst signal by adding the offset to the phase error of the reproduction horizontal synchronization signal, and the selector 26 reproduces the PLL lock target with the color burst signal. At the moment of switching to the horizontal sync signal, a large phase error is not input to the loop filter 28.
Does not become unstable.

As described above, in the state where the PLL synchronizes the color burst signal with the synchronization target, the phase difference between the color burst signal and the reproduction horizontal synchronization signal is detected from the outputs of the phase comparator 27 and the phase comparator 22. Then, the output of the phase comparator 22 is corrected so that the output of the adder 23 becomes almost equal to the output of the phase comparator 27 by setting the other input of the adder 23 to the color burst target of the PLL synchronization. When switching between the signal and the reproduction horizontal synchronizing signal, a large phase error is not generated, so that the clock of the VCO 30 is also stable and synchronization disorder is not generated after the switching.

Further, since the calculated correction values of the phase difference are averaged, even if the output of the phase comparator 22 suddenly becomes large due to a false reproduction horizontal synchronization signal caused by undetected dropout, etc. Can be minimized.

In the above embodiment, the case where the signal processing is digitally applied to the PLL circuit has been described, but the present invention is also applicable to the PLL circuit that performs the signal processing in an analog manner. However, the present invention is particularly suitable for a PLL circuit that performs signal processing digitally because digital processing can more accurately perform addition / subtraction arithmetic processing and the like.

As described above, according to the synchronization method of the present invention, in the PLL circuit that generates the clock synchronized with the reproduced video signal, the PLL makes the color burst signal the synchronization target and is synchronized with this. By calculating the phase difference between the color burst signal and the reproduction horizontal synchronization signal, and correcting the phase error of the reproduction horizontal synchronization signal based on this phase difference,
Since a large phase error does not occur when the synchronization target is switched, the VCO clock is also stable, and the synchronization disorder does not occur after the switching.

[Brief description of drawings]

FIG. 1 is a block diagram of a video signal reproducing apparatus having a PLL circuit to which the synchronizing method of the present invention is applied, and FIG. 2 is a block diagram showing a concrete configuration of the PLL circuit in FIG. Explanation of main part code 8 …… Signal separation circuit, 9 …… PLL circuit 10 …… Reference signal generation circuit 11 …… Buffer memory 20 …… PLL control circuit 21,24,26 …… Selector 22,27 …… Phase Comparator 28 …… Loop filter 31,32,33 …… Frequency divider

Claims (2)

[Claims] 1. A color burst signal is generated when a color burst signal is extracted from the reproduced video signal while generating a clock in synchronization with a reproduced horizontal synchronizing signal extracted from the reproduced video signal reproduced from a recording medium. A method for synchronizing a PLL circuit for generating a clock synchronized with the color burst signal, wherein a phase difference between the color burst signal and the reproduction horizontal synchronization signal is obtained during an operation for generating a clock synchronized with the color burst signal, When the clock generation operation synchronized with the signal is switched to the clock generation operation synchronized with the reproduction horizontal synchronization signal, a phase error of the reproduction horizontal synchronization signal with respect to a predetermined phase comparison signal is corrected by the phase difference. PLL circuit synchronization method. 2. The method of synchronizing a PLL circuit according to claim 1, wherein the phase difference is averaged, and the phase error is corrected by the averaged phase difference.