JPS63280592A - Pull-in method for pll circuit - Google Patents

Abstract

PURPOSE:To attain stable pull-in in a short time by resetting a loop filter so that the oscillating frequency of a voltage-controlled oscillator of the PLL circuit is nearly equal to the frequency at the synchronization after power application of a video signal reproducing device obtaining a reproducing video signal and before the start of operation of pull-in. CONSTITUTION:When the object of synchronization is switched from the reproduced horizontal synchronizing signal into a reference horizontal synchronizing signal after power application of a video signal reproducing device and before the pull-in operation start or the object of synchronization is a reference synchronization signal and the pull-in is disabled, then the loop filter 28 is reset so that the oscillating frequency of a voltage-controlled oscillator 30 in the PLL circuit 9 is nearly equal to the frequency at the time of synchronization. Thus, the pull-in is applied stably in a short time.

Description

TECHNICAL FIELD The present invention relates to a synchronization pull-in method for a PLL circuit, and more particularly to a synchronization pull-in method for a PLL circuit that generates a clock synchronized with a reproduced video signal.

Background Art Video signal reproducing devices such as video disc players and VTRs are configured to control rotational systems such as spindle motors based on a reference horizontal synchronization signal generated within the device. Although the video signal includes jitter (time axis fluctuation), it is on average synchronized with the reference horizontal synchronization signal. Therefore, if the PLL circuit that generates a clock synchronized with the reproduced video signal is synchronized with the reference horizontal synchronization signal before synchronizing with the reproduced video signal, synchronization with the reproduced video signal can be easily achieved in a short time and reliably. You will be able to pull it in. In addition, when the video signal is being regenerated stably, phase errors can be detected with higher accuracy using the color burst signal than the reproducing horizontal synchronization signal, so P
It is preferable to synchronize the LL circuit with the color burst signal.

By the way, in a PLL circuit, if the initial frequency error from the human input signal at the time of starting synchronization pull-in is large, the time required for synchronization pull-in becomes long. In particular, if the phase comparator in the PLL circuit has a trapezoidal phase comparison characteristic with a narrow dynamic range to reduce the number of output bits, synchronization may be impossible if the initial frequency error is large. It may happen.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a method for locking in synchronization for a PLL circuit that can perform locking in synchronization stably and in a short time.

The synchronization pull-in method for a PLL circuit according to the present invention is such that a PLL circuit that generates a clock synchronized with a reproduced video signal including a horizontal synchronization signal and a color burst signal obtained from a recording medium is synchronized after the video signal reproducing device is powered on. During the period before the pull-in operation starts, when the synchronization target is switched from the reproduced horizontal synchronization signal to the reference horizontal synchronization signal, or when the synchronization target is the reference horizontal synchronization signal and the synchronization pull-in becomes impossible, It is characterized in that the loop filter is reset so that the oscillation frequency of the voltage controlled oscillator in the PLL circuit is approximately equal to the frequency at the time of synchronization.

Example Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram of a video signal reproducing apparatus having a PLL circuit according to the present invention and having a configuration in which, for example, signal processing is performed digitally. In the figure, an FM video signal read from a recording medium such as a video disc is supplied to an A/D converter 2 via an analog LPF (low pass filter) 1.

LPFI is for removing aliasing distortion in A/D conversion. The digitized FM video signal output from the A/D converter 2 is supplied to a digital BPF (band pass filter) 3. This digital BP
F3 extracts only the components necessary for detecting the video signal from the A/D conversion output that also includes the FM audio signal, and supplies the extracted components to the FM detection circuit 4 at the next stage. As the FM detection circuit 4, for example,
The structure proposed by the present applicant in Japanese Patent Application No. 59-262481 may be used. From the detection output of the FM detection circuit 4, only the baseband component of the video signal is extracted by the video LPF 5.

A dropout detection circuit 6 is provided for detecting dropout of the video signal. This dropout detection circuit 6 has a level comparator configuration, for example, and detects that the signal level of the square signal of the envelope component of the digitized FM video signal in the FM detection circuit 4 has become below a predetermined value, and performs dropout. Outputs a detection signal.

The digitized video signal that has passed through the video LPF 5 is supplied to a dropout correction circuit 7 and a signal separation circuit 8. The dropout correction circuit 7 performs dropout correction in response to the dropout detection signal supplied from the dropout detection circuit 6.

The signal separation circuit 8 separates signals such as a horizontal synchronization signal and a color burst signal contained in the digitized video signal and supplies them to the PLL circuit 9. The PLL circuit 9 generates a clock synchronized with the reproduced video signal, and its synchronization targets include the reproduced horizontal synchronization signal from the signal separation circuit 8, the color burst signal, and the reference horizontal synchronization signal from the reference signal generation circuit 10. 3 signals are input, and based on these signals, 4 fsc (fsc is the color subcarrier frequency) and 4
N+ fsc (N+ is an integer greater than or equal to 2, for example 3
) generates a clock. This 4fsc and 4N+fS
The clock of C is used as a clock for digital signal processing, and the sampling clock of A/D converter 2 and the clock of signal processing up to video LPF 5 are used as 4N+.
fsc, and downsampling is performed from the output of the video LPF 5 to a clock of 4 fsc. Further, in the signal separation circuit 8, the 4fSC clock is used as a sampling clock for the reproduced horizontal synchronization signal and the color burst signal.

The digitized video signal output from the dropout correction circuit 7 is written into the buffer memory 11 using a 4fsc clock generated by the PLL circuit 9. Data is read from the buffer memory 11 using a 4fsc reference clock generated by the reference signal generation circuit 10.

In this way, by reading data from the buffer memory 11 using a stable reference clock that is unrelated to the reproduced video signal, jitter in the reproduced video signal can be absorbed.

The digitized video signal read from the buffer memory 11 is converted into an analog signal by the D/A converter 12 and becomes a reproduced video output.

FIG. 2 is a block diagram showing a specific configuration of the PLL circuit 9 to which the synchronization pull-in method of the present invention is applied. In the figure, a reproduced horizontal synchronizing signal (PB 11) separated from a reproduced video signal by a signal separation circuit 8 and a reference signal generating circuit 1
The reference horizontal synchronization signal (REP H) generated at P
The selector 21 is switched and controlled by the LL control circuit 20, and is operated by two people. The reproduction horizontal synchronization signal or reference horizontal synchronization signal selected by the selector 21 is supplied to the control circuit 20 and the first phase comparator 2
2 will become a single person's strength. The comparison output of the phase comparator 22 is supplied to the control circuit 20 and becomes the input power of the adder 23 and selector 24. The selector 24 is switched and controlled by the control circuit 20. This selector 2
The selection output of No. 4 is supplied to the limiter 25. Limiter 2
5 is configured to selectively perform an amplitude limiting operation on an input signal, and the selection control is performed by a control circuit 20.
It is carried out by The output of limiter 25 is selector 2
6 becomes a single person's strength.

On the other hand, the color burst signal (CB) separated from the reproduced video signal by the signal separation circuit 8 becomes the sole power of the second phase comparator 27. The comparison output of this phase comparator 27 is supplied to the control circuit 20 and serves as an oil input to the selector 26. The selector 26 is switched and controlled by the control circuit 20. The selection output of this selector 26 is PL
The signal is supplied to a loop filter 28 for determining the loop characteristics of L. The loop filter 28 is a digital filter configured to achieve desired characteristics, and its output is converted to an analog voltage by a D/A converter 29 and sent to the VCO.
(Voltage controlled oscillator) 30 control voltage. VCO30
The oscillation frequency is controlled by the output voltage of the D/A converter 29, and its output becomes the master clock fM of this circuit, and is also connected to the N2 frequency divider 32 and N2 frequency divider 32 via the N1 frequency divider 31.
The signal is supplied to the frequency divider 33 and the control circuit 20. N
The output of the 2 frequency divider 32 becomes the oil input of the phase comparator 22,
Further, the output of the N3 frequency divider 33 serves as an oil input to the phase comparator 27, and a PLL is formed by the above.

The N1 frequency divider 31 reproduces the master clock fM and converts it into a sampling clock 4 for horizontal synchronization signals and color burst signals.
This is for frequency division up to fsc, for example fM-16
If it is fsc, it will be N1-4. N2 frequency divider 32 is N
This is for dividing the output (fM/N, +) of the 1 frequency divider 31 to the horizontal scanning frequency f+, which is N2-910 in the NTSC system. N3 frequency divider 33 is N1 frequency divider 31
This is for frequency-dividing the output (fM/N+) of 1 to the color subcarrier frequency fsc, and when fM/N+ -4fsc, it becomes N3-4.

The PLL control circuit 20 includes a flip-flop and a PLL control circuit 20.
L A (Programmable Logic A
An initial reset signal (IR8T) that is generated when the power is turned on, a vertical blanking signal (VBLX) that indicates the vertical blanking period, and a search or visual scan. The selector 21,
24 and 26, selection of the amplitude limiting operation of the limiter 25, resetting the loop filter 28, that is, setting it to its initial state, and resetting the frequency dividers 32 and 33. Note that the loop filter 28 is reset by setting each register in the digital filter to a predetermined value.

Next, the procedure of the synchronization pull-in method according to the present invention executed by the PLL control circuit 20 will be explained along the flowchart of FIG.

When the power is turned on or when no video signal is input, the PL
The L control circuit 20 receives an initial reset signal (IR9T
), the selector 21 is set to the a side to select the reference horizontal synchronizing signal, the selector 24 is set to the a side to select the comparative output of the phase comparator 22, and the limiter 25 is not set to the amplitude limiting state but is set to through, The output of the limiter 25 is selected by setting the selector 26 to the a side. In addition, the oscillation frequency of the VCO 30 is unstable immediately after the power is turned on.
Since the initial frequency error with the reference horizontal synchronizing signal may be large, the loop filter 28 is reset so that the initial frequency of the VCO 30 is approximately equal to the frequency at the time of PLL lock, and the initial phase of the two manual inputs of the phase comparator 22 is reset. The N2 frequency divider 32 is connected to the control circuit 20 so that the error becomes 0.
(step S1). After these resets are released, the PL
L starts synchronization pull-in to the reference horizontal synchronization signal selected by the selector 21 (step S2).

The phase comparator 22 digitally detects the phase error between the horizontal scanning frequency fH clock obtained by dividing the output of the VCO 30 and the reference horizontal synchronizing signal.

The detected value is input to the loop filter 28 via the selector 24, limiter 25, and selector 26. The output of the loop filter 28 is converted into an analog signal by two D/A converters and becomes a control voltage for the VCO 30. The control circuit 2o monitors the output of the phase comparator 22, and detects that the phase error occurs 02 times (for example, 4 times) consecutively within nl H (for example, n+-16, H is the horizontal scanning period) from the start of synchronization pull-in. When the angle falls within the range W+ (for example, +1.2 to -1.6 degrees), it is considered that the lock is established (step S3). Step S1
If step S3 is entered via step S2, the oscillation frequency of the VCO 30 is set close to the locking frequency, so locking will not become impossible.

After determining that synchronization is achieved in step S3, the control circuit 2o passes through step S4, which will be described later, and then selects the selector 21.
is switched to the b side to select the reproduced horizontal synchronizing signal, and the N2 frequency divider 32 is reset by the reproduced horizontal synchronizing signal (step S5), so that the initial phase error of the phase comparator 22 with respect to the reproduced horizontal synchronizing signal becomes 0. do it like this.

As in the case of the reference horizontal synchronization signal, the control circuit 20 releases the reset of the N2 frequency divider 32 and starts synchronization pull-in to the reproduced horizontal synchronization signal, and the phase comparator 22
The output is monitored and it is determined whether the locking conditions are satisfied (step S6).

As a result of the determination, if the locking conditions are not satisfied, locking is disabled, and the control circuit 20 returns to step S2, switches the selector 21 to the a side again, selects the reference horizontal synchronizing signal, and resets the N2 frequency divider 32. . After this, lock determination is performed again for the reference horizontal synchronization signal (step S3), but in this case, in step 6, the VCO
In some cases, the oscillation frequency of 30 has deviated significantly, making it impossible to lock. In that case, the process returns to step S1, returns to the initial state after power-on, and sets and resets each part. Note that the conditions for determining lock and lock failure may be the same for the reference horizontal synchronization signal and the reproduced horizontal synchronization signal, or may be stationary (for example, the values of nl, 02 and range W1 are changed).

In the case of the reference horizontal sync signal, the signal itself is stable with no fluctuations, so there is no problem in using a simpler judgment condition, but if it is the same as the reproduced horizontal sync signal, the control in the control circuit 20 will be easier. becomes easier.

When the selector 21 is set to the b side, if it is determined that it is locked to the reproduced horizontal synchronizing signal (step S6), the control circuit 20 causes the limiter 25 to perform an amplitude limiting operation and continues monitoring the output of the phase comparator 22.

Here, instead of always performing the amplitude limiting operation while locked to the playback horizontal synchronization signal, it may be possible to perform the amplitude limiting only during the vertical blanking period, during operations such as video disc player scanning, searching, and track jumping. . After locking to the reproduced horizontal synchronization signal, if the output of the phase comparator 22 exceeds the predetermined range W2, from that point on
If the phase error does not fall within the predetermined range W3 n4 times in a row within 3ΦH, it is considered that the lock has been released (step S7), and in this case, as in step S6, the process returns to step S2 and the selector 21 is switched to the a side to set the reference level. The synchronization signal is the target of synchronization. Note that returning to step S2 from step S6 or step S7 and switching the synchronization target from the reproduced horizontal synchronizing signal to the reference horizontal synchronizing signal occurs when synchronization cannot be achieved or synchronization is lost with respect to the reproduced horizontal synchronizing signal. Since there is a possibility that the oscillation frequency of the VCO 30 has shifted significantly, as shown by the dotted line in Fig. 3, the synchronization target is changed from the reproduced horizontal synchronization signal by returning to step S1 instead of returning to step S2. The loop filter 28 may be reset when switching to the reference horizontal synchronization signal. In this way, the loop filter 28 will always be reset when entering step S3, so
Unlocking in step S3 and unlocking in step S4 no longer occur. Therefore, steps S3 and S4 may be omitted to simply provide a period of time before locking. The predetermined ranges W, , W2, and W3 (including the case of the reference horizontal synchronization signal) may be different, but they should be the same value, and n3 and n4 are also n+ and n, respectively.
If the value is the same as 2, control within the control circuit 20 becomes easier.

When locked to the reproduction horizontal synchronization signal, the color burst signal is input and the output of the phase comparator 22 is in a range W that is narrower than the predetermined range used for lock determination.
a (for example, ±0.1"), the control circuit 20 switches the selector 26 to the b side to select the output of the phase comparator 27 (step S8), and at the same time
Color subcarrier frequency fSC obtained by dividing the output of CO30
The phase comparator 27 before the selector 26 switches so that the phase error between the clock and the color burst signal is minimized.
The output phase of the N3 frequency divider 33 is selected according to the value of . Note that during the vertical blanking period, during a video disc player search, or immediately after a track jump, the selector 26 may be left on the a side without switching.

After setting the selector 26 to the b side, the control circuit 20 monitors the output of the phase comparator 27, and within n5·H after switching the selector 26, the phase error continues n6 times within a predetermined range WS (for example, fSC +21″~-22 in phase
,5@), it is considered to be locked and step S9),
If it does not, it is assumed that locking is impossible, and the process returns to step S5, switches the selector 26 to side a, and starts over from the state locked to the reproduction horizontal synchronizing signal. When locked to the color burst signal, the output of the phase comparator 27 is continuously monitored, and the output of the phase comparator 27 exceeds the predetermined range W6, and within nl·H from there, the phase error continues n8 times within the predetermined range. W
If it does not fall within 7, it is assumed that the lock is unlocked and proceed to step 5.
10) As in the case where the lock is disabled, return to step S5 and switch the selector 26 to the a side. The control circuit 20 also monitors the output of the phase comparator 22 when the selector 26 is on the b side, and if it determines that it is out of lock with respect to the reproduced horizontal synchronization signal (step 511), it similarly returns to step S5. switch the selector 26 to the a side.

Here, n5 to n8 may be different values, but as described above, n5. It is better for nl to have the same value as nl, and for nB and nB to have the same value as n2. Also, Ws.

It is better for w6 and w to be the same value, but different from w3.

This is because the reproduction horizontal synchronization signal and the color burst signal have the same phase comparison period (-1H), but the frequencies of the phase comparison signals are different.

In normal playback conditions, it remains locked to the color burst signal, but as mentioned above, during the vertical blanking period, when searching for a video disc player, immediately after a track jump, and during playback of a portion without color burst, the selector 26 It is also possible to return the signal to side a and switch the lock target to the reproduction horizontal synchronization signal. Further, in a state locked to the color burst signal, the selector 24 is switched to the b side to select the output of the adder 23.

At this time, the control circuit 20 calculates the phase difference between the output of the phase comparator 27 and the output of the phase comparator 22, averages it, and uses this as the output of the adder 23. As a result, the output of the adder 23 becomes a value approximately equal to the phase error of the color burst signal by adding an offset to the phase error of the reproduced horizontal synchronization signal, and the selector 26 sets the PLL lock target to the color burst signal and the reproduced signal. Since no large phase error is input to the loop filter 28 at the moment of switching between the horizontal synchronizing signal and the horizontal synchronizing signal, the PLL does not become unstable before and after switching.

The series of operations described above are repeated until it is determined in step S12 that the playback has ended.

Note that the reference horizontal synchronization signal is a stable signal and will not go out of synchronization once it is synchronized, so the determination in step S4 in FIG. 3 can be omitted. Further, if the switching of the synchronization target from the reproduction horizontal synchronization signal to the color burst signal is performed immediately after synchronization with the reproduction horizontal synchronization signal, the judgment in step S7 is not necessary. If the switching to the color burst signal is performed when a predetermined condition is satisfied after synchronizing with the signal, the judgment in step S7 is inserted because the synchronization of the reproduced horizontal synchronization signal may be disrupted during that time. There is.

In this way, during the period after the power is turned on and before the synchronization pull-in operation starts, when the target of synchronization is switched from the reproduced horizontal synchronization signal to the reference horizontal synchronization signal, or when the target of synchronization is the reference horizontal synchronization signal and its synchronization pull-in When it becomes impossible,
Even if the oscillation frequency of the VCO 30 deviates significantly, the loop filter 28 is reset and the oscillation frequency of the VCO 30 is changed to P.
By setting the value to approximately the center value during LL synchronization, the initial frequency error can be reduced, so that synchronization of the PLL can be performed stably and in a short time.

Furthermore, since the loop filter 28 is composed of a digital filter, the output value of the digital filter is determined so that the oscillation frequency of the VCO 30 becomes approximately the center value at the time of PLL synchronization, and each register within the digital filter is determined. By setting the respective output values to predetermined values, the loop filter 28 can be reset accurately and easily.

It should be noted that although the present invention is applicable even when the loop filter has an analog configuration, a digital configuration is more accurate and easier to implement.

As described in detail, according to the synchronization pull-in method according to the present invention, a PLL that generates a clock synchronized with a reproduced video signal
In the circuit, during the period after the power is turned on and before the synchronization pull-in operation starts, when the target of synchronization is switched from the reproduced horizontal synchronization signal to the reference horizontal synchronization signal, or when the target of synchronization is the reference horizontal synchronization signal and the synchronization pull-in is When this becomes impossible, the initial frequency error can be reduced by setting the VCO oscillation frequency to approximately the center value at PLL synchronization.
Synchronous pull-in can be performed stably and in a short time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a video signal reproducing device having a PLL circuit according to the present invention, FIG. 2 is a block diagram showing a specific configuration of a PLL circuit to which the synchronization pull-in method according to the present invention is applied, and FIG. 3 is a flowchart showing the steps of a synchronization pull-in method according to the present invention executed by the PLL control circuit of FIG. 2; Explanation of symbols of main parts

Claims (3)

[Claims] (1) A method for synchronizing a PLL circuit that generates a clock synchronized with a reproduced video signal including a horizontal synchronization signal and a color burst signal obtained from a recording medium, the power source of a video signal reproducing device that obtains the reproduced video signal. A synchronous pull-in of a PLL circuit characterized in that a loop filter is reset so that the oscillation frequency of the voltage controlled oscillator in the PLL circuit becomes approximately equal to the frequency at the time of synchronization during a period after the input and before the start of the synchronous pull-in operation. Method. (2) A synchronization pull-in method for a PLL circuit that generates a clock synchronized with a reproduced video signal including a horizontal synchronization signal and a color burst signal obtained from a recording medium, the time of a video signal reproducing device that obtains the reproduced video signal. When a reference horizontal synchronization signal serving as a reference or a reproduced horizontal synchronization signal separated from the reproduced video signal is used as a synchronization target, and the target of synchronization is switched from the reproduced horizontal synchronization signal to the reference horizontal synchronization signal, in the PLL circuit. A method for synchronizing a PLL circuit, comprising resetting a loop filter so that the oscillation frequency of a voltage controlled oscillator becomes approximately equal to the frequency at the time of synchronization. (3) A synchronization pull-in method for a PLL circuit that generates a clock synchronized with a reproduced video signal including a horizontal synchronization signal and a color burst signal obtained from a recording medium, the time of a video signal reproducing device that obtains the reproduced video signal. A reference horizontal synchronization signal serving as a reference is a target of synchronization, and when synchronization to the reference horizontal synchronization signal becomes impossible, the oscillation frequency of the voltage controlled oscillator in the PLL circuit becomes approximately equal to the frequency at the time of synchronization. A synchronous pull-in method for a PLL circuit, characterized by resetting a loop filter.