JPS63286081A - Method for controlling pll circuit - Google Patents

Abstract

PURPOSE:To contrive to stabilize the synchronization of a PLL by applying an amplitude limiting to a phase error within a prescribed range if the phase error of a regenerative horizontal synchronizing signal exceeds the prescribed range in using the regenerative horizontal synchronizing signal separated from an FM regenerative video signal as an object of synchronization while a PLL circuit locks thereto. CONSTITUTION:In throwing a selector 21 to the position (b), when it is discriminated to be locked to the regenerative horizontal synchronizing signal, a control circuit 20 allows a limiter 25 to apply amplitude limit and keeps monitoring the output of a phase comparator 22. When the PLL uses the regenerative horizontal synchronizing signal as an object of synchronization and is synchronized therewith, no large phase error is caused in the phase comparator 25. In case caused, because it is due to a dropout not being detected, the limiter 25 limits it. That is, if the phase error reaches a value being the upper limit or over or the lower limit or below the range of the amplitude limiting, the error is replaced respectively by the upper limit or the lower limit thereby preventing a large phase error from being given to a loop filter 28, then a large fluctuation in the oscillated frequency from a VCO 30 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of controlling a PLL circuit, and in particular to a control method of a PLL circuit that generates a clock for digitizing an FM playback video signal in synchronization with the FM playback video signal. This relates to a control method.

Video signal reproducing devices such as small video disc players and VTRs are configured to control rotational systems such as spindle motors based on a reference horizontal periodic signal generated within the device. Although the reproduced video signal includes jitter (time axis fluctuation), it is on average synchronized with the reference horizontal periodic signal. Therefore, if the PLL circuit that generates a clock synchronized with the reproduced video signal is synchronized with the reference horizontal period signal before synchronizing with the reproduced video signal, the synchronization with the reproduced horizontal period signal included in the reproduced video signal can be synchronized. It will be easier and you will be able to reliably pull it in in a short time.

Incidentally, when the PLL is synchronized with the reproduced horizontal period signal, if a false reproduced horizontal period signal is generated due to undetected dropout, the phase error of the reproduced horizontal period signal may vary greatly.

If this large phase error is directly input to the loop filter, the oscillation frequency of the VCO (voltage controlled oscillator) in the PLL circuit will instantly change greatly, causing the PLL to become unstable or lose synchronization. In particular, the FM playback video signal is
When digitizing with a CO clock, if the clock frequency changes instantaneously, a drastic level fluctuation will occur in the FM-detected video signal, which will also have a negative effect on the separation of periodic signals, and the reproduced horizontal periodic signal will be distorted. It may become undetectable, and the influence on PLL, rotation system servos, etc. is even greater.

Further, when the video signal reproducing device performs one-time playback during special playback such as still image playback, if there is a skew (time difference) between tracks, a large phase error will occur when jumping. Therefore, the same problem as described above will occur in this case as well.

1匪五且1 The present invention is notable for the above-mentioned points, and even if there is undetectable dropout or skew between tracks, sudden level fluctuations will not occur in the FM-detected video signal. An object of the present invention is to provide a method for controlling a PLL circuit as described above.

A method for controlling a PLL circuit according to the present invention is a PLL circuit that generates a clock for digitizing an FM reproduced video signal in synchronization with the FM reproduced video signal, and synchronizes with the reproduced horizontal periodic signal. The present invention is characterized in that when the phase error of the reproduced horizontal periodic signal exceeds a predetermined range in a state in which the phase error is within the predetermined range, the amplitude of this phase error is limited to within the predetermined range.

Branch-1 Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram of a video signal reproducing apparatus having a PLL circuit according to the present invention and having a configuration in which, for example, signal processing is performed digitally. In the figure, an FM video signal read from a recording medium such as a video disc is an analog L
A/D converter 2 via PF (low pass filter) 1
is supplied to

LPFl is for removing aliasing distortion in A/D conversion. The digitized FM video signal output from the A/D converter 2 is supplied to a digital BPF (band pass filter) 3. This digital BP
F3 extracts only the components necessary for detecting the video signal from the A/D conversion output including the FM sound and body sounds, and supplies the extracted components to the FMM wave circuit 4 at the next stage. As the FMM wave circuit 4, for example,
The structure proposed by the present applicant in Japanese Patent Application No. 59-262481 may be used. From the detection output of the FMM wave circuit 4, only the baseband component of the video signal is extracted by the video LPF 5.

A dropout detection circuit 6 is provided for detecting dropout of the video signal. This dropout detection circuit 6 has a level comparator configuration, for example, and detects that the signal level of the square signal of the envelope component of the digitized FM video signal in the FMM wave circuit 4 has become below a predetermined value, and performs dropout. Outputs a detection signal.

The digitized video signal that has passed through the video LPF 5 is supplied to a dropout correction circuit 7 and a signal separation circuit 8. The dropout correction circuit 7 performs dropout correction in response to the dropout detection signal supplied from the dropout detection circuit 6.

The signal separation circuit 8 separates signals such as horizontal periodic signals and color burst signals contained in the digitized video signal and supplies them to the PLL circuit 9. The PLL circuit 9 generates a clock synchronized with the reproduced video signal, and its synchronization targets include the reproduced horizontal period signal from the signal separation circuit 8, the color burst signal, and the reference horizontal period signal from the reference signal generation circuit 10. 3 signals are input, and based on these signals, 4fsc (fsc is color subcarrier frequency) and 4N+
fsc <N+ is an integer of 2 or more, for example, 3) clocks are generated. These 4fsc and 4N+fsc clocks are used as clocks for digital signal processing.
c, and down-samples the video to a 4fsc clock from the output of PF5. Further, in the signal separation circuit 8, the 4fSC clock is used as a sampling clock for the reproduced horizontal period signal and the color burst signal.

The digitized video signal output from the dropout correction circuit 7 is written into the buffer memory 11 using a 4f'sc clock generated by the PLL circuit 9. Data is read from the buffer 7 memory 11 using a 4fsc reference clock generated by the reference signal generation circuit 10.

In this way, by reading data from the buffer memory 11 using a stable reference clock unrelated to the reproduced video signal, jitter in the reproduced video signal can be absorbed.

The digitized video signal read from the buffer memory 11 is converted into an analog signal by the D/A converter 12 and becomes a reproduced video output.

FIG. 2 is a block diagram showing a specific configuration of the PLL circuit 9 to which the control method of the present invention is applied.

In the figure, the reproduced horizontal period signal (PaN) separated from the reproduced video signal by the signal separation circuit 8 and the reference horizontal period signal (REFI) generated by the reference signal generation circuit 10 are
The selector 21 is switched and controlled by the PLL control circuit 20, and is operated by two people.

The reproduced horizontal period signal or reference horizontal period signal selected by the selector 21 is supplied to the control circuit 20 and becomes the sole power of the first phase comparator 22 . The comparison output of the phase comparator 22 is supplied to the control circuit 20 and becomes the input power of the numbing device 23 and the selector 24.

The selector 24 is switched and controlled by the control circuit 20.

The selected output of this selector 24 is supplied to a limiter 25. The limiter 25 is configured to selectively perform an amplitude limiting operation on the input signal, and the selection control is performed by the control circuit 20. When the signal level of the input signal becomes a value above the upper limit or below the lower limit of the limit range due to the amplitude limiting operation of the limiter 25, it is output as the upper limit or lower limit value, respectively. The output of the limiter 25 becomes the sole power of the selector 26.

On the other hand, the color burst signal (CB) separated from the reproduced video signal by the signal separation circuit 8 becomes the sole power of the second phase comparator 27. The comparison output of this phase comparator 27 is control 1
It is supplied to the call circuit 20 and serves as an input to the selector 26. The selector 26 is switched and controlled by the control circuit 20. The selection output of this selector 26 is P
The signal is supplied to a loop filter 28 for determining the loop characteristics of LL. The loop filter 28 is a digital filter configured to achieve desired characteristics, and its output is converted to an analog voltage by a D/A converter 29 and then applied to the VC.
This becomes the control tIl voltage of O30. The oscillation frequency of the VCO 30 is controlled by the output voltage of the D/A converter 29, and its output serves as the master clock fM of this circuit, as well as the NI
Via the frequency divider 31, the N2 frequency divider 32 and the N3 frequency divider 33
and is supplied to the control circuit 20. N2 division frequency division 32
The output of the N3 frequency divider 33 becomes the output of the phase comparator 22, and the output of the N3 frequency divider 33 becomes the output of the phase comparator 27, thus forming a PLL.

The N1 frequency divider 31 reproduces the master clock fM as a sampling clock 4 of the horizontal period signal and color burst signal.
This is to divide the frequency up to fsc, for example fM=16
If it is fsc, it will be N1-4. N2 frequency divider 32 is N
1 The output (fM/NI) of the frequency divider 31 is set to the horizontal scanning frequency t.
It is for dividing the frequency up to 'H, and is N2-910 in the NTSC system. N3 frequency divider 33 is N1 frequency divider 31
This is for frequency-dividing the output (fM/NI) of (fM/NI) to the color subcarrier frequency fsc, and when fM/N+=4fsc, it becomes N3-4.

The PLL control circuit 20 includes a flip-flop and p
l A (Programmable Logic A
An initial reset signal (IR3T) that is generated when the power is turned on, a vertical blanking signal (to VBL) that indicates the vertical blanking period, and a search or visual scan. The selector 21.2 uses control signals such as a scan signal (SCAM) indicating that the track is currently in progress, and a jump signal (JUMP) indicating that the track has been jumped to an adjacent track during special playback of still images, etc.
4. Switching of 26, selection of amplitude limiting operation of limiter 25, setting of loop filter 28 to initial state, frequency divider 3
Performs control such as resetting 2.33. Note that the loop filter 28 is set to the initial state by setting each register in the digital filter to a predetermined value.

Next, the procedure of the control method according to the present invention executed by the PLL control circuit 20 will be explained along the flowchart of FIG.

When the power is turned on or when no video signal is input, the PL
The L control l~roll circuit 20 receives the initial reset signal (IR3
T), etc., the selector 21 is set to the a side to select the reference horizontal period signal, the selector 24 is set to the a side to select the comparison output of the phase comparator 22, and the limiter 25 is set to the through state without being in the amplitude limiting state. , select the output of the limiter 25 by setting the selector 26 to the a side. In addition, immediately after the power is turned on, the loop filter 28 is set so that the initial frequency of the VCO 30 is set to the center value during PLL rotation, and the initial phase error between the two inputs of the phase comparator 22 is set to O. The N2 frequency divider 32 is connected to the control circuit 2.
Reset by the reference horizontal period signal via 0 (
Step 81). After these sets and resets are released, the PLL starts synchronizing with the reference horizontal periodic signal selected by the selector 21 (step 82).

The phase comparator 22 detects, as a digital value, the phase error between the clock having the horizontal scanning frequency fH obtained by dividing the output of the VCO 30 and the reference horizontal period signal.

The detected value is input to the loop filter 28 via the selector 24, limiter 25, and selector 26. The output of the loop filter 28 is converted into an analog signal by a D/A converter 29 and becomes a control voltage for the VCO 30. The control circuit 20 monitors the output of the phase comparator 22, and detects if the phase error occurs n2 times (for example, 4 times) consecutively within nl H (for example, n+=16, H is the horizontal scanning period) from the start of synchronization pull-in. When the angle falls within the range W+ (for example, +1.2 to -1.6 degrees), it is considered that the lock is established (step 83). If the video signal is being reproduced at this time, the control circuit 20 switches the selector 21 to the b side to select the reproduced horizontal periodic signal and selects the N2 frequency divider 3 after passing through step S4, which will be described later.
2 is reset by the reproduction horizontal periodic signal in step S.
5) The initial phase error of the phase comparator 22 is set to O with respect to the reproduced horizontal periodic signal.

As in the case of the reference horizontal period signal, the control circuit 20 releases the reset of the N2 frequency divider 32 and starts synchronization with the reproduced horizontal period signal, and the phase comparator 22
The output is monitored and it is determined whether the locking conditions are satisfied (step S6).

As a result of the determination, if the locking conditions are not satisfied, locking is disabled, and the control circuit 20 returns to step S2, switches the selector 21 to the a side again, selects the reference horizontal period signal, and resets the N2 frequency divider 32. . At this time, the loop filter 28 may also be set to the initial state. After this, the lock determination is performed again on the reference horizontal period signal (step S4), but if locking is not possible here as well, the process returns to step S1 to return to the initial state after the power is turned on and set each part. Perform a reset. In addition,
The conditions for determining lock and unlockability may be the same or different for the reference horizontal period signal and the reproduced horizontal period signal (for example, the value of nl+n2 and range W1 are changed). In the case of the reference horizontal period signal, the signal itself is stable with no jitter, so there is no problem in using a simpler judgment condition, but if it is the same as the reproduced horizontal period signal, control within the control circuit 20 will be easier. .

When the selector 21 is set to the b side, if it is determined that it is locked to the reproduced horizontal periodic signal (step S6), the control circuit 20 causes the limiter 25 to operate to limit the amplitude and continues monitoring the output of the phase comparator 22.

When the PLL synchronizes with the reproduced horizontal periodic signal and is synchronized with it, a large phase error will not occur in the phase comparator 25. Therefore, this is suppressed by the limiter 25. In other words, when the phase error becomes a value above the upper limit or below the lower limit of the amplitude limit range, by replacing it with the upper limit value or the lower limit value, respectively.
Since a large phase error is not input to the loop filter 28, large fluctuations in the launch frequency of the VCO 30 can be prevented. Note that even if PLI- is synchronized with the reproduced horizontal periodic signal, if it is not synchronized, if the limiter 25 performs amplitude limiting operation to limit the change in the oscillation frequency of the VCO 30, it will take time to pull in synchronization. Therefore, amplitude limitation on the phase error of the reproduced horizontal periodic signal is performed only when the PLL is locked to the reproduced horizontal periodic signal.

Here, instead of always performing the amplitude limiting operation locked to the playback horizontal periodic signal, the amplitude limiting operation is performed only during operations such as video disc player scanning, search, track dipping, and vertical blanking period of the playback video signal. You can do it as well. When scanning or searching,
Since a large number of track jumps occur irregularly, there is a high probability that undetected dropouts will occur, and the problem of skew between tracks also arises. Furthermore, during a track jump or during a vertical blanking period, a 1-to-rack jump for special playback such as still picture playback is performed, so there is a similar problem of skew. Therefore, it is necessary to limit the amplitude using the limiter 25 at least during scan, search, track jump, or vertical blanking period.

When the output of the phase comparator 22 exceeds the predetermined range W2 after the PIL locks to the reproduced horizontal periodic signal, from that time n
If the phase error does not fall within the predetermined range W3 n4 times in a row within 3.H, it is assumed that the lock has been released (step S7), and in this case also, the process returns to step S2 and the selector 21 is switched to the a side to output the reference horizontal period signal. to be synchronized. These ranges W1, W2 . W3 (including the case of the reference horizontal period signal) may be different from each other, but should be the same value, and n
3. Control within the control circuit 20 becomes easier if n4 has the same value as nl and n2, respectively.

In the state locked to the reproduced horizontal periodic signal, the color burst signal is input and the output of the phase comparator 22 is in a range W that is narrower than the predetermined range used for lock determination.
4 (for example, ±0.1°), the control circuit 20 switches the selector 26 to the b side to select the output of the phase comparator 27 (step $8), and at the same time the VCO
Divide the output of 30 (!Also, the color subcarrier frequency fSC
The phase comparator 27 before the selector 26 switches so that the phase error between the clock and the color burst signal is minimized.
The output phase of the N3 frequency divider 33 is selected according to the value of . It should be noted that during the vertical blanking period, during a video disc player search, or immediately after a 1-rack jump, the selector 26 may be left on the a side without being switched.

When the selector 26 is set to the b side, the control circuit 20 monitors the output of the phase comparator 27, and detects that the phase error is within a predetermined range Ws (for example, f' +21° to -22 in phase of sc,
5°), it is regarded as locked, and if not, it is regarded as impossible to lock, and the process returns to step $5, switches the selector 26 to side a, and starts over from the state locked to the reproduced horizontal periodic signal. When locked to the color burst signal, continue to monitor the output of the phase comparator 27,
The output of the phase comparator 27 exceeds the predetermined range W6, and within nl·H from there, the phase error continues n8 times within the predetermined range W.
If it does not fall within 7, it is assumed that the lock is unlocked and proceed to step 5.
10) As in the case where the lock is impossible, return to step S5 and switch the selector 26 to the a side. The control circuit 20 also monitors the output of the phase comparator 22 when the selector 26 is on the b side, and if it determines that it is out of lock with respect to the reproduced horizontal periodic signal (step 511), it similarly returns to step S5. switch the selector 26 to the a side.

Here, n5 to n8 may be different values, but as described above, n5. It is better for ny to have the same value as nl, and for n6 and n8 to have the same value as nl. Also, Ws.

It is better that We and Wy have the same value, but they are different from Ws.

This is because the reproduction horizontal period signal and the color burst signal have the same phase comparison period (=1H), but the frequencies of the phase comparison signals are different.

In normal playback conditions, it remains locked to the color burst signal, but as mentioned above, during the vertical blanking period, when searching for a video disc player, immediately after a track jump, and during playback of a portion without color burst, the selector 26 may be returned to side a and the lock target may be switched to the reproduction horizontal periodic signal. Further, in a state locked to the color burst signal, the selector 24 is switched to the b side to select the output of the adder 23.

At this time, the control circuit 20 controls the angle of the phase comparator 27.
After calculating and averaging the phase difference between the output and the output of the phase comparator 22, this is used as the output of the adder 23.

As a result, the output of the adder 23 becomes a value that is approximately equal to the phase error of the color burst signal by adding an offset to the phase error of the reproduced horizontal periodic signal, and the selector 26 sets the PLL lock target to the color burst signal and the reproduced signal. Since a large phase error is not input to the loop filter 28 at the moment of switching between the horizontal periodic signal and the horizontal periodic signal,
This prevents the PLL from becoming unstable before and after switching.

The series of operations described above are repeated until it is determined in step S12 that the playback has ended.

Note that the reference horizontal period signal is a stable signal and will not deviate once synchronized, so the determination in step S4 in FIG. 3 can be omitted. Furthermore, if the switching of the synchronization target from the reproduced horizontal period signal to the color burst signal is performed immediately after the synchronization to the reproduced horizontal period signal, the judgment in step S7 is not necessary. If the signal is synchronized and then switched to a color burst signal that satisfies a predetermined condition, the judgment in step $7 is inserted because the synchronization of the reproduced horizontal periodic signal may be disrupted during that time. -ing

In the above embodiment, a case has been described in which the present invention is applied to a PLL circuit that performs signal processing digitally, but it is also applicable to a PLL circuit that performs signal processing in an analog manner. However, digital processing allows the upper and lower limit values of the limiter 25 to be specified and the amplitude limiting operation to be performed more accurately, and therefore the present invention is particularly suitable for a PLL circuit that performs signal processing digitally.

As explained above, according to the control method according to the present invention,
In a PLL circuit that generates a clock for digitizing an FM playback video signal in synchronization with the FM playback video signal, the playback horizontal periodic signal is the target of synchronization, and the phase of the playback horizontal periodic signal is synchronized with this. When the error exceeds a predetermined range, by limiting the amplitude of this phase error within the predetermined range, even if there is undetectable dropout or skew between tracks, sudden level fluctuations can be prevented in the FM detected video signal. It never happens.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video signal reproducing device having a PLL circuit according to the present invention, and FIG. 2 is a block diagram showing a specific configuration of the PLL circuit to which the control method according to the present invention is applied.
FIG. 3 is a flowchart showing the procedure of the control method according to the present invention executed by the PLL control circuit of FIG. Explanation of symbols of main parts

Claims (4)

[Claims] (1) A method for controlling a PLL circuit that generates a clock for digitizing an FM reproduced video signal obtained from a recording medium in synchronization with the FM reproduced video signal, the method comprising:
The reproduction horizontal synchronization signal separated from the M reproduction video signal is the target of synchronization, and when the phase error of the reproduction horizontal periodic signal exceeds a predetermined range in a state where the PLL circuit is synchronized with this, the phase error is A method for controlling a PLL circuit, characterized in that the amplitude is limited within the predetermined range. (2) The amplitude limitation is carried out when the video signal reproducing device that obtains the FM reproduced video signal is searching for a designated image or reproducing an image while crossing a track at high speed. A method for controlling a PLL circuit according to claim 1. (3) The method for controlling a PLL circuit according to claim 1, wherein the amplitude limitation is performed when a video signal reproducing device that obtains the FM reproduced video signal performs a track jump. (4) The method for controlling a PLL circuit according to claim 1, wherein the amplitude limitation is performed during a vertical blanking period of the FM reproduced video signal.