JPS63280593A - Synchronization method for pll circuit - Google Patents

Abstract

PURPOSE:To prevent disturbance in synchronization after changeover by allowing a PLL to use a color burst signal as an object of synchronization, obtaining a phase difference between a color burst signal and a reproduced horizontal synchronization signal while being synchronized and correcting the phase error of the horizontal synchronizing signal based on the phase difference. CONSTITUTION:A signal separation circuit 8 separates a signal such as a horizontal synchronizing signal and a color burst signal included in a digitized video signal and gives the result to a PLL circuit 9. In the PLL circuit 9, the color burst signal is used as the object of synchronization and the phase difference between the color burst signal and the reproduced horizontal synchronizing signal is obtained in the synchronizing state and when the object of synchronization is switched from the color burst signal into the reproduced horizontal synchronizing signal, the phase error of the reproduced horizontal synchronizing signal with respect to the prescribed phase comparison signal is corrected and synchronized with the reproduced horizontal synchronizing signal based on the corrected phase error. Thus, the production of a large phase error is suppressed and the disturbance of the synchronization after changeover is eliminated.

Description

TECHNICAL FIELD The present invention relates to a method of synchronizing a PLL circuit, and more particularly to a method of synchronizing a PLL circuit that generates a clock synchronized with a reproduced video signal.

Background Art Video signal reproducing devices such as video disc players and VTRs are configured to control rotational systems such as spindle motors based on a reference horizontal synchronization signal generated within the device. Although the video signal includes jitter (time axis fluctuation), it is on average synchronized with the reference horizontal synchronization signal. Therefore, if the PLL circuit that generates a clock synchronized with the reproduced video signal is synchronized with the reference horizontal synchronization signal before synchronizing with the reproduced video signal, synchronization with the reproduced video signal can be easily achieved in a short time and reliably. You will be able to pull it in. In addition, when the video signal is being regenerated stably, phase errors can be detected with higher accuracy using the color burst signal than the reproducing horizontal synchronization signal, so P
It is preferable to synchronize the LL circuit with the color burst signal.

However, even when the PLL circuit is synchronized with the color burst signal, the synchronization target may be lost during vertical blanking periods, track jumps, search periods, or during playback of sections where there is no color burst signal in the playback video signal. It may be switched to the playback horizontal sync signal. When switching the synchronization target from the color burst signal to the reproduced horizontal sync signal or from the reproduced horizontal sync signal to the color burst signal, if the phase difference between the color burst signal and the reproduced horizontal sync signal is large, a large phase error will occur immediately after switching. This causes the clock of the PLL's VCO (voltage controlled oscillator) to fluctuate greatly, making the PLL unstable. In particular, when a signal obtained by FM modulating a video signal is subjected to AD conversion using a VCO clock, fluctuations in the clock result in fluctuations in the level of the FM-detected video signal, which also adversely affects the separation of synchronization signals.

Summary of the Invention The present invention has been made in view of the above-mentioned points, and it stabilizes the VCO clock by suppressing the occurrence of large phase errors when switching the synchronization target between the color burst signal and the reproduced horizontal synchronization signal. It is an object of the present invention to provide a method for synchronizing a PLL circuit that eliminates synchronization disturbance after switching.

A PLL circuit synchronization method according to the present invention is a PLL circuit that generates a clock synchronized with a reproduced video signal including a horizontal synchronization signal and a color burst signal obtained from a recording medium, and synchronizes with a color burst signal. In this state, the phase difference between the color burst signal and the reproduced horizontal sync signal is calculated, and when the synchronization target is switched from the color burst signal to the reproduced horizontal sync signal, the phase error of the reproduced horizontal sync signal with respect to a predetermined phase comparison signal is determined by the above position. It is characterized by correcting the phase difference and synchronizing with the reproduced horizontal synchronizing signal based on the corrected phase error.

Example Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram of a video signal reproducing apparatus having a PLL circuit according to the present invention and having a configuration in which, for example, signal processing is performed digitally. In the figure, an FM video signal read from a recording medium such as a video disc is an analog L
A/D converter 2 via PF (low pass filter) 1
is supplied to

LPFI is for removing aliasing distortion in A/D conversion. The digitized FM video signal output from the A/D converter 2 is supplied to a digital BPF (band pass filter) 3. This digital BP
F3 extracts only the components necessary for detecting the video signal from the A/D conversion output that also includes the FM audio signal, and supplies the extracted components to the FM detection circuit 4 at the next stage. As the FM detection circuit 4, for example,
The structure proposed by the present applicant in Japanese Patent Application No. 59-262481 may be used. From the detection output of the FM detection circuit 4, only the baseband component of the video signal is extracted by the video LPF 5.

A dropout detection circuit 6 is provided for detecting dropout of the video signal. This dropout detection circuit 6 has a level comparator configuration, for example, and detects that the signal level of the square signal of the envelope component of the digimorized FM video signal in the FM detection circuit 4 has become below a predetermined value, and performs dropout. Outputs a detection signal.

The digitized video signal that has passed through the video LPF 5 is supplied to a dropout correction circuit 7 and a signal separation circuit 8. The dropout correction circuit 7 performs dropout correction in response to the lower dropout detection signal supplied from the dropout detection circuit 6.

The signal separation circuit 8 separates signals such as a horizontal synchronization signal and a color burst signal contained in the digitized video signal and supplies them to the PLL circuit 9. The PLL circuit 9 generates a clock synchronized with the reproduced video signal, and its synchronization targets include the reproduced horizontal synchronization signal from the signal separation circuit 8, the color burst signal, and the reference horizontal synchronization signal from the reference signal generation circuit 10. 3 signals are input, and based on these signals, 4fsc (fsc is color subcarrier frequency) and 4N
+ fsc (N+ is an integer greater than or equal to 2, for example 3)
generates a clock. This 4fsc and 4N +f
The sc clock is used as a clock for digital signal processing, and the sampling clock of the A/D converter 2 and the signal processing clock up to the video LPF 5 are 4N.
+ fsc, 4 fs from the output of video LPF5
Downsample to the clock of c. Further, in the signal separation circuit 8, the 4fSC clock is used as a sampling clock for the reproduced horizontal synchronization signal and the color burst signal.

The digitized video signal output from the dropout correction circuit 7 is written into the buffer memory 11 using a 4fsc clock generated by the PLL circuit 9. Data is read from the buffer memory 11 using a 4fsc reference clock generated by the reference signal generation circuit 10.

In this way, by reading data from the buffer memory 11 using a stable reference clock unrelated to the reproduced video signal, jitter in the reproduced video signal can be absorbed.

The digitized video signal read from the buffer memory 11 is converted into an analog signal by the D/A converter 12 and becomes a reproduced video output.

FIG. 2 is a block diagram showing a specific configuration of the PLL circuit 9 in FIG. 1. In the figure, the signal separation circuit 8
The playback horizontal synchronization signal (FB
I() and the reference horizontal synchronizing signal (REF H) generated by the reference signal generation circuit 10, the PLL control circuit 2
0, the selector 21 is controlled by two people. The reproduced horizontal synchronizing signal or the reference horizontal synchronizing signal selected by the selector 21 is supplied to the control circuit 20 and becomes the sole power of the first phase comparator 22 . The comparison output of the phase comparator 22 is supplied to the control circuit 20 and becomes the input power of the adder 23 and selector 24. The selector 24 is switched and controlled by the control circuit 20. The selected output of this selector 24 is supplied to a limiter 25.

The limiter 25 is configured to selectively perform an amplitude limiting operation on the input signal, and the selection control is performed by the control circuit 20. The output of the limiter 25 becomes the sole power of the selector 26.

On the other hand, the color burst signal (CB) separated from the reproduced video signal by the signal separation circuit 8 becomes the sole power of the second phase comparator 27. The comparison output of the phase comparator 27 is supplied to the control circuit 20 and serves as an input to the selector 26. The selector 26 is switched and controlled by the control circuit 20. The selection output of this selector 26 is PL
The signal is supplied to a loop filter 28 for determining the loop characteristics of L. The loop filter 28 is a digital filter configured to achieve desired characteristics, and its output is converted to an analog voltage by a D/A converter 29 and sent to the VCO.
The control voltage is 30. VCO 30 is D/A converter 29
The oscillation frequency is controlled by the output voltage of the circuit, and its output becomes the master clock fM of this circuit, and is also supplied to the N2 frequency divider 32, the N3 frequency divider 33, and the control circuit 20 via the N1 frequency divider 31. Ru. The output of the N2 frequency divider 32 becomes the external power of the phase comparator 22, and the output of the N3 frequency divider 33 becomes the external power of the phase comparator 27, thus forming a PLL.

The N1 frequency divider 31 reproduces the master clock fM and converts it into a sampling clock 4 for horizontal synchronization signals and color burst signals.
This is for frequency division up to fsc, for example fM-16
If it is fsc, it will be N1-4. N2 frequency divider 32 is N
The output (fM/N+) of the i frequency divider 31 is set to the horizontal scanning frequency f
This is to divide the frequency up to H, and in the NTSC system, it is N
It becomes 2-910. The N3 frequency divider 33 is for dividing the output (fM/N1) of the N1 frequency divider 31 to the color subcarrier frequency fsc, f M / N + -4f.
When SC, it becomes N3-4.

The PLL control circuit 20 includes a flip-flop and a PLL control circuit 20.
L A (Progra+able Logic A
An initial reset signal (IR3T) that is generated when the power is turned on, a vertical blanking signal (VBLK) that indicates the vertical blanking period, and a search or visual scan. The selector 21,
24 and 26, selection of the amplitude limiting operation of the limiter 25, setting the loop filter 28 to its initial state, and resetting the frequency dividers 32 and 33. Note that the loop filter 28 is set to the initial state by setting each register in the digital filter to a predetermined value.

The PLL control circuit 20 further provides that when the PLL synchronizes with the color burst signal,
Based on the output of the phase comparator 27 and the output of the phase comparator 22, the phase difference between the color burst signal and the reproduced horizontal synchronization signal is calculated and averaged, and this is used as the extraction input of the adder 23 to calculate the phase. The phase error of the output of the comparator 22, that is, the reproduced horizontal synchronization signal, is corrected. The reason why the phase difference between the color burst signal and the reproduced horizontal synchronizing signal is determined when synchronization is not with the reproduced horizontal synchronizing signal but with the color burst signal is as follows.

■ Phase errors can be determined more accurately with color burst signals, so there are fewer clock fluctuations during synchronization.

■ The period (1/fsc) of the color burst signal is short,
Due to poor synchronization accuracy by the reproduced horizontal synchronization signal, there is a possibility that the phase fluctuation will be ±1800 or more of fSC. If the phase variation exceeds this value, the phase difference between the reproduced horizontal synchronizing signal and the color burst signal cannot be accurately determined.

■ The phase comparator 27 has sin type phase comparison characteristics.
When approximating θ-θ, the output value of the phase comparator 27 has an error except in the vicinity of O.

When synchronized with the reproduced horizontal synchronization signal, phase comparator 2
The output value of 7 is not necessarily near 0.

Further, the averaging of the phase difference in the PLL control circuit 20 may be performed by taking a moving average or by passing it through a low-pass filter.The operation of such a configuration will be described below.

When the power is turned on or when no video signal is input, the PL
The L control circuit 2o receives an initial reset signal (IR8T
), the selector 21 is set to the a side to select the reference horizontal synchronizing signal, the selector 24 is set to the a side to select the comparative output of the phase comparator 22, and the limiter 25 is not set to the amplitude limiting state but is set to through, The output of the limiter 25 is selected by setting the selector 26 to the a side. In addition, immediately after the power is turned on, the loop filter 28 is set so that the initial frequency of the vCO 30 is set to the center value at the time of PLL lock, and the initial phase error between the two inputs of the phase comparator 22 is set to 0. The N2 frequency divider 32 is connected to the control circuit 20.
Reset by reference horizontal sync signal via. After these sets and resets are released, the PLL starts synchronizing with the reference horizontal synchronizing signal selected by the selector 21.

The phase comparator 22 detects, as a digital value, the phase error between the clock having the horizontal scanning frequency fH obtained by dividing the output of the VCO 30 and the reference horizontal synchronizing signal.

The detected value is input to the loop filter 28 via the selector 24, limiter 25, and selector 26. The output of the loop filter 28 is converted into an analog signal by a D/A converter 29 and becomes a control voltage for the VCO 30. The control circuit 20 monitors the output of the phase comparator 22, and the phase error is continuously within a predetermined range W+(
For example, if the signal is within 11.2 to -1.6'), it is considered to be locked, and if a video signal is being reproduced at this time, the control circuit 20 immediately switches the selector 21 to the b side and outputs the reproduced horizontal synchronization signal. N2 frequency divider 32
is reset by the reproduced horizontal synchronizing signal so that the initial phase error of the phase comparator 22 with respect to the reproduced horizontal synchronizing signal becomes O.

As in the case of the reference horizontal synchronization signal, the control circuit 20 releases the reset of the N2 frequency divider 32 and starts synchronization pull-in to the reproduced horizontal synchronization signal, and the phase comparator 22
monitors the output of and determines whether the lock conditions are met. As a result of the determination, if the locking conditions are not satisfied, locking is disabled, and the control circuit 20 switches the selector 21 to the a side again to select the reference horizontal synchronizing signal and reset the N2 frequency divider 32. At this time, the loop filter 28 may also be set to the initial state.

Thereafter, locking is again determined for the reference horizontal synchronizing signal, but if locking is not possible here as well, the system is returned to its initial state after power-on, and each part is set and reset. Note that the conditions for determining lock and unlockability may be the same for the reference horizontal synchronization signal and the reproduced horizontal synchronization signal (or may be stationery (for example, the value of n I r n 2 and the range W1 are changed). For the reference horizontal synchronization signal,
Since the signal itself has no jitter and is stable, there is no problem in using a simpler judgment condition, but if it is made the same as the reproduced horizontal synchronization signal, control within the control circuit 20 will be easier.

When the selector 21 is set to the b side, if it is determined that it is locked to the reproduced horizontal synchronizing signal, the control circuit 20 causes the limiter 25 to perform an amplitude limiting operation and continues monitoring the output of the phase comparator 22. Here, instead of always performing the amplitude limiting operation while locked to the playback horizontal synchronization signal, it may be possible to perform the amplitude limiting only during the vertical blanking period, during operations such as video disc player scanning, searching, and track jumping. . If the output of the phase comparator 22 exceeds the predetermined range W2 after locking to the reproduced horizontal synchronization signal, the lock will be lost unless the phase error falls within the predetermined range W3 consecutively n4 times within 03·H from that time. In this case as well, the selector 21 is switched to the a side and the reference horizontal synchronization signal is used as the synchronization target. These ranges w,,w2. W3
(including the reference horizontal synchronizing signal) may be different from each other, but if they are the same value, and n31'n4 is also the same value as nl and nl, control within the control circuit 2o becomes easier.

In a state locked to the reproduction horizontal synchronization signal, when the color burst signal is input and the output of the phase comparator 22 falls within a predetermined range Wj (for example, ±0°111) which is narrower than the predetermined range W1 used for lock determination. When the input signal is input to the VCO, the control circuit 20 switches the selector 26 to the b side to select the output of the phase comparator 27, and also selects the output of the phase comparator 27.
The frequency is divided by N3 according to the value of the phase comparator 27 before switching of the selector 26 so that the phase error between the color burst signal and the clock of the color subcarrier frequency fsc obtained by dividing the output of 30 is minimized. The output phase of the device 33 is selected. In addition,
During the vertical blanking period, during a video disc player search, or immediately after a track jump, the selector 26 may be left on the a side without switching.

After setting the selector 26 to the b side, the control circuit 20 monitors the output of the phase comparator 27, and within 05·H after switching the selector 26, the phase error continues to be within a predetermined range Ws (for example, rsc). +21@~-22,5 in phase
”), it is considered to be locked, and if it is not, it is considered to be impossible to lock, and the selector 26 is switched to the a side, and the operation is restarted from the state locked to the playback horizontal synchronization signal. When it is locked to the color burst signal, the phase comparator 27 The output of the phase comparator 27 is continuously monitored, and if the output of the phase comparator 27 exceeds the predetermined range W6 and the phase error does not fall within the predetermined range W7 n8 times in a row within 07·H from there, it is considered that the lock is off.
As in the case where the lock is disabled, the selector 26 is switched to the a side. Further, the control circuit 20 monitors the output of the phase comparator 22 even when the selector 26 is on the b side, and similarly switches the selector 26 to the a side when it is determined that the lock is off with respect to the reproduced horizontal synchronizing signal.

Here, n5 to n8 may be different values, but as described above, n5. It is better for n7 to have the same value as nl, and "6+n8" to have the same value as nl. Also, it is better to have the same value for W5゜W5゛, w, but it is different from W3. This is because the frequency of the phase comparison signal is different between the burst signal and the burst signal, although the phase comparison period (-1H) is the same.

In normal playback conditions, it remains locked to the color burst signal, but as mentioned above, during the vertical blanking period, when searching for a video disc player, immediately after a track jump, and during playback of a portion without color burst, the selector 26 It is also possible to return the signal to side a and switch the lock target to the reproduction horizontal synchronization signal. Further, in a state locked to the color burst signal, the selector 24 is switched to the b side to select the output of the adder 23.

At this time, the control circuit 20 calculates the phase difference between the output of the phase comparator 27 and the output of the phase comparator 22, averages it, and uses this as the output of the adder 23. As a result, the output of the adder 23 becomes a value approximately equal to the phase error of the color burst signal by adding an offset to the phase error of the reproduced horizontal synchronization signal, and the selector 26 sets the PLL lock target to the color burst signal and the reproduced signal. Since no large phase error is input to the loop filter 28 at the moment of switching between the horizontal synchronizing signal and the horizontal synchronizing signal, the PLL does not become unstable before and after switching.

In this way, when the PLL is synchronized with the color burst signal as a synchronization target, the phase comparator 27
The phase difference between the color burst signal and the reproduced horizontal synchronizing signal is calculated from the output of the phase comparator 22 and the output of the phase comparator 22, and is used as the output of the adder 23, so that the output of the adder 23 becomes almost equal to the output of the phase comparator 27. By correcting the output of the phase comparator 22, a large phase error will not occur when the PLL synchronization target is switched between the color burst signal and the reproduced horizontal synchronization signal. The clock is also stable and no synchronization disturbance occurs after switching.

In addition, since the obtained phase difference correction value is averaged, even if a false reproduction horizontal synchronization signal is generated due to undetected dropout, etc., and the output of the phase comparator 22 suddenly increases, the influence of the can be minimized.

In the above embodiment, a case has been described in which the present invention is applied to a PLL circuit that performs signal processing digitally, but it is also applicable to a PLL circuit that performs signal processing in an analog manner. However, since digital processing can perform calculations such as addition and subtraction more accurately, the present invention is particularly suitable for a PLL circuit that performs signal processing digitally.As explained in detail of the invention, According to the synchronization method according to the present invention, in a PLL circuit that generates a clock synchronized with a reproduced video signal, the color burst signal and the reproduced horizontal synchronization are performed while the PLL is synchronizing with the color burst signal. By determining the phase difference with the signal and correcting the phase error of the reproduced horizontal synchronization signal based on this phase difference, a large phase error will not occur when the synchronization target is switched, so the vCO clock can also be adjusted. It is stable and does not cause synchronization disturbances after switching.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video signal reproducing apparatus having a PLL circuit to which the synchronization method of the present invention is applied, and FIG. 2 is a block diagram showing a specific configuration of the PLL circuit in FIG. 1. Explanation of symbols of main parts

Claims (2)

[Claims] (1) A method for synchronizing a PLL circuit that generates a clock that is synchronized with a reproduced video signal including a horizontal synchronization signal and a color burst signal obtained from a recording medium, wherein the reproduced video signal is used as an input signal to be synchronized. The separated color burst signal is selected, the phase difference between the color burst signal and the reproduced horizontal synchronization signal separated from the reproduced video signal is determined in a state in which the PLL circuit is synchronized with the color burst signal, and the input signal is When switching from the color burst signal to the reproduced horizontal synchronizing signal, a phase error of the reproduced horizontal synchronizing signal with respect to a predetermined phase comparison signal is corrected by the phase difference, and the reproduction horizontal synchronizing signal is changed to the reproduced horizontal synchronizing signal based on the corrected phase error. A method for synchronizing a PLL circuit characterized by synchronization. (2) A method for synchronizing a PLL circuit according to claim 1, wherein the phase difference is averaged, and the phase error is corrected using the averaged phase difference.