JPS63280590A - Control method for pll circuit - Google Patents

Abstract

PURPOSE:To operate a PLL surely and stably by using a reference horizontal synchronizing signal, a reproduction horizontal synchronizing signal and a color burst signal as an input signal being an object of synchronization and using the three signals properly and switchingly to facilitate synchronizing locking. CONSTITUTION:A signal separation circuit 8 separates a horizontal synchronizing signal and a color burst signal included in a digital video signal and gives the result to a PLL circuit 9. The PLL circuit 9 generates a clock synchronously with the reproduced video signal and three signals, the reproduced horizontal synchronizing signal from the signal separation circuit 8, the color burst signal and the reference horizontal synchronizing signal from the reference signal generating circuit 10 are inputted as the object of synchronization. Then the three signals are used properly and switchingly in response to the state of the PLL. Thus, the synchronizing locking is facilitated and the PLL is operated stably and surely.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of controlling a PLL circuit, and more particularly to a method of controlling a PLL circuit that generates a clock synchronized with a reproduced video signal.

1 and I Video signal reproducing devices such as video disc players and VTRs are configured to control rotational systems such as spindle motors based on a reference horizontal synchronization signal generated within the device. Although the reproduced video signal includes jitter (time axis fluctuation), it is on average synchronized with the reference horizontal synchronization signal. Therefore, if the PLL circuit that generates a clock synchronized with the reproduced video signal is synchronized with the reference horizontal synchronization signal before synchronizing with the reproduced video signal, synchronization with the reproduced video signal can be easily achieved in a short time and reliably. You will be able to pull it in. In addition, when the video signal is being regenerated stably, phase errors can be detected with higher accuracy using the color burst signal than the reproducing horizontal synchronization signal, so P
It is preferable to synchronize the LL circuit with the color burst signal. However, since the color burst signal has a short period,
If the phase comparison range in terms of jitter is narrow and the frequency error of the PLL circuit is not small enough, cycle slips will occur.
A false synchronization state may occur when the period is shifted by an integral multiple of 1/fsc (fsc is the color D1 carrier frequency) in IH (H is the horizontal scanning period).

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a control method that can easily perform synchronization and operate a PLL stably and reliably.

In the PLL circuit control method according to the present invention, in a PLL circuit that generates a clock synchronized with a reproduced video signal including a horizontal synchronization signal and a color burst signal obtained from a recording medium, a reference horizontal synchronization signal is used as an input signal to be synchronized. signal, playback horizontal synchronization signal and color burst signal,
The present invention is characterized in that these three signals are appropriately switched and used depending on the state of the PLL.

LJI Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram of a video signal reproducing apparatus having a PLL circuit according to the present invention and having a configuration in which, for example, signal processing is performed digitally. In the figure, an FM video signal read from a recording medium such as a video disc is an analog L
A/D converter 2 via PF (low pass filter) 1
is supplied to

LPFl is for removing aliasing distortion in A/'D conversion. The digitized FM video signal output from the A/D converter 2 is processed by a digital BPF.
(bandpass filter) 3. This digital BPF 3 extracts only the components necessary for detecting the A/D variable detection ratio detection power video signal, which also includes the FM audio signal, and outputs it to the next stage.
Supplied to the M detection circuit 4. As the FM detection circuit 4, for example, one having the configuration proposed by the present applicant in Japanese Patent Application No. 59-262481 can be used. From the detection output of the FM detection circuit 4, only the baseband component of the video signal is extracted by the video LPF 5.

A dropout detection circuit 6 is provided for detecting dropout of the video signal. This dropout detection circuit 6 has a level comparator configuration, for example, and detects that the signal level of the square signal of the envelope component of the digitized FM video signal in the FM detection circuit 4 has become below a predetermined value, and performs dropout. Outputs a detection signal.

The digitized video signal passed through the video LPF 5 is supplied to a dropout correction circuit 7 and a signal separation circuit 8. The dropout correction circuit 7 performs dropout correction in response to the dropout detection signal supplied from the dropout detection circuit 6.

The signal separation circuit 8 separates signals such as horizontal synchronization signals and color burst signals contained in the digitized video signal and supplies them to the PLL circuit 9. The PLL circuit 9 generates a clock synchronized with the reproduced video signal, and its synchronization targets include the reproduced horizontal synchronization signal from the signal separation circuit 8, the color burst signal, and the reference horizontal synchronization signal from the reference signal generation circuit 10. 3 signals are input, and based on these signals, 4fsc (fsc is color subcarrier frequency) and 4N
fsc (N is an integer greater than or equal to 2, for example 3) +
1 clock is generated. This 4fsc and 4N.

The fsc clock is used as a clock for digital signal processing.1. The sampling clock of the A/D converter 2 and the signal processing clock up to the video LPF 5 are set to 4N fsc, and the output of the video LPF 5 is downsampled to the 4 fsc clock. Also,
The signal separation circuit 8 uses the 4fSC clock as a sampling clock for the reproduced horizontal synchronization signal and color burst signal.

The device digitized video signal constituted by the dropout correction circuit 7 is written into the buffer memory 11 by a 4f'sc clock generated by the PLL circuit 9. Data is read from the buffer memory 11 using a 4fsc reference clock generated by the reference signal generation circuit 10.

In this way, by reading data from the buffer memory 11 using a stable reference clock unrelated to the reproduced video signal, jitter in the reproduced video signal can be absorbed.

The digitized video signal read from the buffer memory 11 is converted into an analog signal by the D/A converter 12 and becomes a reproduced video output.

FIG. 2 is a block diagram showing a specific configuration of the PLL circuit 9 to which the control method of the present invention is applied.

In the figure, the reproduced horizontal synchronizing signal (PBH) separated from the reproduced video signal by the signal separation circuit 8 and the reference horizontal synchronizing signal (REF H) generated by the reference signal generating circuit 10 are switched and controlled by the PLL control circuit 20. The selector 21 is operated by two people.

The reproduced horizontal synchronizing signal or the reference horizontal synchronizing signal selected by the selector 21 is supplied to the control circuit 20 and becomes the sole power of the first phase comparator 22 . The comparison output of the phase comparator 22 is supplied to the control circuit 20 and serves as input for each of the adder 23 and selector 24.

The selector 24 is switched and controlled by the control circuit 20.

The selected output of this selector 24 is supplied to a limiter 25. The limiter 25 is configured to selectively perform an amplitude limiting operation on the input signal, and the selection control is performed by the control circuit 20. The output of the limiter 25 becomes the sole power of the selector 26.

On the other hand, the color burst signal (CB) separated from the reproduced video signal by the signal separation circuit 8 becomes the sole power of the second phase comparator 27. The comparison output of this phase comparator 27 is supplied to the control circuit 20 and also to the selector 26. It becomes the power of others. The selector 26 is switched and controlled by the control circuit 20. The selection output of this selector 26 is P
The signal is supplied to a loop filter 28 for determining the loop characteristics of LL. The loop filter 28 is a digital filter configured to achieve desired characteristics, and its output is converted to an analog voltage by a D/A converter 29 and sent to the VC.
This becomes the control voltage of O (voltage controlled oscillator) 30. VCO3
The oscillation frequency of 0 is controlled by the output voltage of the D/A converter 29, and its output becomes the master clock fM of this circuit, and also passes through the N1 frequency divider 31 to the N2 frequency divider 32 and the N3 frequency divider. 33 and the control circuit 20.

The output of the N2 frequency divider 32 becomes the external power of the phase comparator 22, and the output of the N3 frequency divider 33 becomes the external power of the phase comparator 27, thus forming a PLL.

The N1 frequency divider 31 reproduces the master clock fM and converts it into a sampling clock 4 for horizontal synchronization signals and color burst signals.
This is to divide the frequency up to fsc, for example, LM=15
fs (If it is, it becomes N1-4.N2 frequency divider 32 is N
1 The output (fM/N+) of the frequency divider 31 is set to the horizontal scanning frequency f
This is to divide the frequency up to H, and in the NTSC system, it is N
2=910. The N3 frequency divider 33 is for frequency-dividing the output (fM/N+) of the N1 frequency divider 31 to the color subcarrier frequency fSC, and when fM/N+=4fsc, N5=4.

The PLL control circuit 20 consists of a flip 70 tube and a PLL control circuit 20.
L A (Program-able Lo(lic)
(7) Initial reset signal (IR8T), which is configured by a combination or a microcomputer, etc. and is issued when the power is turned on, vertical blanking signal (to VBL) indicating the vertical blanking period, search or visual・Scan signal (SCAM) indicating that scanning is in progress, jump signal (JUMP) indicating jumping to an adjacent track during special playback of still images, etc. are used as control signals to switch selectors 21, 24, 26, and limiter. 25 amplitude limiting operation, setting the loop filter 28 to the initial state,
Controls such as resetting the frequency dividers 32 and 33. Note that the loop filter 28 is set to the initial state by setting each register in the digital filter to a predetermined value.

Next, the procedure of the control method according to the present invention executed by the PLL control circuit 20 will be explained along the flowchart of FIG. 0
By a control signal such as an initial reset signal (IR3T), the selector 21 is set to the a side to select the reference horizontal synchronizing signal, the selector 24 is set to the a side to select the comparative output of the phase comparator 22, and the limiter 25 is set to the amplitude limiting state. The output of the limiter 25 is selected by setting the selector 26 to the a side. In addition, immediately after the power is turned on, VCO3
The loop filter 28 is set so that the initial frequency of 0 is set to the center value at the time of PLL lock, and the phase comparator 2
The N2 frequency divider 32 is reset by the reference horizontal synchronization signal via the control circuit 20 so that the initial phase error between the two inputs of N2 becomes 0 (step 81). After these sets and resets are released, the PLL starts synchronization pull-in to the reference horizontal synchronization signal selected by the selector 21 (step 82).

The phase comparator 22 detects, as a digital value, the phase error between the clock having the horizontal scanning frequency fH obtained by dividing the output of the VCO 30 and the reference horizontal synchronizing signal.

The detected value is input to the loop filter 28 via the selector 24, limiter 25, and selector 26. The output of the loop filter 28 is converted into an analog signal by a D/A converter 29 and becomes a control voltage for the VCO 30. The control circuit 20 monitors the output of the phase comparator 22, and detects that the phase error occurs n2 times (for example, 4 times) consecutively within nI −H (for example, n+=16, H is the horizontal scanning period) from the start of synchronization pull-in. When the angle falls within the range W+ (for example, +1.2 to -1.6 degrees), it is considered that the lock is established (step 83). If the video signal is being reproduced at this time, the control circuit 20 switches the selector 21 to the b side to select the reproduced horizontal synchronization signal and selects the N2 frequency divider 3 after passing through step S4, which will be described later.
2 to be reset by the playback horizontal sync signal step $
5) The initial phase error of the phase comparator 22 is set to O with respect to the reproduced horizontal synchronizing signal.

As in the case of the reference horizontal synchronization signal, the control circuit 20 releases the reset of the N2 frequency divider 32 and starts synchronization pull-in to the reproduced horizontal synchronization signal, and the phase comparator 22
The output is monitored and it is determined whether the locking conditions are met (step 86).

As a result of the determination, if the locking conditions are not satisfied, locking is disabled, and the control circuit 20 returns to step S2, switches the selector 21 to the a side again, selects the reference horizontal synchronizing signal, and resets the N2 frequency divider 32. . At this time, the loop filter 28 may also be set to the initial state. After this, locking is determined again for the reference horizontal synchronization signal (step S3), but if locking is not possible here as well, return to step $1, return to the initial state after power-on, and set each part.・Perform a reset. In addition,
The conditions for determining lock and unlockability may be the same for the reference horizontal synchronization signal and the reproduced horizontal synchronization signal, or may be stationary (for example, the value of nl+n2 and the range W1 are changed). In the case of the reference horizontal synchronization signal, the signal itself is stable with no jitter, so there is no problem in using a simpler judgment condition, but if it is the same as the reproduced horizontal synchronization signal, control within the control circuit 20 will be easier. .

When the selector 21 is set to the b side, if it is determined that it is locked to the reproduced horizontal synchronizing signal (step 86), the control circuit 20 operates the limiter 25 to limit the amplitude and continues monitoring the output of the phase comparator 22.

Here, instead of always performing the amplitude limiting operation while locked to the playback horizontal synchronization signal, it may be possible to perform the amplitude limiting only during the vertical blanking period, during operations such as video disc player scanning, searching, and track jumping. . After locking to the reproduced horizontal synchronization signal, if the output of the phase comparator 22 exceeds the predetermined range W2, from that point on
If the phase error does not fall within the predetermined range W3 n4 times in a row within 3.H, it is assumed that the lock is off (step S7), and in this case also, the process returns to step S2 and the selector 21 is switched to the a side to output the reference horizontal synchronization signal. to be synchronized. These ranges WI, W2, and W3 (including the case of the reference horizontal synchronization signal) may be different from each other, but should be the same value, and n3. Control within the control circuit 20 becomes easier if n4 has the same value as n+ and nl, respectively.

When locked to the reproduction horizontal synchronization signal, the color burst signal is input and the output of the phase comparator 22 is in a range W that is narrower than the predetermined range used for lock determination.
J (for example, ±0.1°), the control circuit 20 switches the selector 26 to the b side to select the output of the phase comparator 27 (step S8), and at the same time
Color subcarrier frequency fsc obtained by dividing the output of CO30
The phase comparator 27 before the selector 26 switches so that the phase error between the clock and the color burst signal is minimized.
The output phase of the N3 frequency divider 33 is selected according to the value of . Note that during the vertical blanking period, during a video disc player search, or immediately after a track jump, the selector 26 may be left on the a side without switching.

After setting the selector 26 to the b side, the control circuit 20 monitors the output of the phase comparator 27 and detects that the phase error is within a predetermined range Ws (for example, fsc +21° to -22,5 in phase
°), it is considered to be locked and step S9), and if not, it is considered that locking is impossible, and the process returns to step S5, switches the selector 26 to the a side, and starts over from the state locked to the reproduction horizontal synchronizing signal. When locked to the color burst signal, the output of the phase comparator 27 is continuously monitored, and if the output of the phase comparator 27 exceeds the predetermined range W6, the signal changes to 0.
If the phase error does not fall within the predetermined range W7 for n8 consecutive times within 7.H, it is assumed that the lock is off and step 510
), the process returns to step S5 and the selector 26 is switched to the a side, as in the case where the lock is impossible. The control circuit 20 also monitors the output of the phase comparator 22 when the selector 26 is on the b side, and if it determines that it is out of lock with respect to the reproduced horizontal synchronization signal (step 511), it similarly returns to step S5. switch the selector 26 to the a side.

Here, n5 to n8 may have different values, but as described above, it is better that ns and nl have the same values as nl, and that n6 and ns have the same values as nl. Further, it is better that W5, W6, and W7 have the same value, but they are different from W3.

This is because the reproduction horizontal synchronization signal and the color burst signal have the same phase comparison period (=18), but the frequencies of the phase comparison signals are different.

In normal playback conditions, it remains locked to the color burst signal, but as mentioned above, during the vertical blanking period, when searching for a video disc player, immediately after a track jump, and during playback of a portion without color burst, the selector 26 It is also possible to return the signal to side a and switch the lock target to the reproduction horizontal synchronization signal. Further, in a state locked to the color burst signal, the selector 24 is switched to the b side to select the output of the adder 23.

At this time, the control circuit 20 calculates the phase difference between the output of the phase comparator 27 and the output of the phase comparator 22, averages it, and uses this as the output of the adder 23. As a result, the output of the adder 23 becomes a value approximately equal to the phase error of the color burst signal by adding an offset to the phase error of the reproduced horizontal synchronization signal, and the selector 26 sets the PLL lock target to the color burst signal and the reproduced signal. Since a large phase error is not input to the loop filter 28 at the moment of switching between the horizontal synchronizing signal and the horizontal synchronizing signal, P and LL do not become unstable before and after switching.

The series of operations described above are repeated until it is determined in step S12 that the playback has ended.

Note that the reference horizontal synchronization signal is a stable signal and will not go out of synchronization once it is synchronized, so the determination in step S4 in FIG. 3 can be omitted. Further, if the switching of the synchronization target from the reproduction horizontal synchronization signal to the color burst signal is performed immediately after synchronization with the reproduction horizontal synchronization signal, the judgment in step S7 is not necessary. If the switching to the color burst signal is performed when a predetermined condition is satisfied after synchronizing with the signal, the judgment in step S7 is inserted because the synchronization of the reproduced horizontal synchronization signal may be disrupted during that time. In this way, by synchronizing with the reference horizontal synchronization signal before the PLL synchronizes with the reproduced video signal or when it cannot synchronize, it can be performed stably and reliably even when synchronizing with the reproduced video signal next time. . In addition, before synchronizing to the color burst signal or when synchronizing to the color burst signal is not possible, by synchronizing with the playback horizontal synchronization signal, the synchronization with the playback video signal will not be disrupted significantly, and then the synchronization with the color burst signal will be synchronized. It can be performed stably and reliably even when transitioning to Furthermore, when the reproduced video signal is being reproduced stably, P
By driving LL, high synchronization accuracy can be obtained.

Furthermore, even when synchronized to the color burst signal, by monitoring the synchronization of both the color burst signal and the playback horizontal sync signal, you will not remain stuck in a false synchronization state with cycle slips. .

In the above embodiment, a case has been described in which the present invention is applied to a PLL circuit that performs signal processing digitally, but it is also applicable to a PLL circuit that performs signal processing in an analog manner. However, since digital processing makes it easier to determine the synchronization relationship, the present invention is particularly suitable for PLL circuits that perform signal processing digitally.

As explained above, according to the control method according to the present invention,
In a PLL circuit that generates a clock synchronized with a reproduced video signal, a reference horizontal sync signal, a reproduced horizontal sync signal, and a color burst signal are used as input signals to be synchronized, and these three signals are switched and used as appropriate depending on the state. By doing so, synchronization can be easily pulled in and the PLL can be operated stably and reliably.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a video signal reproducing device having a PLL circuit according to the present invention, and FIG. 2 is a block diagram showing a specific configuration of the PLL circuit to which the control method according to the present invention is applied.
FIG. 3 is a flowchart showing the procedure of the control method according to the present invention executed by the PLL control circuit of FIG. 2. Explanation of symbols of main parts

Claims (1)

[Claims] A method for controlling a PLL circuit that generates a clock synchronized with a reproduced video signal including a horizontal synchronization signal and a color burst signal obtained from a recording medium, wherein the video from which the reproduced video signal is obtained is used as an input signal to be synchronized. In the initial state of the signal reproducing device, a reference horizontal synchronization signal is selected as its time reference, and when the PLL circuit is synchronized with the reference horizontal synchronization signal, the input signal is switched to a reproduction horizontal synchronization signal separated from the reproduction video signal, When synchronization cannot be achieved after the reproduction horizontal synchronization signal is selected, or when synchronization is lost after synchronization acquisition, the input signal is switched to the reference horizontal synchronization signal, and the PLL circuit selects the reproduction horizontal synchronization signal. When synchronized with the synchronization signal, the input signal is switched to a color burst signal separated from the reproduced video signal, and after the color burst signal is selected, when synchronization to the color burst signal cannot be achieved or to the color burst signal. A method for controlling a PLL circuit, comprising switching the input signal to the reproduced horizontal synchronizing signal when the color burst signal or the reproduced horizontal synchronizing signal becomes out of synchronization after synchronization is pulled in.