JPS63286082A - Method for locking pll circuit - Google Patents

Abstract

PURPOSE:To attain quick locking in changing over an object of synchronization by resetting a phase of an input signal so as to make the initial phase error zero when a reference horizontal synchronizing signal or a regenerative horizontal synchronizing signal is selected as other input signal to a phase comparator. CONSTITUTION:A phase comparator 22 detects a phase error between a clock of a horizontal scanning frequency fH obtained from the frequency-division of an output of a voltage controlled oscillator VCO 30 and a reference horizontal synchronizing signal by a digital value. A control circuit 20 monitors an output of the phase comparator 22 and regards it to be in the locking state that the phase error reaches the range W1 n2 times consecutively within n1.H (H is a horizontal scanning period) from the locking start of the synchronization. In this case, when a video signal is regenerated, a control circuit 20 throws a selector 21 to the position (b) to select the regenerative horizontal synchronizing signal. Simultaneously, the phase of the signal of horizontal scanning frequency fH being the frequency division output of the N2 frequency divider 32 is set to make the initial phase error of the phase comparator 22 zero with respect to the regenerative horizontal synchronizing signal.

Description

TECHNICAL FIELD The present invention relates to a synchronization pull-in method for a PLL circuit, and more particularly to a synchronization pull-in method for a PLL circuit that generates a clock synchronized with a reproduced video signal.

Background Art Video signal reproducing devices such as video disc players and VTRs are configured to control rotational systems such as spindle motors based on a reference horizontal synchronization signal generated within the device. The video signal is, on average, synchronized with the reference horizontal synchronization signal. However, since the reproduced video signal includes jitter (time axis fluctuation), when the PLL circuit that generates a clock synchronized with the reproduced video signal is synchronized with the reference horizontal sync signal, the synchronization target is set to the reproduced horizontal sync signal. Immediately after switching, the initial phase error is equal to the magnitude of the jitter, and can be a large value. In a PLL circuit, the smaller the initial phase error, the shorter the time required for locking in.

Furthermore, if a trapezoidal wave characteristic as shown in Fig. 5 is used as a phase comparator in a PLL circuit in order to reduce the number of output bits from 10 bits to 8 bits, If there is also a large initial phase error, the effect on the synchronization pull-in time will be even greater.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a synchronization pull-in method for a PLL circuit that can quickly perform synchronization pull-in when the object of synchronization is switched.

A synchronization pull-in method for a PLL circuit according to the present invention is a PLL circuit that generates a clock synchronized with a reproduced video signal including a horizontal synchronization signal obtained from a recording medium, in which a reference horizontal synchronization signal and a reproduction horizontal synchronization signal are selectively input. One input signal of the phase comparator is a horizontal scanning frequency signal obtained by dividing the clock of the voltage controlled oscillator, and the other input signal of the phase comparator is a reference horizontal synchronization signal or a reproduced horizontal signal. It is characterized in that when selecting a synchronization signal, the phase of the other input signal is reset so that the initial phase error becomes O.

Example Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram of a video signal reproducing apparatus having a PLL circuit according to the present invention and having a configuration in which, for example, signal processing is performed digitally. In the figure, an FM video signal read from a recording medium such as a video disc is an analog L
A/D converter 2 via PF (low pass filter) 1
supplied to

LPFI is for removing aliasing distortion in A/D conversion. The digitized FM video signal output from the A/D converter 2 is supplied to a digital BPF (band pass filter) 3. This digital B
The PF 3 extracts only the components necessary for detecting the video signal from the A/D conversion output including the FM audio signal, and supplies the extracted components to the FM detection circuit 4 at the next stage. As the FM detection circuit 4, for example, one having the configuration proposed by the present applicant in Japanese Patent Application No. 59-262481 can be used. From the detection output of the FM detection circuit 4, only the baseband component of the video signal is extracted by the video LPF 5.

A dropout detection circuit 6 is provided for detecting dropout of the video signal. This dropout detection circuit 6 has a level comparator configuration, for example, and detects that the signal level of the square signal of the envelope component of the digitized FM video signal in the FM detection circuit 4 has become below a predetermined value, and performs dropout. Outputs a detection signal.

The digitized video signal that has passed through the video LPF 5 is supplied to a dropout correction circuit 7 and a signal separation circuit 8. The dropout correction circuit 7 performs dropout correction in response to the dropout detection signal supplied from the dropout detection circuit 6.

The signal separation circuit 8 separates signals such as a horizontal synchronization signal and a color burst signal contained in the digitized video signal and supplies them to the PLL circuit 9. The PLL circuit 9 generates a clock synchronized with the reproduced video signal, and its synchronization targets include the reproduced horizontal synchronization signal from the signal separation circuit 8, the color burst signal, and the reference horizontal synchronization signal from the reference signal generation circuit 10. 3 signals are input, and based on these signals, 4fsc (fsc is color subcarrier frequency) and 4N
+ fsc (N+ is an integer greater than or equal to 2, for example 3)
generates a clock. This 4 fSC and 4 N l
The fSC clock is used as a clock for digital signal processing, and the sampling clock of the A/D converter 2 and the signal processing clock up to the video LPF 5 are
N+fsc, 4fs from the output of video LPF5
Downsample to the clock of c. Further, in the signal separation circuit 8, the 4fSC clock is used as a sampling clock for the reproduced horizontal synchronization signal and the color burst signal.

The digitized video signal output from the dropout correction circuit 7 is written into the buffer memory 11 using a 4fSC clock generated by the PLL circuit 9. Data is read from the buffer memory 11 using a 4fsc reference clock generated by the reference signal generation circuit 10.

In this way, by reading data from the buffer memory 11 using a stable reference clock unrelated to the reproduced video signal, jitter in the reproduced video signal can be absorbed.

The digitized video signal read from the buffer memory 11 is converted into an analog signal by the D/A converter 12 and becomes a reproduced video output.

FIG. 2 is a block diagram showing a specific configuration of the PLL circuit 9 to which the synchronization pull-in method of the present invention is applied. In the figure, a reproduced horizontal synchronizing signal (PBH) separated from a reproduced video signal by a signal separation circuit 8 and a reference signal generation circuit 10
The reference horizontal synchronization signal (REF H) generated at PL
The selector 21 is switched and controlled by the L control circuit 20, and is operated by two people. The reproduction horizontal synchronization signal or reference horizontal synchronization signal selected by the selector 21 is supplied to the control circuit 20 and the first phase comparator 22
Becoming a single person's strength. The comparison output of the phase comparator 22 is supplied to the control circuit 20 and becomes the input power of the adder 23 and selector 24. The selector 24 is switched and controlled by the control circuit 20. This selector 24
The selected output is supplied to the limiter 25. limiter 25
is configured to selectively perform an amplitude limiting operation on an input signal, and the selection control is performed by a control circuit 20. The output of the limiter 25 is the selector 26
Becoming a single person's strength.

On the other hand, the color burst signal (CB) separated from the reproduced video signal by the signal separation circuit 8 becomes the sole power of the second phase comparator 27. The comparison output of this phase comparator 27 is supplied to the control circuit 20 and becomes a low input of the selector 26. The selector 26 is switched and controlled by the control circuit 20. The selection output of this selector 26 is PL
The signal is supplied to a loop filter 28 for determining the loop characteristics of L. The loop filter 28 is a digital filter configured to achieve desired characteristics, and its output is converted to an analog voltage by a D/A converter 29 and sent to the VCO.
(Voltage controlled oscillator) 30 control voltage. VCO30
The oscillation frequency is controlled by the output voltage of the D/A converter 29, and its output becomes the master clock fM of this circuit, and is also connected to the N2 frequency divider 32 and N2 frequency divider 32 via the N1 frequency divider 31.
The signal is supplied to the frequency divider 33 and the control circuit 20. N
The output of the 2 frequency divider 32 becomes the low input of the phase comparator 22,
The output of the N3 frequency divider 33 is the low input of the phase comparator 27, and a PLL is formed by the above.

The N1 frequency divider 31 reproduces the master clock fM and converts it into a sampling clock 4 for horizontal synchronization signals and color burst signals.
This is for frequency division up to fsc, for example fM-16
If it is fsc, it will be N1-4. N2 frequency divider 32 is N
1 The output (fM/N+) of the frequency divider 31 is set to the horizontal scanning frequency f
This is to divide the frequency up to H, and in the NTSC system, it is N
It becomes 2-910. The N3 frequency divider 33 is for dividing the output (fM/N+) of the N1 frequency divider 31 to the color subcarrier frequency fsc, and when fM/N+-4fsc,
It becomes N3-4.

The PLL control circuit 20 includes a flip-flop and a PLL control circuit 20.
L A (ProgramIIable Logic
An initial reset signal (IRST), which is generated when the power is turned on, a vertical blanking signal (VBLK), which indicates the vertical blanking period, and a microcomputer.
A scan signal (SCAN) indicating that a search or visual scan is in progress, a jump signal (JUMP) indicating that a jump has been made to an adjacent track during special playback of still images, etc. are used as control signals, and the selector 21
．． 24 and 26, selection of the amplitude limiting operation of the limiter 25, setting the loop filter 28 to its initial state, and resetting the frequency dividers 32 and 33. Note that the loop filter 28 is set to the initial state by setting each register in the digital filter to a predetermined value.

FIG. 4 shows an example of the configuration of the phase comparator 22 and N2 frequency divider 32 in FIG. 2.

In the figure, the counter 41 is an N2-binary synchronous counter with a synchronous load that operates as the N2 frequency divider 32;
It is set to 910, and the output is 10 bits. The value 0 to 909 expressed in 10 bits is converted into 8 bits by the trapezoidal wave generating circuit 42 as shown in FIG. 5, and is supplied to the register 43. The register 43 is configured to be loaded in clock synchronization with synchronous clear.
When the input is “L”, all outputs are “0” with clock synchronization
When the CLR input is “H#” and the LOAD input is “L”, the IN value is output to OUT in clock synchronization, and the CLR input is “H#” and the LOAD input is “L”.
When both the LR input and the LOAD input are "H", the output retains its previous value.

The counter 41 and register 43 use the 4fsc signal as a clock input.

The trapezoidal wave generating circuit 42 and the resilister 43 constitute a phase comparator with characteristics as shown in FIG.
Since the value of the counter 41 is loaded into the register 43 when the reference horizontal synchronization signal or the reproduced horizontal synchronization signal is input, the phase comparison between the reference horizontal synchronization signal or the reproduction horizontal synchronization signal and the signal of the horizontal scanning frequency f+ is performed. As a result,
This value is output as a phase error of the phase comparator 22.

The OR gate 44 outputs a reference horizontal synchronization signal or a reproduced horizontal synchronization signal to set the counter 41 to "129" when the reset signal (possible press) generated from the PLL control circuit 20 (Fig. 2) is "L#". At the same time as loading, the register 43 is reset to "0".As shown in FIG.
The count value “128” of the counter 41 is the trapezoidal wave output “
However, since the outputs of the counter 41 and the register 43 are shifted by one clock, the load value of the counter 41 becomes "129".

Next, the procedure of the synchronization pull-in method according to the present invention executed by the PLL control circuit 20 will be explained along the flowchart of FIG.

When the power is turned on or when no video signal is input, the PL
The L control circuit 20 receives an initial reset signal (IR8T
), the selector 21 is set to the a side to select the reference horizontal synchronizing signal, the selector 24 is set to the a side to select the comparative output of the phase comparator 22, and the limiter 25 is not set to the amplitude limiting state but is set to through, The output of the limiter 25 is selected by setting the selector 26 to the a side. In addition, immediately after the power is turned on, the loop filter 28 is set so that the initial frequency of the vCO 30 is set to the center value at the time of PLL lock, and the initial phase error between the two inputs of the phase comparator 22 is set to 0. The phase of the signal of the horizontal scanning frequency fH, which is the frequency-divided output of the N2 frequency divider 32, is reset (step SL). In FIG. 4, this reset is performed by the control circuit 20 setting the reset signal (Kawako) to "L" and setting the output of the register 43 to "0°" using the reference horizontal synchronization signal and loading the counter 41. .After these sets and resets are released, the PLL
starts synchronization pull-in to the reference horizontal synchronization signal selected by the selector 21 (step S2).

The phase comparator 22 detects, as a digital value, the phase error between the clock having the horizontal scanning frequency fH obtained by dividing the output of the VCO 30 and the reference horizontal synchronizing signal.

The detected value is input to the loop filter 28 via the selector 24, limiter 25, and selector 26. The output of the loop filter 28 is converted into an analog signal by a D/A converter 29 and becomes a control voltage for the VCO 30. The control circuit 20 monitors the output of the phase comparator 22, and detects if the phase error occurs n2 times (for example, 4 times) consecutively within nl H (for example, n+ = 16, H is the horizontal scanning period) from the start of synchronization pull-in. When the angle falls within the range W+ (for example, +1.2 to -1.6 degrees), it is considered that the lock is established (step S3). If the video signal is being reproduced at this time, the control circuit 20 switches the selector 21 to the b side after passing through step S4, which will be described later, to select the reproduced horizontal synchronizing signal and the divided output of the N2 frequency divider 32. The phase of the signal with the horizontal scanning frequency f+ is reset (step S5) so that the initial phase error of the phase comparator 22 with respect to the reproduced horizontal synchronizing signal becomes 0. This reset is performed by the control circuit 20 setting the reset signal (PHR8T) to "L" in FIG. 4, setting the output of the register 43 to "0" in response to the reproduction horizontal synchronizing signal, and loading the counter 41.

As in the case of the reference horizontal synchronization signal, the control circuit 20 releases the reset of the N2 frequency divider 32 and starts synchronization pull-in to the reproduced horizontal synchronization signal, and the phase comparator 22
The output is monitored and it is determined whether the locking conditions are satisfied (step S6).

As a result of the determination, if the locking conditions are not satisfied, the locking is disabled, and the control circuit 20 returns to step S2, switches the selector 21 to the a side again, selects the reference horizontal synchronizing signal, and performs the N2 minute signal in the same way as when the power is turned on. Reset the frequency generator 32. At this time, the loop filter 28 may also be set to the initial state. After this, locking is determined again for the reference horizontal synchronization signal (step S4), but if locking is not possible here as well, the process returns to step S1 to return to the initial state after the power is turned on and set/set each part. Perform a reset. Note that the conditions for determining whether to lock or cannot lock may be the same or different for the reference horizontal synchronization signal and the reproduced horizontal synchronization signal (for example, nl r n2
(change the value and range W1). In the case of the reference horizontal synchronization signal, the signal itself is stable with no jitter, so there is no problem in using a simpler judgment condition, but if it is the same as the reproduced horizontal synchronization signal, control within the control circuit 20 will be easier. .

When the selector 21 is set to the b side, if it is determined that it is locked to the reproduced horizontal synchronizing signal (step S6), the control circuit 20 causes the limiter 25 to perform an amplitude limiting operation and continues monitoring the output of the phase comparator 22.

Here, instead of always performing the amplitude limiting operation while locked to the playback horizontal synchronization signal, it may be possible to perform the amplitude limiting only during the vertical blanking period, during operations such as video disc player scanning, searching, and track jumping. . After locking to the reproduced horizontal synchronization signal, if the output of the phase comparator 22 exceeds the predetermined range W2, from that point on
3 ・The phase error is within the specified range W3 04 times in a row
If it does not enter the lock, it will be considered as unlocked (step S7),
In this case as well, the process returns to step S2 and the selector 21 is switched to the a side to set the reference horizontal synchronization signal as the synchronization target. These ranges Wl, W2 . W3 (including the case of the reference horizontal synchronization signal) may be different from each other, but should be the same value, and n3. If n4 also has the same value as n + r 02, control within the control circuit 20 will be easier.

When locked to the reproduction horizontal synchronization signal C, the color burst signal is input and the output of the phase comparator 22 is in a range W that is narrower than the predetermined range used for lock determination.
a (for example, ±0.1@), the control circuit 20 switches the selector 26 to the b side to select the output of the phase comparator 27 (step S8), and at the same time
Color subcarrier frequency esc obtained by dividing the output of CO30
The phase comparator 27 before the selector 26 switches so that the phase error between the clock and the color burst signal is minimized.
The output phase of the N3 frequency divider 33 is selected according to the value of . Note that during the vertical blanking period, during a video disc player search, or immediately after a track jump, the selector 26 may be left on the a side without switching.

After setting the selector 26 to the b side, the control circuit 20 monitors the output of the phase comparator 27, and detects that the phase error is within a predetermined range Ws (for example, fSC +21″~-22 in phase,
5"), it is considered to be locked and step S9); if not, it is considered to be impossible to lock, and the process returns to step S5, switches the selector 26 to the a side, and starts over from the state locked to the playback horizontal synchronizing signal.Color burst signal When locked, the output of the phase comparator 27 is continuously monitored,
The output of the phase comparator 27 exceeds the predetermined range W6, and within 07·H from there, the phase error continues 08 times within the predetermined range Wy.
If it does not go inside, it is assumed that the lock is unlocked and proceed to step 51.
0), the process returns to step S5 and the selector 26 is switched to the a side, as in the case where the lock is impossible. The control circuit 20 also monitors the output of the phase comparator 22 when the selector 26 is on the b side, and if it determines that it is out of lock with respect to the reproduced horizontal synchronization signal (step 511), it similarly returns to step S5. switch the selector 26 to the a side.

Here, n5 to n8 may be different values, but as described above, n5. It is better for n7 to have the same value as nl, and "6 + n8 to have the same value as n2. Also, it is better to have the same value for W5, W6, and Wy, but it is different from W3. This is because the playback horizontal synchronization signal and color burst This is because the frequency of the phase comparison signal is different, although the phase comparison period (-1H) is the same as that of the signal.

In normal playback conditions, it remains locked to the color burst signal, but as mentioned above, during the vertical blanking period, when searching for a video disc player, immediately after a track jump, and during playback of a portion without color burst, the selector 26 It is also possible to return the signal to side a and switch the lock target to the reproduction horizontal synchronization signal. Further, in a state locked to the color burst signal, the selector 24 is switched to the b side to select the output of the adder 23.

At this time, the control circuit 20 calculates and averages the phase difference from the output of the phase comparator 27 and the output of the phase comparator 22, and then sets this as the low input of the adder 23. As a result, the output of the adder 23 becomes a value approximately equal to the phase error of the color burst signal by adding an offset to the phase error of the reproduced horizontal synchronization signal, and the selector 26 sets the PLL lock target to the color burst signal and the reproduced signal. Since no large phase error is input to the loop filter 28 at the moment of switching between the horizontal synchronizing signal and the horizontal synchronizing signal, the PLL does not become unstable before and after switching.

The series of operations described above are repeated until it is determined in step S12 that the playback has ended.

Note that the reference horizontal synchronization signal is a stable signal and will not go out of synchronization once it is synchronized, so the determination in step S4 in FIG. 3 can be omitted. Furthermore, if the switching of the synchronization target from the reproduction horizontal synchronization signal to the color burst signal is performed immediately after synchronization with the reproduction horizontal synchronization signal, the judgment in step S7 is not necessary. If the switching to the color burst signal is performed when a predetermined condition is met after synchronization with the synchronization signal, the judgment in step S7 is inserted because the synchronization of the reproduced horizontal synchronization signal may be disrupted during that time. -ing

As described above, in the present invention, when switching the synchronization target from the reference horizontal synchronization signal to the reproduced horizontal synchronization signal, the initial phase error between the reproduced horizontal synchronization signal and the signal of the horizontal scanning frequency fH is completely set to 0, and then Since the synchronization pull-in is started, even when the jitter is large, the synchronization pull-in can be carried out in a short time.

On the other hand, when the synchronization target is switched from the reproduced horizontal synchronizing signal to the reference horizontal synchronizing signal, it is when the PLL is unable or out of synchronization with the reproduced horizontal synchronizing signal, so in addition to the phase error due to jitter, There are also frequency and phase errors due to PLL disturbances. As a result, the initial frequency error and initial phase error immediately after switching the synchronization target become even larger than in the above case, and if this continues, not only will synchronization take a long time, but the synchronization itself may even become impossible. Therefore, similarly to the above case, when switching the synchronization target from the reproduced horizontal synchronization signal to the reference horizontal synchronization signal, the phase of the signal at the horizontal scanning frequency ft-+ must be reset so that the initial phase error becomes 0. Therefore, synchronization can be quickly performed.

This effect is greater than the above case.

In the above embodiment, a case has been described in which the present invention is applied to a PLL circuit that performs signal processing digitally, but it is also applicable to a PLL circuit that performs signal processing in an analog manner. However, since digital processing can more accurately reset the counter and phase comparison output, the present invention is particularly suitable for a PLL circuit that performs signal processing digitally.

As described in detail, according to the synchronization pull-in method according to the present invention, a PLL that generates a clock synchronized with a reproduced video signal
In the circuit, when switching the synchronization target to the reference horizontal synchronization signal or the reproduced horizontal synchronization signal, by resetting the horizontal scanning frequency signal so that the initial phase error becomes 0, it is impossible to synchronize with the reproduced horizontal synchronization signal. Alternatively, even when synchronization is lost and the frequency and phase of the PLL are disturbed, or when jitter is large, synchronization can be quickly performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a video signal reproducing device having a PLL circuit according to the present invention, FIG. 2 is a block diagram showing a specific configuration of a PLL circuit to which the synchronization pull-in method according to the present invention is applied, and FIG. FIG. 2 is a flowchart showing the steps of the synchronization pull-in method according to the present invention executed by the PLL control circuit of FIG. 2; FIG. 4 is a block diagram showing an example of the configuration of the phase comparator and N2 frequency divider in FIG. 2; This figure is a characteristic diagram of the phase comparator having the configuration shown in FIG. 4. Explanation of symbols of main parts

Claims (4)

[Claims] (1) A method for synchronizing a PLL circuit that generates a clock synchronized with a reproduced video signal including a horizontal synchronization signal obtained from a recording medium, the standard serving as a time reference for a video signal reproducing device that obtains the reproduced video signal. The horizontal synchronization signal and the reproduced horizontal synchronization signal separated from the reproduced video signal are alternatively used as one input signal of the phase comparator, and the signal at the horizontal scanning frequency obtained by dividing the clock of the voltage controlled oscillator is used as the phase comparator. the other input signal of the comparator, and when selecting the reference horizontal synchronization signal or the reproduced horizontal synchronization signal as the one input signal, reset the phase of the other input signal so that the initial phase error becomes 0; A synchronous pull-in method for a PLL circuit, characterized in that: (2) Synchronization of the PLL circuit according to claim 1, wherein the phase reset is performed when the one input signal is switched from the reference horizontal synchronization signal to the reproduced horizontal synchronization signal. Retraction method. (3) Synchronization of the PLL circuit according to claim 1, wherein the phase reset is performed when the one input signal is switched from the reproduced horizontal synchronization signal to the reference horizontal synchronization signal. Retraction method. (4) The PL according to claim 1, wherein the phase is reset when the reference horizontal synchronization signal is selected as a synchronization target after power is turned on.
Synchronous pull-in method for L circuit.