JPS58208905A - Time base collector - Google Patents

Abstract

PURPOSE:To prevent overflow of a memory, by monitoring an address distance of write and read-out, setting a variable frequency oscillator of a read-out clock to free-run when its value becomes below a prescribed value, and also controlling the oscillator by voltage corresponding to the address distance. CONSTITUTION:Information from a write address counter 5 and information from a read-out address counter 7 are supplied to a subtracter 10, a difference of both the address information is supplied to one input terminal of a comparator 11, and a reference value from a comparing reference value generator 12 is supplied to the other input terminal. When this difference becomes smaller than the reference value, a loop of a PLL circuit of a read-out clock generator 6 is cut by an output of the comparator 11, a difference output from the subtracter 10 is supplied to a D/A converter, and by its output, frequency of the PLL circuit of the clock generator 6 is controlled. In this way, clock frequency is varied in accordance with an address distance of read-out and write, and even if phase displacement of a reproducing signal becomes larger than a time base error, overflow of a memory can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time base collector VC for removing a time axis error in a signal having a time axis error, such as a playback signal of a video tape recorder or an audio tape recorder.

The configuration of this type of time base collector is generally to synchronize an input signal with a time axis error with this input signal, write it to the memory using a write clock having the same time axis error, and then write the written input signal to the memory. The time axis error is removed by reading with a reference read clock that does not have a time axis error. By the way, in this case, if you try to read the signal written to the memory immediately, that is, if you make the initial values of the write address and read address the same, the read will be faster than the write due to the time axis error. As a result, the read signal will be completely different from the original signal. This phenomenon is generally called memory overflow. Conventionally, in order to prevent the memory from overflowing in this way, the read address is usually delayed by an amount that takes into account the time axis error relative to the write address. If the amount of deviation between the read address and the write address, that is, the address distance, is too large, the memory capacity will increase accordingly. Therefore, set an appropriate value that takes into account the maximum time axis error and prevents the memory capacity from becoming too large. It will be selected by

However, even if the address distance between the read address and the write address is selected with the maximum time axis error in mind, there may be large dropouts in the reproduced signal, or there may be cases where, for example, external force is applied to the rotating system. If the servo goes out of order, you will not be able to obtain a reproduced signal, and this will be treated as a time axis error, which may cause the memory to overflow. In other words, input dropouts or variations in the servo system are directly detected as time axis errors, and if this becomes larger than the difference between the write address and read address of the memory, the memory will overflow.

Conventionally, in consideration of such overflows such as dropouts, negative feedback is applied to the tape recorder itself before the memory overflows to prevent the memory from overflowing.

In view of the above points, this invention makes it possible to prevent memory overflow using only the time pace collector without applying negative feedback to the tape recorder5.
This is an attempt to propose a new approach.

Hereinafter, some embodiments of this invention will be described with reference to the drawings.

In FIG. 1, (1) is an input terminal to which an input signal 8A having a time axis error, such as a playback signal from a tape recorder, is supplied, and the signal S through this input terminal (1) is
A is supplied to the human/D converter (2) and the PLL
A write clock generator (4) consisting of a circuit is supplied. In the write clock generator (4) input signal 8
A write clock Wc that has a frequency that is more than twice the highest frequency of A and has the same time axis error as the input signal.
k is obtained. This write clock We k is human/D
The input signal SA is supplied to the converter (2), where it is sampled and converted into a digital signal DA6C. This dental signal DA is supplied to a memory (3). On the other hand, the write clock Wck is the write address counter (5
) k is supplied and the digital signal D is written to the memory (3).
The write address of A is set, and the digital signal D
A are sequentially stored at predetermined addresses in the memory (3).

The input signal 8A is also supplied with a readout clock generator (6)K composed of a PLL circuit, which is synchronized with the input signal frequency but is synchronized with the phase of the input signal SA, that is, the time [
A read clock Re k is obtained which is made not to respond to 11 difference components. In this example, the 8 wave number of this read clock is assumed to be the same as the write clock frequency.

The entertainment clock Shinjima Rck is supplied to the read address counter (7), and the memory (
3) 1: The stored information is sequentially read out, and the read digital signal is supplied to the D/A=t inverter (8)K. This D/A converter (8)K is supplied with a readout clock signal BIck, and the readout digital signal is returned to the original analog signal and output to the output terminal (9). In this case, the start value of the read address is shifted from the read address as shown in Figure 2, and the amount of shift is determined by the maximum time axis error in the input signal as described above. In the 6th second frame, for example, if the read address starts from [000...0], the read address starts from [100...0], that is. The read address is set to start from the center address value of the total capacity of the memory sled (3). In other words, reading is delayed by that amount.

In the present invention, the following considerations are made in order to eliminate memory overflow due to dropouts and the like. That is, write address information from the write address counter (5) and read address information from the read address counter (input) are supplied to the subtractor (IQl).

In this subtracter αa, the difference between both address information (digital signals) is obtained as an output. And this subtractor α [
The output SB of is supplied to one input terminal of the comparator aυ. A reference value from a comparison reference value generator (13) is supplied to the other large output end of the comparator aυ.

and the subtractor (memory (3) detected in IQ)
When the difference between the write address and the read address becomes smaller than the reference value, the output of the comparator αυ cuts the loop of the PLL circuit of the read clock generator (6), and the subtractor (1 (read from 1) and The difference output (digital signal) corresponding to the address distance is D/
A converter (131) is supplied and converted into an analog voltage, which controls the variable frequency oscillator of the PLL circuit of the read clock generator (6).

In this way, the read clock frequency changes according to the read and write address distance, so
Even if the phase shift of the reproduced signal becomes larger than the time axis error estimated in advance, overflow of the memory (3) can be prevented.

An example of a specific configuration of the cutting clock generator (4) and the cutting clock generator (6) is shown in FIGS. 3 and 4, and the above circuit operation will be explained in further detail.

That is, FIG. 3 shows an example of a specific configuration of the write clock generator (4), and FIG. 4 shows an example of a specific configuration of the read clock generator (6).

The write clock generator (4) and the read clock generator (6) are variable frequency oscillators (c) and 1i, respectively.
It has 11 spoons. The reproduced signal through the input terminals 6 and 6 is supplied to the phase ratio converter and 1 through the gate circuits and -. The gate circuit and t6z is for gating a signal having a time axis error component of a large power signal, and a signal that is extracted as a signal having a time axis error is, for example, when a reproduced signal is a video signal. 0 phase comparator where the color burst signal is used! The output signals of the variable frequency oscillators 14 and 111 are divided by a frequency divider and 111ibll to the other input terminals of the gate circuits 431 and 1ti31, and are supplied with the same frequency as the signals obtained from the gate circuits 14 and 111. The comparison output is supplied to a variable frequency triad oscillator through a low-pass filter to control its oscillation frequency, and its oscillation output is outputted to output terminals 44I and 44I through a frequency divider (49I and 49I).

In this case, the time constant τl of the narrow filter (b) of the clock generator (4) is made relatively small, and the output Jfi1f of the variable frequency oscillator ++:11 is synchronized with the gated signal frequency. The output of the variable frequency oscillator (451) is also synchronized with the phase of that signal.In other words, the output of the variable frequency oscillator (c) is locked to the frequency and phase of the input signal, and is synchronized with the time axis of the input signal. On the other hand, the low-pass filter of the readout clock generator (6) has a relatively large time constant τ2, so the output signal of the variable frequency oscillator is synchronized only with the input signal frequency, and its phase is In other words, although the output signal of the variable frequency oscillator is locked to the frequency of the input signal, it does not have the time base error of the input signal.

And in this example, the read clock generator (6)
A switch circuit (608) is provided between the phase comparator B) and the rotor filter.
The output of the phase comparator (to) is supplied to one input terminal of 08), and the output of the D/A converter (13) is supplied to the other input terminal of the switch circuit (60S). Switching is controlled by the output of the comparator S. In other words, when the read and write address distance is larger than a predetermined value, the switch circuit (608) is switched to the state shown in the figure, and a PLL loop is configured. When the read and write address distance becomes smaller than a predetermined value, the switch circuit (6
08) is switched to the state opposite to the state shown in the figure and the PLL
The loop is cut, and when the variable frequency oscillator is used, it is free-run and controlled by a voltage according to the address distance from the D/A converter αJ.

The above example is an example in which a RAM (random access memory) or the like is used as the memory, but a shift register can also be used as the memory. FIG. 5 shows an example of such a case, in which a shift register is used as the memory (c). As an example of the structure of the memory @ in this case, the one shown in FIG. 6 is used. In other words, three shift registers (221
)(222)(223) are provided.

The digital signals (for example, PCM audio signals) through input terminal competition are sequentially switched by a switch circuit (224) and supplied to each shift register (221X222) (223) by the capacity of one shift register. The write clock is generated in @write clock generator G, and is connected to the input terminal - by the configuration shown in FIG.
The signal is synchronized to the frequency and phase of a gated signal (eg, a block synchronization signal) from among the input digital signals through the block synchronization signal. This write clock is sent to the switch circuit (226) (227) through the terminal (229).
(228) Three shift registers (221) (
222) and (223) for each period corresponding to the capacity.

That is, the write clock is never supplied to multiple shift registers at the same time, but is always supplied to only one shift register. Then, the switch circuit (224) and the switch circuit (226) (227) (22
By interlocking the switching of 8), the input digital signal is sequentially written into each shift register (221) (222) (223) by the capacity thereof.

On the other hand, the readout clock generator (2) has a configuration as shown in Fig. 4, and locks only to the frequency of the gated signal from the input digital signal, and performs readout that does not include the time axis error of the input digital signal. You will get a clock.

This read clock is transmitted through the terminal (220) by the switch circuits (226), (227), and (228).
Among the shift registers (221) to (223), the signal is supplied to one shift register that is not in a write state and has been previously written, and furthermore, these switch circuits (226) ( 227) (228)
A readout output is taken out to the output terminal - through a switch circuit (225) which is switched to select the shift register to which the readout clock is supplied in conjunction with the switching of the readout clock. In this case, as shown in FIG. 6, writing is performed from the beginning position of each shift register, and reading is performed from the center position of each shift register.

In this example, the following steps are taken to prevent each shift register from overflowing. That is,
A write clock signal is supplied to a write address counter (e). Also, a read clock signal is supplied to a read address counter (4). The counter (c) starts counting from a count value corresponding to the write initial phase of each shift register, and the counter (2ψ is a count value corresponding to the filling initial phase corresponding to the writing initial phase of each shift register). Counting is started from a count value that differs by a predetermined value from the counter.The count information of these counters is supplied to a subtracter (27), and a voltage Es corresponding to the difference is obtained from the D/A comparator. , is supplied to the readout clock generator ■.The output of the subtracter (2 outputs is also supplied to the comparator Φ and compared with the reference value from the reference value generator (201), and its output is used to generate the readout clock. It is supplied to the vessel (to).

Similarly to the above example, when the output of the subtracter (27) becomes smaller than the reference value, that is, when the read and write address distance becomes smaller than a predetermined value, the read clock generator (2) At the same time that the variable frequency oscillator is free-run, the variable frequency oscillator is
)/A comperum output voltage according to the read and write address distances.

In the above example, only the read clock generator was controlled due to the busy output of the comparator, but as shown in Figure 7,
In the embodiment of FIG. 1, the output of the comparator circle is also supplied to a write clock generator (4) K, and when the read and write address distance becomes smaller than a predetermined value, the read clock is controlled as described above. At the same time, lower the write clock frequency.

In order to lower the write clock frequency from the write clock generator (4), the write clock generator (4) may be configured as shown in FIG. That is, in this case, as a divider when supplying the output signal of the variable frequency oscillator α9 to the phase comparator (43), the frequency dividing ratio is different.
For example, when the - frequency divider (46A) and the address distance between protrusion and writing are larger than a predetermined value, use the frequency divider (46A), and when the address distance is smaller than the predetermined value, use the divider (46B), respectively. Comparator to select (11)
The output of the switch circuit (47) is used to switch the switch circuit (47).

In this way, lowering the clock frequency will have the same effect as the capacity of Memo 'J'+31 has increased, and overflow can be reliably prevented, and the effect of time base correction will also be the same as in the example in Figure 1. can be kept more than

As described above, according to the present invention, the address distance for writing and reading is monitored, and when this address distance becomes less than a predetermined value, the variable frequency oscillator that obtains the read clock is set to free run, and the address distance is By controlling this variable 8-number oscillator with a voltage corresponding to the voltage, overflow of the memory can be avoided.

Note that in the above example, the write clock frequency and read clock frequency are set equal, or when considering time base compression or time base expansion at the same time as timebase correction, the write clock frequency and read clock frequency are The ratio to the frequency is set to a predetermined value.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an example of this invention, Fig. 2 is a diagram for explaining an example of its essential parts, Figs. 3 and 4 are block diagrams of an example of its essential parts, and Fig. 5 is a diagram for explaining an example of its essential parts. FIG. 6 is a block diagram of another example of the invention; FIG. 7 is a block diagram of still another example of the invention; FIG. 8 is a block diagram of an example of the essential part. be. 9 1st evil 2nd;<1 3rd cause birth 51・i +81・1 funeral l evil

Claims (1)

[Claims] a memory to which an input signal having a time axis error is supplied; a write clock generator that generates a write clock for the memory; a read clock generator that generates a read clock for the memory; It has a first counter that determines the write address of the memory, and a second counter that counts the read clock and determines the read address. The clock generator is also configured with a PLL circuit, but the read clock is locked only to the frequency of the input signal, and the read clock is configured to lock only to the frequency of the input signal. The time base error is removed by writing to the memory using a write clock and reading from the memory using the read clock, wherein a difference between address values of the first and second counters is detected; When the difference becomes less than a predetermined value, the read clock generator's PL
When the L loop is turned off and the variable frequency oscillator is free-run, the variable frequency oscillator is controlled by a voltage corresponding to the output of the subtracter at the same time! .