JPS6437186A - Signal processor - Google Patents

Signal processor

Info

Publication number
JPS6437186A
JPS6437186A JP62192462A JP19246287A JPS6437186A JP S6437186 A JPS6437186 A JP S6437186A JP 62192462 A JP62192462 A JP 62192462A JP 19246287 A JP19246287 A JP 19246287A JP S6437186 A JPS6437186 A JP S6437186A
Authority
JP
Japan
Prior art keywords
vco
read
address counter
inputted
error signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62192462A
Other languages
Japanese (ja)
Inventor
Motoaki Kawasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP62192462A priority Critical patent/JPS6437186A/en
Priority to DE19883814447 priority patent/DE3814447A1/en
Publication of JPS6437186A publication Critical patent/JPS6437186A/en
Priority to US07/831,084 priority patent/US5231507A/en
Pending legal-status Critical Current

Links

Landscapes

  • Television Signal Processing For Recording (AREA)

Abstract

PURPOSE:To stably correct the time base by controlling the timing of the impressing of a read clock for a storage means according to a read address value/ write address value. CONSTITUTION:A counting output obtained from a write address counter 17 and that from a read address counter 19 are inputted to a phase comparator 20. An address error signal outputted from the comparator 20 is inputted to a VCO 21 that generates a read clock for a memory 18, and the VCO 21 outputs an oscillating frequency signal controlled corresponding to an error signal from the VCO 21 to supply it to the read address counter 19.
JP62192462A 1987-04-28 1987-07-31 Signal processor Pending JPS6437186A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP62192462A JPS6437186A (en) 1987-07-31 1987-07-31 Signal processor
DE19883814447 DE3814447A1 (en) 1987-04-28 1988-04-28 Apparatus for recording and/or reproducing information signals
US07/831,084 US5231507A (en) 1987-04-28 1992-02-05 Information signal recording/reproducing apparatus with time base correction facility

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62192462A JPS6437186A (en) 1987-07-31 1987-07-31 Signal processor

Publications (1)

Publication Number Publication Date
JPS6437186A true JPS6437186A (en) 1989-02-07

Family

ID=16291700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62192462A Pending JPS6437186A (en) 1987-04-28 1987-07-31 Signal processor

Country Status (1)

Country Link
JP (1) JPS6437186A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58208905A (en) * 1982-05-31 1983-12-05 Sony Corp Time base collector

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58208905A (en) * 1982-05-31 1983-12-05 Sony Corp Time base collector

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