DE3814447A1 - Apparatus for recording and/or reproducing information signals - Google Patents

Abstract

An information signal recording/reproducing apparatus includes a recording part and a reproducing part. With the recording part, an information signal is recorded according to its angle modulation on a recording material in such a way that a signal corresponding to a period of time of the angle-modulated information signal is brought into a predetermined relationship with a reference signal. The reproducing part is designed in such a way that the angle-modulated information signal is demodulated when it is picked up from the recording material, and a time-base correction is performed in a way corresponding to the signal part of the angle-modulated information signal. As a result, it is possible to compensate for the time-base fluctuations occurring during the reproduction in an accurate way by the circuit arrangement, without any special signal being added to the information signal during the recording.

Description

The invention relates to a device for recording and / or reproducing information signals on or from a recording material.

To the known recording / playback devices with one Recording part for recording a color video signal on, for example, disk-shaped magnetic recording media rial and with a playback part for playing the recorded color video signal from the recording medium rial counts a still video system.

In the still video system, for example, a method is used ren applied, in which a color video signal thereby split the color video signal is converted into a luminance signal component and a color beard signal component is divided and then the components in different frequency bands which are modulated and where the recorded signal reproduced by reproducing these modulated components  will give. According to another known method, a Color video signal as a composite color video signal draws and / or reproduces what a luminance signal component and a color beard signal component, which in the Frequency division multiplex are nested. To the systems at which this method for recording and playback is used, for example, a so-called optical memory counts disk system. In the optical disk system the color video signal is on an optical disc together with a color synchronization signal or burst signal recorded contained in the color video signal; the recorded color video signal is recorded using the Color sync signal to correct time base swan reproduced on the color video signal due to Synchronization fluctuations arise from a motor for causes rotation of the disk and the like will.

In the above system for recording and / or playing still video signals was enough Properly preventing the adverse effects of peers Fluctuations in running are not possible because of the recording material rial no reference signal for time base correction recorded has been. In the recording and / or reproducing system the correction is on or from an optical disk the time base of the color video signal by the recorded one Color beard signal enabled. On a signal without a color beard signal such as on a black and white video signal however, a sufficient time base correction is not possible.

Furthermore, in the conventional devices for recording and / or reproducing color video signals two monostable Toggle stages as a circuit for picking out one Part of a reproduced color video signal used who the one in which the color beard signal is inserted. This has too  a complicated circuit arrangement of the device.

With the invention, the above, in which Problems occurring in the prior art are solved.

As a result, the invention is based on the object To provide apparatus for recording information signals which is a recording of the information signals on an up drawing material in such a way that the correction of those occurring on the information signal during playback Time base fluctuations is facilitated without the need for the recording any special signal to the information signal is added.

To achieve the object, the information according to the invention has signal recording device for recording informa tion signals on a recording material a modulation device that receives an input information signal and modulate it into an angle-modulated information signal liert, a correction device that a one period of the angle-modulated information signal corresponding sig nal with a reference signal and the angle modulator te information signal from the modulator corresponds corrected according to the comparison result, and a record device for recording the corrected angle modulated information signal on the recording material rial.

It is also an object of the invention to provide an information signal Playback device to create the exact elimination of the an information signal occurring during playback Allows time base fluctuations without an additional Record any particular signal along with the Information signal required on the recording material is.  

To achieve the object, the device according to the invention has Playing an information signal from a record a playback device by the on drawing material from a modulated information signal which takes on a predetermined period of time Frequency modulated, a demodulating device for demo dulate the modulated information signal from the re and a time base corrector, the the time base of the demodulated information signal corresponds corrected according to the time period of the signal.

Furthermore, the invention is intended to record a video signal be created with which a video signal such is recorded that the on the video signal during the Record on a recording material or during the Playback of the time base of the recording material fluctuations can be suppressed immediately.

For this purpose, the device according to the invention for the draw video signals on a recording material a reference signal generator for generating a reference signal, an angle modulator that the recorded video signal under phase synchronization with the reference signal modulated an angle-modulated video signal, an off Exchange device, the one of the synchronization signal section section corresponding to the angle-modulated video signal of the video signal is replaced by the reference signal, and a Recording device for recording the video signal, whose synchronizing signal section by the reference signal is replaced on the recording material.

The invention is described below with reference to exemplary embodiments len explained with reference to the drawing.

Fig. 1 is a block diagram of the recording part of the recording / reproducing apparatus according to a first embodiment.

Fig. 2 is a block diagram of the reproducing part of the device according to the first embodiment.

Fig. 3, 4 and 7 are block diagrams showing At games for modifications of the embodiment of FIG. 2.

Fig. 5 is a block diagram of a Zeilenspei chers in the playback part of FIG. 4 or 7th

Fig. 6 is an illustration of the waveform of a synchronizing signal part of a video signal and illustrates light the function of the first exemplary embodiment shown in Fig. 1.

Fig. 8 is a block diagram of the recording part of the recording / reproducing apparatus according to a second embodiment.

Fig. 9 is a block diagram of the reproducing part of the device according to the second embodiment.

Fig. 10 to 13 are block diagrams of modifications of Step Example le Ausführungsbei shown in Fig. 9, game show.

Fig. 14 is a block diagram of the recording part of the recording / reproducing apparatus according to a third embodiment.

Fig. 15 is a block diagram showing an example of a variation of the FIG. Third exporting approximately 14 shown example.

Fig. 16 is a block diagram of the reproducing section of the apparatus according to the third embodiment.

Fig. 17 is a block diagram of the recording part of the recording / reproducing apparatus according to a fourth embodiment.

Fig. 18 is a block diagram of the recording part of the recording / reproducing apparatus according to a fifth embodiment.

Fig. 19 is a block diagram of the recording part of the recording / reproducing apparatus according to a sixth embodiment.

FIG. 20 illustrates the frequency allocation of a frequency-modulated video signal in the recording part shown in FIG. 19.

Fig. 21 is a block diagram of the reproducing section of the apparatus according to the sixth embodiment.

FIG. 22 illustrates the frequency allocation of a frequency-modulated video signal in the reproducing part shown in FIG. 21.

FIG. 23 is a block diagram showing an example of a modification of the first embodiment shown in FIG. 1.

FIGS. 24 and 25 show waveforms in a Syn chronbodenteil a playback video signal.

Fig. 26 is a block diagram of circuitry for suppressing curve deformation on the synchronous bottom portion of the playback video signal shown in Fig. 24.

Fig. 27 shows the waveforms of signals on the various parts of the circuit arrangement shown in Fig. 26.

FIG. 28 shows details of an interrogation / hold circuit etc. in the circuit arrangement according to FIG. 26.

FIG. 29 is a block diagram showing an example of a modification of the reproducing part shown in FIG. 4.

In the following, embodiments of the recording / Playback device described in detail. With this execution Example is the device for recording one Video signal on a plate-shaped recording material or to play back a recorded video signal forms, but of course there is no restriction Devices of this type. Rather, the same design is also applicable to other types of devices, for example a tape-shaped recording material is used. Further can record material for recording with light or can be used for magnetic recording. To the devices, at to whom the described design is applicable do not count only the devices for processing video signal mixtures, but also devices for the preparation of component Video signals and any other signals as long as contain these synchronization signals.

Fig. 1 is a block diagram of the recording part of the recording / reproducing apparatus according to a first embodiment. Referring to FIG. 1, a composite color television signal (FBAS signal) be taken, such as a television signal conforming to the NTSC system is applied to an input terminal 8. By means of a clamping circuit 10 , the synchronizing floor or synchronizing floor level of the video signal is placed at a predetermined level. In a boost circuit 12 , a predistortion of the frequency response of the video signal is performed. A subsequent voltage / frequency converter or frequency modulator 14 has two control inputs. A frequency divider 16 divides the frequency of an input signal in half. Fig. 1 further shows a Aufzeichnungsver stronger 18, a loop filter 20 a phase locked loop (PLL), an analog switch 22 for transmitting a signal for a preset by a control signal period, a set / reset phase comparator 24 as play, the integrated circuit MC4044 from Motorola, a crystal oscillator 26 for generating a reference signal with a fixed frequency, a separating circuit 28 for separating a composite synchronizing signal from the video signal received at the input terminal 8 , a line synchronizing signal separating circuit 30 , a clamp pulse generator 32 , a synchronous-floor switching pulse generator 34 , which is used to apply a phase comparison signal over a predetermined period of time, and an image synchronizing signal separation circuit 36 . A magnetic head 38 is designed to record a video signal. A magnetic disk 9 is circulated by means of a motor 29 . At a part of a central core and a hub 27 of the magnetic disk 9 is mounted, a phase pulse pin 25, with means of which the rotational phase of the magnetic disk is detected. 9 From a phase pulse generator 23 , the curve of a phase pulse signal is formed, which is emitted from a phase pulse generator coil 33 each time the pin 25 is detected. From a motor servo circuit 31 , the rotation of the plate motor 29 is controlled in such a way that a certain phase difference between the phase-shaped pulse signal from the phase pulse generator 23 and a picture synchronization signal picked out by the separating circuit 36 is maintained. The phase pulse signal given by the phase pulse generator 23 is also supplied to the recording amplifier 18 for channel switching of the magnetic head 38 . The function of the recording part is as follows:

In Fig. 6, the time base of the video signal is shown on the abscissa, while the signal level is plotted on the ordinate. Part A is the synchronized bottom part or synchronizing level bottom part of the composite video signal. Part B is a part at which the level drop to the synchronizing level bottom part A of the composite video signal is to be detected as a drop to a horizontal or line synchronizing signal. A part C is a part at which the level increase from the synchronizing level bottom part A of the composite video signal is to be detected as an increase in the line synchronizing signal. In the case of a color video signal, the color synchronization signal (burst) is inserted in part C.

At the signal which is received at the input terminal 8 and which is, for example, a composite color video signal or composite signal, the line synchronization signal or synchronization level bottom part A ( FIG. 6) of the clamping circuit 10 is placed at a predetermined DC potential. From the input CVBS signal, the composite synchronizing signal or S signal is picked out by the S-signal separating circuit 28 , after which the clamp pulse generator 32 generates the pulse for setting the level at a point in time which is determined by the line synchronization signal which is determined by the line synchronization signal separation circuit is separated from the S signal.

The input signal thus placed on the predetermined DC voltage potential by means of the clamping circuit 10 is supplied to the lifting circuit 12 . The boost circuit 12 imprints a predetermined frequency response on the leveled-in input signal (such as by increasing the level of the high-frequency components of the signal). After this boost predistortion, the signal is fed to one of the inputs of the frequency modulator 14 . Frequency modulator 14 , for example, like Texas Instruments Integrated Circuit 74 LS628, is equipped with a frequency control input and a translate range control input. The output signal of the boost circuit 12 is applied to the frequency control input of the frequency modulator 14 . In this exemplary embodiment, the frequency modulator 14 carries out a modulation with a frequency assignment to twice a predetermined frequency assignment. After the modulation, the frequency-modulated video signal is fed to the frequency divider 16 , in which the frequency is divided in half. This process results in a frequency-modulated video signal with the desired frequency assignment. In the above-described first embodiment, the input video signal is thus modulated by the frequency modulator 14 to twice the frequency, after which the frequency is then divided by half by means of the frequency divider 16 , thereby preventing a beat resulting from any interference difference between the secondary distortion component of the color subcarrier signal of the frequency-modulated video signal (7.16 MHz for the television signal according to the NTSC system or 8.86 MHz for the television signal according to the PAL or SECAM system) and the frequency-modulated carrier of the video signal. The video signal is thus first modulated to a high frequency band and then shifted to a low frequency band by frequency division.

The output signal of the frequency divider 16 is fed to the phase comparator 24 . The phase comparator 24 compares the phase of the output signal of the frequency divider 16 with the phase of a reference synchronous floor frequency signal from the quartz oscillator 26 . The deviation or error signal output by the phase comparator 24 is fed to the analog switch 22 . The analog switch 22 is only switched on for the period corresponding to the synchronizing level bottom part of the video signal by a pulse signal which is emitted by the switching pulse generator 34 and which has a high level only for a period G shown in FIG. 6. The output signal of the phase comparator 24 is then fed to the Regelkreisfil ter 20 , which forms part of a phase-locked loop. The pass time of the analog switch 22 is determined by the switching pulse generator 34 in such a way that a curve section is avoided which is deformed by the predistortion in the lifting circuit 12 . The error signal emitted by the phase comparator 24 and passed by the analog switch 22 is integrated by the control loop filter 20 , so that a predetermined phase compensation is carried out. The phase-compensated error signal is then fed to the conversion range control input of the frequency modulator 14 (for frequency control in the same way as via the frequency control input). The phase locked loop is thus formed by the loop frequency modulator 14 - frequency divider 16 - phase comparator 24 - analog switch 22 - control loop filter 20 - frequency modulator 14 . On the video signal modulated in this way by the frequency modulator 14 via this phase locked loop, the synchronization level floor frequency is kept at a value by the phase locked loop which corresponds to the predetermined frequency of the reference oscillator. The frequency modulated video signal is then fed to the recording amplifier 18 .

The output signal of the recording amplifier 18 is supplied to the magnetic head 38 for recording on the magnetic disk 9 . The recording timing on the magnetic head 38 will not be described further here.

When recording, the Magnetspei cherplatte 9 synchronously with the vertical or image synchronizing signal is put into circulation, which is picked out by means of the image synchronizing signal separation circuit 36 from the input composite signal.

Fig. 2 is a block diagram of the reproducing part of the recording / reproducing apparatus according to the first embodiment, for example. The parts that are common to the arrangement according to FIG. 1 are designated in FIG. 2 by the same reference numerals and are not described further. Fig. 2 shows a playback amplifier 102, a reproduction equalizer 104, a frequency demodulator 106, a decreasing circuit 108, an analog / digital or A / D converter 110, a Bildspei cher 112 tion for writing and reading under Synchronisie with a Write clock signal WRCLK or a read clock signal RDCLK is formed, a digital / analog or D / A converter 114 , a crystal oscillator 116 for generating a reference signal for reading a signal from the image memory 112 , an amplifier 118 for amplifying the off output signal of the D / A converter 114 , an S-signal separation circuit 120 , a line synchronization signal separation circuit 122 , a synchronous floor switching pulse generator 124 , a pulse delay circuit 126 for a predetermined delay time, a synchronous floor switching element 128 for taking out the Synchronization level bottom part of the output signal of the playback equalizer 104 , a control amplifier 130 , a bandpass file ter 132 , whose pass band center frequency is the frequency f _{ST of} the synchronization level bottom part, a phase comparator 134 with a ring modulator, a low-pass filter 136 for picking out only one error signal output by the phase comparator 134 , a query / hold circuit 138 for calling up and storing the From the output signal of the low-pass filter 136 under a certain time control, a control loop filter 140 for a phase control circuit, a voltage-controlled oscillator 142 , a frequency divider 144 for dividing the frequency of an input signal by half, an oscillator 146 for generating a reference signal 4 f _SC for the Rotary drive of the Magnetspei cherplatte 9 during playback and a frequency divider 148 , the output signal is a reference signal that is used for the rotary drive of the magnetic disk 9 and which has the same frequency as the image synchronization signal.

The function of the reproducing part of the apparatus shown in Fig. 2 according to the first embodiment is as follows: The motor drive reference signal obtained from the signal output from the oscillator 146 with the frequency 4 f _SC by frequency division in the frequency divider 148 is supplied to the motor servo circuit 31 . The motor servo circuit 31 compares the phase of the reference signal with the phase pulse signal from the phase pulse generator 23 and drives the motor 29 in such a manner that the two signals have a phase-locked phase difference. In this way, the magnetic disk is adjusted 9 to a predetermined speed, while by means of a not shown magnetic head is displaced Stellmecha mechanism of the magnetic head 38 to a desired location on the surface of the magnetic disk. 9 Then the frequency-modulated video signal is read out and output with the magnetic head 38 . The frequency modulated playback video signal is very weak, so it is therefore amplified by the playback amplifier 102 . The frequency modulated amplified playback video signal is fed to the playback equalizer 104 by correcting the amplitude and phase of the signal in a predetermined manner. The corrected video signal is fed to the frequency demodulator 106 and demodulated therein. The demodulated video signal is fed to the lowering circuit 108 , in which it is subjected to a rectification with a frequency response which is opposite to that in the predistortion during recording. In this way, the lowering circuit 108 again achieves the original frequency response of the video signal. The equalized video signal is converted into a digital signal by the A / D converter 110 . The digital video signal is written into the image memory 112 . In this case, the write clock signal WRCLK is generated in synchronism with the frequency of the synchronizing level bottom part of the frequency-modulated playback video signal, which will be described in more detail below.

If, for example, only one frame section of the video signal was recorded during the recording, the writing into the image memory 112 is controlled such that only one frame section of the playback video signal is written into the memory. After writing, the signal stored in this way is read out of the image memory 112 under the control of the read clock signal RDCLK from the quartz oscillator 116 and fed to the D / A converter 114 . The D / A converter 114 converts the digital signal read out from the image memory 112 into an analog signal in accordance with the read clock signal RDCLK. The analog signal obtained in this way is fed to amplifier 118 . If the above-mentioned write clock signal WRCLK is exactly synchronous with the frequency of the sync level bottom part of the playback video signal, any time base error of the playback video signal is corrected when it is written into the frame memory 112 . Thereafter, when the signal is read out by means of a predetermined clock signal, a time base correction is carried out, if appropriate, any synchronism fluctuations on the playback video signal which are uncontrolled rotation of the magnetic disk 9 could be suppressed.

The write clock signal WRCLK , which is synchronous with the frequency of the synchronizing level floor part of the frequency-modulated playback video signal, is obtained as follows: A part of the playback video signal from the playback equalizer 104 corresponding to the synchronizing floor or synchronization level floor is picked out by means of the switching element 128 . The pull-out time of the switching element 128 is determined as follows: The S signal is first extracted from the playback video signal corrected for the frequency response by the S signal separation circuit 120 . Thereafter, the line synchronization signal is separated by means of the line synchronization signal separating circuit 122 . This separate line synchronizing signal is fed to the switching pulse generator 124 , which then generates synchronous bottom switching pulses.

After the synchronous floor part has been pulled out of the frequency-modulated playback video signal by the switching element 128 alone, the picked-out part is fed to the control amplifier 130 in order to bring about an amplitude limitation. The output signal of the control amplifier 130 is fed to the bandpass filter 132 , through which unwanted interference signals are eliminated. After passing through the bandpass filter 132 , the synchronizing level bottom part of the playback video signal is supplied as a reference input signal to the phase comparator 134 , which is a ring modulator, namely a multiplier comparator.

The phase comparator 134 compares the phase of this reference signal with the phase of a comparison signal which is fed back via the phase locked loop described below. As a result of the phase comparison, the phase comparator 134 outputs an error signal. Since the phase comparator 134 is a multiplier comparator, the error signal contains some unnecessary high frequency components. These high-frequency components are suppressed by the low-pass filter 136 . The output signal of the low-pass filter 136 is fed to the interrogation / hold circuit 138 . The query / hold circuit 138 retrieves the part of the output signal of the low-pass filter 136 corresponding to the predetermined synchronization level bottom part and stores it. The time for polling and storing by the polling / holding circuit 138 is controlled by the pulse signal generated by the switching pulse generator 124 . However, the timing is adjusted by the pulse delay circuit 126 to compensate for a delay caused by the low pass filter 136 and to retrieve and store the optimal part of the error signal.

The error signal queried and stored in this way is corrected for the phase by the control loop filter 140 of the phase locked loop and then supplied to the voltage controlled oscillator (VCO) 142 . The oscillation frequency of the voltage-controlled oscillator 142 is set to a value which is n times as high as the frequency f _{ST of} the synchronizing level bottom part. That is, the oscillator frequency is nf _ST . In this embodiment, n = 2 is set in the fol lowing. The oscillation frequency of the voltage-controlled oscillator 142 can be changed by the error signal from the control loop filter 140 such that the value 2 f _ST lies in the middle of the change values. The output signal from the voltage controlled oscillator 142 is supplied to the frequency divider 144 . The frequency divider 144 divides the frequency of the input signal by half and in this way generates a variable signal with the central frequency f _ST . The phase-locked loop is formed by a loop phase comparator 134 - low-pass filter 136 - query / hold circuit 138 - control loop filter 134 - voltage-controlled oscillator 142 - frequency divider 144 - phase comparator 134 . The phase-locked loop designed on this causes the oscillation frequency of the voltage-controlled oscillator 142 to become exactly twice as high as the original value. The output signal of the voltage controlled oscillator 142 obtained in this way is fed to the A / D converter 110 and the image memory 112 and used as a write clock signal WRCLK . By this circuit arrangement, the aforementioned synchronous interference component is kept from the image memory 112 , so that a digital reproduction video signal is stored in the image memory 112 , which is obtained by time base correction.

The digital reproduction video signal stored in the image memory 112 is read out with the output signal of the quartz oscillator 116 oscillating at the oscillation frequency 2 f _ST as the read clock signal RDCLK . The read-out signal is fed to the amplifier 118 via the D / A converter 114 .

The re-designed in the manner described above gave part of the device according to the first embodiment enables the advantageous underlying the task To achieve time base correction.

According to the method used in the first exemplary embodiment, the frequency of the synchronous base part or synchronizing signal part of the frequency-modulated video signal is compared with the reference frequency during recording and is recorded to a predetermined frequency after processing. During playback, the recorded signal is subjected to the time base correction by means of the image memory 112 in accordance with the playback frequency of the synchronous bottom part. Compared to the conventional method for time base correction using a color synchronization signal, the device according to the exemplary embodiment is advantageous since the time base correction also enables a signal that does not contain a color synchronizing signal as is the case with a black and white video signal. Furthermore, due to the use of the synchronous video contained in the video signal, it is not necessary to add any other signal to the video signal for time base correction. For the picking out of the synchronous bottom part, the line synchronization signal separating circuit is used in the described exemplary embodiment, which is usually used for processing a video signal. Therefore, the advantageous effect described above can be achieved without many additions to the circuit arrangement being required.

If in the embodiment described above the frequency of the synchronous bottom part of the video signal after the Frequency modulation higher than the frequency of the color auxiliary gersignal is applied, thereby the accuracy the embodiment further improved, so that the Accuracy in conventional time base correction with the Color synchronization signal is exceeded.

FIG. 3 shows a modification of the reproducing part shown in FIG. 2 in the first embodiment. The same parts as those used in the first exemplary embodiment are designated by the same reference numerals in FIG. 3 and are not further explained in the following description, which alone contains the differences in the modification form from the first exemplary embodiment.

In the arrangement according to FIG. 3, the section up to the circuit point at which the playback video signal is written into the image memory 112 is identical to the arrangement shown in FIG. 2. While in the circuit arrangement shown in Fig. 2, the signal is read out by means of the read clock signal at a fixed frequency, the circuit arrangement according to Fig. 3 is changed such that the time base correction is also carried out during the readout, thereby further improving the quality of the playback video signal becomes.

When the signal is read out from the image memory 112 , the time base correction is carried out as follows: A bandpass filter 156 according to FIG. 3 only allows the color bit signal band of the composite color video signal or composite signal to pass through. A color synchronizing signal switching element 158 picks out only the color synchronizing part contained in the color key signal of the video signal. An automatic color control circuit 160 automatically brings the color synchronization part to a predetermined fixed amplitude. A black and white detector circuit 162 determines that the input signal is a black and white video signal when the level of the color synchronizer is partly lower than a predetermined level. The Fig. 3 also shows a multiplying phase comparator 170, a loop filter 172 a phase locked loop, a voltage-controlled crystal oscillator 174, a S-signal chop circuit 164, a horizontal synchronizing signal-Abtrennschal tung 166, and a burst or color synchronizing switching pulse generator 168 . The oscillator 146 generates the reference signal for the rotary drive of the motor 29 with the frequency f _SC . A frequency divider 152 divides the frequency of the input signal into a quarter and is used to generate a clock signal with the frequency f _SC from the signal with the frequency 4 f _SC . The frequency divider 148 generates as in the reproduction part of FIG. 2, the image synchronization signal, which is used as the basis for controlling the rotation of the magnetic disk 9 . A bandpass filter 176 passes the signal with the frequency f _SC and forms a sinusoidal signal from the clock signal with the frequency f _SC from the frequency divider 152 .

The signal output by the D / A converter 114 is supplied to the bandpass filter 156 . The bandpass filter 156 picks out the color beard signal. The separated color beard signal is supplied to the color synchronization switching element 158 , so that only the color synchronization signal part is pulled out and the color control circuit 160 is supplied. From a color synchronization signal switching pulse generator 168 , a switching pulse signal is generated in accordance with the line synchronization signal, which is obtained by separating the S signal in the S signal separation circuit 164 from the output signal of the D / A converter 114 and by separating the line synchronization signal in the line sync Chronization signal separation circuit 166 is obtained from the composite sync signal or S signal. The color control circuit 160 carries out an amplitude control accordingly to the input time of the color synchronization switching pulse signal in such a way that the level of the color synchronization signal part receives a predetermined amplitude. The gain control range of the color control circuit 160 is relatively narrow. Therefore, if a signal does not include a color synchronizing signal part, the color control circuit 160 does not output a signal having a level detected by the black and white detector circuit 162 , which will be described below. The color synchronization signal regulated in this way to the predetermined amplitude is fed to the phase comparator 170 for phase comparison with the reference signal with the fixed frequency f _SC , which is fed to the phase comparator 170 via the bandpass filter 176 . As a result of the comparison, the phase comparator 170 outputs an error signal which indicates an error or a deviation from the reference signal f _SC . A useless high-frequency component contained in this error signal is eliminated by the control loop filter 172 .

In this case, unlike the write-in of the phase-locked loop, no polling / holding process is carried out by means of any polling / holding circuit, because the use of the voltage-controlled quartz oscillator 174 achieves high stability, which makes it unnecessary to save the control signal. Of course, it can also be queried and saved.

The output signal of the control loop filter 172 is supplied to the voltage-controlled crystal oscillator 174 . This controls the phase of the read clock signal. The control loop of the phase locked loop for the read clock signal proceeds as follows: phase comparator 170 - control loop filter 172 - voltage controlled crystal oscillator 174 - image memory 112 - D / A converter 114 - bandpass filter 156 - switching element 158 - color control circuit 160 - phase comparator 170 . The read clock signal emitted by the voltage-controlled quartz oscillator 174 is controlled in such a way that the signal for the color synchronization part of the output signal of the D / A converter 114 exactly matches the reference signal with the frequency f _SC from the frequency divider 152 .

If the video signal is a black and white video signal without a color synchronizing part, this is detected by the black and white detector 162 . In this case, the read clock signal is switched to the output signal of the crystal oscillator 116 having the most frequency. This switching prevents synchronism from frequency fluctuations of the output signal of the voltage-controlled crystal oscillator 174 , which result from the lack of the color synchronization part in the video signal from any faulty function of the phase-locked loop.

FIG. 4 shows a further example of the modification of the circuit arrangement shown in FIG. 2. The same parts as those shown in Figs. 2 and 3 are given the same reference numerals in Fig. 4, and the detailed description of these parts is omitted. A line memory 113 has a write clock input and a read clock input separately from one another. The write addresses and the read addresses are offset against one another to a predetermined extent in order to prevent mutual overlap of the write and read. The amount of displacement is predetermined in accordance with a maximum value of synchronism disturbances which are to be foreseen in the rotary drive system for the magnetic storage disk 9 .

The line memory 113 used in this modification of the reproducing part is shown in detail in FIG. 5.

A memory part 113 -1 of the line memory 113 of FIG. 5 has a memory cell capacity for receiving the data, the valley of a video signal portion for a single horizontal or line scan period, namely a period of 1 H by retrieving according to a clock signal having the frequency 2 f _ST can be obtained. A counter 113 -2 counts the number of pulses of the write clock signal WRCLK and is reset by a reset signal R supplied reset signal RESET . The counter 113 -2 is a ring counter which automatically returns to the count "0" when the video signal section for the period 1 H has been written into the memory part 113 -1 . A decoder 113 -3 decodes the output signal of the write address counter 113 -2 in such a way that the individual memory cells of the memory part 113 -1 are loaded. The output from the A / D converter 110 data are respectively inserted at the determined by the decoder 113 -3 addresses written. A counter 113 -5 counts the pulses of the read clock signal RDCLK . The counter 113 -5 is constructed in the same way as the counter 113 -2 . A decoder 113 -7 is similar to the write address decoder 113 -3 . The data written in an address determined by the decoder 113 -7 are read out and supplied to the D / A converter 114 . After resetting the write address counter 113 -2 , the output signal from the A / D converter 110 is written to the address of the memory part 113 -1 , which corresponds to the pulse count value of the write clock signal WRCLK received by the counter 113 -2 . Thereafter, the above genann th offset time from the resetting of the write address counter 113 is reset to -2 of the read address counter 113 after the lapse of -5. After resetting the counter 113 -5 , the data from the address of the memory part 113 -1 corresponding to the pulse count value of the read clock signal RDCLK are passed to the D / A converter 114 .

Each of the cells of the memory part 113 -1 retains after reading in by a read command from the read address decoder 113 -7 the written data until a next write command from the write address decoder 113 -3.

Therefore, by using the line memory of Fig. 5, the write addresses and the read addresses are offset from each other to an extent corresponding to a given number of addresses, so that writing and reading can be carried out simultaneously. Furthermore, by changing the write clock signal according to the frequency of the synchronous part, the time base of the playback video signal can be corrected.

The circuit arrangement according to FIG. 4 contains a phase comparator 140 , which is, for example, the set / reset phase comparator in the MC4044 integrated circuit from Motorola, a control loop filter 182 in a phase locked loop and a voltage-controlled crystal oscillator 184 . In this modification, the phase comparator 180 compares the phase of the write clock signal with the phase of the read clock signal. This phase comparison prevents their mutual overlap by controlling the read and write clock signals. In the embodiment, the magnetic disk memory 9 makes one revolution during each vertical synchronization period. Therefore, the average value of the clock pulses of the read clock signal within a vertical synchronization period is approximately equal to that of the write clock signal. The write and read addresses of the line memory 113 are counted up each time a write clock pulse or a read clock pulse is received.

Compared to the embodiments with the image memory, the modification example shown in FIG. 4 is particularly advantageous in that the line memory is used, which is cheaper than the image memory. Furthermore, a simplification of the circuit arrangement is also made possible in this modification example.

Fig. 7 shows a further modification of the reproducing part according to the first embodiment. In this case, the time base correction is arrangement of FIG. 4 joined added for reproduction by means of the line memory 113, a circuit arrangement for time base correction using the Farbsynchroni sierteils in the reading from the line memory 113. The use of the color synchronization part for the time base correction is similar to that in the circuit arrangement described with reference to FIG. 3, so that details are not described. The modification of Figs. 7 differs from the above-beschrie surrounded modification example in that a phase comparator 190, a loop filter 192 and an adder 194 adds hinzuge are. In this case, the frequency 4 f _{SC of} the clock pulses from the oscillator 146 is divided by a frequency divider 154 for generating the image synchronizing signal for driving the magnetic disk 9 in order to obtain a reference line synchronizing signal. The reference line synchronizing signal is fed to the phase comparator 190 . The phase comparator 190 compares the phase of the reference line synchronization signal output from the frequency divider 154 with the phase of the line synchronization signal output from the D / A converter 114 contained in the video signal. The error signal obtained by the comparison is fed to the control circuit filter 192 . The output signal of the control loop filter 192 is fed to the adder 194 , in which it is added to the error signal obtained from the color synchronization part. The voltage-controlled crystal oscillator 174 is controlled with the sum of the error signals.

In the above-described control, the phase of the reference line synchronizing signal and the phase of the line synchronizing signal of the video signal output from the D / A converter 114 are rigidly coupled, thereby preventing the overlapping of the write and read addresses of the line memory 113 becomes. By adding the phase control loop for the line synchronization signal, the overlapping of the write and read addresses can be prevented for the following reason: In this modification example, the labeled magnetic disk 9 is circulated synchronously with a reference image synchronization signal, which is generated via the frequency divider 148 from the output signal is obtained with the frequency 4 f _{SC of} the oscillator 146 , which is also used to form the reference line synchronization signal. Therefore, even if the written in the line memory 113 Zeilensyn shows chronisiersignal variations due to uneven rotation of the motor 29, is seen in the middle on a vertical synchronizing the different line synchronizing signal with the reference horizontal synchronizing signal in synchronism. As a result, the modified circuit arrangement for synchronizing the line synchronizing signal of the playback video signal with the above-mentioned reference frame synchronizing signal indirectly causes that the line synchronizing signal obtained in writing and the line synchronizing signal obtained in reading are averaged over each other despite their mutual deviations tune in. This ensures that no mutual overlap of the write and read addresses occurs even after the lapse of a predetermined period of time. Without using this phase-locked loop for the line synchronization signal, the voltage-controlled crystal oscillator 174 is controlled exclusively by evaluating the color synchronization part. In this case, the voltage controlled quartz oscillator 174 is controlled in accordance with an interrogation value that is only detected during the color synchronization period or burst period. Therefore, when certain deviations of the read clock signal occur during the period outside the color synchronization period, such read clock deviations cannot be detected. Under these circumstances, the write and read addresses could overlap. The method for preventing this overlap of the write and read addresses is not limited to the circuit arrangement described above. Rather, the circuit arrangement can be changed such that control is carried out by directly comparing the write and read clock signals in accordance with the preceding description of the modification example shown in FIG. 4.

In the circuit arrangement according to FIG. 7, the frequency divider 154 is also reset by the line synchronization signal which is separated from the video signal from the D / A converter 114 . This serves to eliminate an initial permanent misalignment. Frequency divider 154 is reset at the beginning of playback. For example, the frequency divider 154 is reset by means of a not shown counter to write only a single pulse at the output of the Zeilensynchronisiersignal- separating circuit 166 through to the start of the playback, and then does not generate another pulse, even if the separating circuit 166 outputs the off output signal. This circuit arrangement ensures the correct function of the phase locked loop, which is formed for the line synchronization signal by the phase comparator 190 , the control loop filter 192 , etc.

The advantages of the reproducing part in this modification form are as follows: The use of the inexpensive line memory as in the circuit arrangement shown in FIG. 4 allows a reduction in costs. The circuit arrangement can be simplified. In the circuit arrangement shown in FIG. 4, the control loop filter 182 for the voltage-controlled crystal oscillator 184 must have a relatively large time constant. As a result, a relatively long time is required for the phase locked loop of FIG. 4 to reach the stable state of the phase locked loop. In contrast, in the arrangement according to FIG. 7, the time required to achieve the stable state of the phase locked loop is relatively short, since the line synchronization signal of the video signal read out from the line memory 113 is compared in terms of phase with the reference line synchronization signal output by the frequency divider 154 and these signals are controlled to a rigid phase coupling. With this arrangement, the phase control loop can have a relatively small time constant.

Fig. 8 shows the recording part of the recording / reproducing apparatus according to a second embodiment. In Fig. 8, the same parts as those shown in Fig. 1 are given the same reference numerals, while a detailed description of these parts is omitted below. Fig. 8 shows a phase comparator 40 , a control loop filter 42 which is inserted in a phase locked loop, a voltage controlled oscillator (VCO) 44 and a frequency divider 46 which divides the frequency of an input signal to 1 / n .

The second exemplary embodiment shown in FIG. 8 has the feature that a frequency n f _{H is} selected as the carrier frequency in the frequency modulation of the synchronous bottom part or synchronizing signal part of the video signal, where n is a positive integer and f _{H is} the horizontal or line scanning frequency is. In this regard, the recording part in the second embodiment is different from the recording part in the first embodiment. The function of the recording part in the second embodiment is as follows:

The line synchronization signal picked out by means of the line synchronization signal separation circuit 30 is fed to the phase comparator 40 . The phase comparator 40 compares the phase of this signal with the phase of the output signal of the frequency divider 46 , which is obtained by dividing the frequency of the output signal of the voltage-controlled oscillator 44 to 1 / n of the frequency. As a result, the phase comparator 40 outputs an error signal. The phase comparator 40 is preferably a set / reset phase comparator such as the MC4044 integrated circuit from Motorola. The error signal from the phase comparator 40 is fed to the control loop filter 42 . After a desired phase correction in the control circuit filter 42 , the voltage-controlled oscillator 44 is controlled by the signal. The line synchronization signals supplied to the phase comparator 40 are coupled in a phase-locked manner by this control. Therefore, the phase of the voltage output from the voltage-controlled oscillator 44 with the oscillation frequency n f _{H is} coupled or synchronized with the phase of the line synchronization signal of the input video signal. The output signal of the voltage-controlled oscillator 44 with the frequency n f _H is fed to the further phase comparator 24 as the reference frequency for the frequency of the synchronous floor or synchronizing signal part in the frequency modulation.

A feature of the second embodiment is that the reference oscillator or quartz oscillator 26 according to FIG. 1 is unnecessary due to the circuit arrangement in this embodiment. Another feature is that the operation of the entire device with synchronization with the frequency n f _H prevents the possible occurrence of any interference clock signals due to the use of the quartz oscillator 26 as in the first exemplary embodiment shown in FIG. 1. A next feature in the second embodiment is that setting the frequency of the synchronizing signal part to a frequency which is n times the line synchronizing frequency of the input video signal under phase coupling allows the addition of a phase locked loop for the line synchronizing signal during playback. This design gives the advantage in the second embodiment, which is apparent from the following description of the reproducing part, which is designed for reproducing the video signal recorded by means of the recording part shown in FIG. 2.

Fig. 9 shows the reproducing part of the recording / reproducing apparatus according to the second embodiment. In Fig. 9, the same blocks as those shown in Fig. 2 are denoted by the same reference numerals, and the detailed description thereof is omitted below. The reproducing portion of FIG. 9 differs from that according to Fig. 2 in that the phase control loop is added signal for the linesync. The function of this additional part is as follows: A phase comparator 200 receives the line synchronization signal extracted from the playback video signal from the line synchronization signal separation circuit 122 . The phase comparator 200 compares the phase of this line synchronization signal with the phase of a signal, which is obtained by dividing the frequency of the output signal of the voltage-controlled oscillator 142 by the frequency divider 144 by half and further by another frequency divider 206 to 1 / n . As a comparison result, the phase comparator 200 emits an error signal. The error signal thus obtained is corrected in phase by a control loop filter 202 before being supplied to an adder 204 . The adder 204 is also supplied with a phase error signal which corresponds to the phase difference between the frequency of the synchronizing signal part of the frequency-modulated playback video signal and the phase of the signal which is obtained by dividing the frequency of the output signal from the voltage-controlled oscillator 142 in half. Adder 204 adds these two error signals. With the sum signal error signal thus obtained, the voltage controlled oscillator 142 is controlled. The design of the recording part makes it possible to add the phase locked loop designed in this way to achieve the relationship f _ST = nf _H.

The advantage resulting from the addition of the phase-locked loop for the line synchronization signal is as follows: In contrast to a phase-locked loop for the frequency of the synchronizing floor or synchronizing signal part, the phase-locked loop for the line-synchronizing signal has no risk of side or incorrect engagement, namely a phase engagement an incorrect frequency instead of a phase control via an interrogation value, namely the value of information present only on the synchronization signal part. Therefore, by adding the phase locked loop for the line synchronizing signal, the mis-engagement of the phase locked loop for the synchronizing signal part is effectively prevented. In this regard, the reproducing part shown in FIG. 9 has an advantage over the reproducing part shown in FIG. 2.

The term "incorrect locking" used here has the meaning of a phenomenon in which the phase-locked loop brings about the phase-locked coupling at a frequency which deviates by an integral multiple from the interrogation frequency, which in this case corresponds to the line synchronization frequency. In the reproducing section of Fig. 2 is a phase coupling could at a wrong frequency 2 (f _ST ± mf _H) induce be performed, where m is an integer.

Fig. 10 shows a modification of the above-described reproducing part. Here, a further phase locked loop for the color synchronization signal part or burst part of the video signal is added to the reproduction part. The phase locked loop for the color synchronization signal part is designed in the same way as that in FIG. 3.

Fig. 11 shows another modification of the replay of the second embodiment. In the playback part of FIG. 11 in the in Fig. 9 playback part shown is the line memory of Fig. Posted 4.

Fig. 12 shows another modification of the reproducing part of the second embodiment. In this case, in the reproducing part shown in FIG. 11, the phase locked loop designed as shown in FIG. 7 is added for the color synchronizing signal part.

The functions of the modified reproduced parts shown in FIGS . 10 to 12 can be seen from the preceding description, so that a further description is unnecessary.

FIG. 13 illustrates another modification, the playback part according to the second embodiment. In this case, instead of adding a phase locked loop to prevent the write addresses from reading addresses from overlapping, another method is used for this purpose. In view of the fact that the oscillation frequency of the read clock signal crystal oscillator 116 is equal to 2 f _ST = 2 nf _H , in the reproducing part according to FIG. 13 a vertical or image synchronization signal is output signal by frequency division of the oscillator to 1/525 n by means of a frequency divider 117 reached according to the relationship f _H = 525 fv / 2, where fv is the frame rate. The rotation of the magnetic disk 9 is controlled by the image synchronization signal thus obtained. This configuration ensures that the read clock signal and the write clock signal are indirectly synchronized with one another via the drive provided for the rotation of the magnetic disk 9 , the servo device. This prevents the write addresses from overlapping with the read addresses. This Ge design is of course based on the premise that the recording is carried out under the condition f _ST = nf _H and therefore during the recording the image synchronization frequency (= 2 f _H / 525) is synchronous with f _ST .

Further, 13 is in the reproducing portion of FIG. Not only prevents Fehleinrastung (which could occur in the embodiment according to Fig. 2), but also the use of a single oscillator in the reproducing part, instead of the two oscillators of Fig. 2, namely the oscillator 146, which generates the reference signal for the rotary drive of the motor 29 , and enables the oscillator 116 which generates the read clock signal for reading from the image memory 112 for 80931 00070 552 001000280000000200012000285918082000040 0002003814447 00004 80812r. Furthermore, the perfect synchronization of the two clock signals in the arrangement according to FIG. 13 avoids any interference signals which could otherwise result from the mutual interference of the clock signals.

Fig. 14 shows the recording part of the recording / reproducing apparatus according to a third embodiment. The recording part shown in Fig. 14 is designed such that the synchronizing floor or synchronizing signal part is set to a frequency nf _SC which is n times the frequency f _SC of the color synchronizing signal part of the input composite video signal or BAS signal. Compared to the second exemplary embodiment described above, the setting accuracy of the final frequency f _{ST of} the synchronous base part is increased by using the color synchronization signal part. The design of the recording part shown in Fig. 14 is as follows:

In Fig. 14, the same parts as in the above-described embodiments are designated by the same reference numerals, and the details of these parts are omitted in the following description, which is limited to the points different from the arrangement of Fig. 8.

When a video signal is received at the input terminal 8 , only the color synchronizing signal portion of the video signal corresponding to a switching pulse signal from a color synchronizing signal switching pulse generator 58 is picked out by a color synchronizing signal switching element 50 . By means of a bandpass filter 52 , the unnecessary signal section of the color synchronizing signal picked out in this way is suppressed. The output signal of the bandpass filter 52 is fed to a phase comparator 54 . The phase comparator 54 is preferably a double balanced or ring multiplier or ring modulator, which compares the phase of the signal of the color synchronization signal part with the phase of the output signal of a bandpass filter 66 . The output signal from the phase comparator 54 is fed to a low-pass filter 56 in which the high-frequency components which are not required are eliminated. As a result, the low-pass filter 56 outputs a phase error signal. The phase error signal is fed to a query / hold circuit 62 in which a part corresponding to the color synchronization signal part is received and held, which is then fed to a control circuit filter 64 which is inserted into a phase control loop. The polling time of the polling / holding circuit 62 is controlled by a pulse signal from the color synchronizing signal switching pulse generator 58 . The switching pulse signal is corrected such that a delay caused by the low-pass filter 56 is compensated for. Lersignal The corrected by the loop filter 64 for phase Def a voltage controlled crystal oscillator 72 is supplied, which contains a quartz oscillator. In this way, the oscillation frequency of the quartz oscillator 72 is controlled by the error signal. The output signal of the voltage-controlled quartz oscillator 72 is fed to a frequency divider 70 and further fed to the bandpass filter 66 via a next frequency divider 68 . The bandpass filter 66 forms the output signal of the voltage-controlled quartz oscillator 72 into a sine wave and feeds it to the phase comparator 54 . Thus, the phase locked loop from the loop phase comparator 54 - low-pass filter 56 - query / hold circuit 62 - control loop filter 64 - voltage-controlled quartz oscillator 72 - frequency divider 70 - frequency divider 68 - bandpass filter 66 - phase comparator 54 is formed. This phase-locked loop in this way causes the phase-locked coupling of the oscillation frequency of the voltage-controlled crystal oscillator 72 to a value which is four times the frequency f _{SC of} the color synchronization signal part of the input video signal. A signal with the frequency 2 f _{SC is} fed from the frequency divider 70 to the further phase comparator 24 . As a result, the frequency of the synchronous bottom part is set to 2 f _SC .

This frequency value 2 f _SC can be changed to any other value as long as it is an integer multiple of the frequency value f _SC . An advantage of the third exemplary embodiment is that due to the use of the phase-locked loop described above for the color synchronizing signal part, the accuracy of the input signal for the adjustment of the frequency of the synchronous component part 24 supplied to the phase comparator 24 with the frequency 2 f _{SC is} improved.

Fig. 15 shows an example of a modification of the recording part shown in Fig. 14 according to the third exemplary embodiment. The modified recording part differs from that shown in FIG. 14 in that a phase locked loop for the line synchronization signal is added to the circuit arrangement according to FIG. 14. This enables that even if the input video signal is a black / white signal and therefore does not contain a color synchronization signal part, the voltage-controlled crystal oscillator 72 outputs an output signal at a frequency which is 455 times the frequency f _{H of} the line synchronization signal. Therefore, the frequency f _{ST of} the synchronous bottom part can also be set to a value f _ST = 455 f _H = 2 f _SC when entering a black / white video signal. If the input signal in the circuit arrangement according to FIG. 14 is a black / white video signal, the voltage-controlled quartz oscillator 72 would oscillate uncontrolled or freely in the absence of any error signal.

The above-mentioned phase locked loop for the line synchronizing signal is designed as shown in FIG. 15. In FIG. 15, the same parts as those shown in FIG. 14 are designated by the same reference numerals and are not described in more detail below. Fig. 15 shows a phase comparator 74, a loop filter 76 of the Phasenre gelkreises and a frequency divider 78, in which the frequency of the input signal is divided to 1/455. The phase comparator 74 compares the phase of the line synchronization signal separated from the input video signal with the phase of a signal which is obtained by frequency dividing the output signal of the voltage-controlled quartz oscillator 72 by the frequency divider 70 by half and further by the next frequency divider 78 to 1/455 . As a comparison result, the phase comparator 74 emits an error signal. The error signal with respect to the phase is compensated by the control loop filter 76 . The phase compensated error signal is supplied to an adder 80 where it is added to the error signal obtained for the color synchronizing signal part of the input video signal. If the input signal is a color video signal, the error signal obtained for the line synchronization signal and the other error signal for the color synchronization signal part on the voltage-controlled quartz oscillator 72 cooperate in such a way that its output signal is fixed phase-locked to a frequency which is four times the frequency f _{SC of} the input Color synchronization signal is. No error signal for the color synchronizing signal part is obtained from an input black / white video signal. However, since the error signal for the line synchronization signal is still available, the voltage-controlled quartz oscillator 72 is fixed in a phase-locked manner to a signal frequency f _H × 455 × 2. As a result of this design, a reference signal with the frequency 2 f _{SC is} supplied to the phase comparator 24 even in the case of an input black / white video signal. Therefore, the frequency of the synchronous base part is brought into agreement with the signal frequency f _H × 455. Furthermore, the uncontrolled or free oscillation of the quartz oscillator 72 is prevented when a black / white video signal is input. This design of the recording part ensures the proper functioning of a phase-locked loop for the line synchronization signal in the reproducing part of the device, which will be described below with reference to FIG. 16.

Fig. 16 shows the reproducing part of the recording / reproducing apparatus which is designed to reproduce the video signal recorded by means of the above-described recording part. The main feature of the reproducing part shown in FIG. 16 compared to the circuit arrangement according to FIG. 9 is the following: While a particular frequency n f _{H is} used as the reference frequency in the circuit arrangement according to FIG. 9, the circuit arrangement according to FIG . 16, a phase-locked loop used to start a Bezugssig for the sync tip portion of the playback video signal nalfrequenz 2 f _SC sets. The function of the additional part of the circuit arrangement is as follows:

The phase comparator 200 compares the phase of a signal obtained by frequency-dividing the output signal of the voltage controlled oscillator 214 with the center frequency 4 f _SC by a frequency divider 220 with the phase of a line synchronizing signal controlled by an automatic frequency control circuit (AFC) 123 . A frequency divider 216 divides the frequency 4 f _{SC of} the signal from the voltage controlled oscillator 214 in half. A bandpass filter 218 has a pass band at the frequency 2 f _SC .

In this exemplary embodiment, the write clock signal for writing into the image memory 112 is controlled by means of the synchronous floor part of the video signal which has been modulated to the frequency 2 f _SC . Therefore, a higher accuracy than can be achieved with a method in which the time base correction takes place at the frequency f _SC . Furthermore, the use of the phase locked loops with the phase comparators 200 and 134 effectively prevents the incorrect engagement. It can also be seen that all of the parts shown in Fig. 16 except a write clock generator circuit WR framed by a broken line can be replaced at will by the circuit parts shown in Figs. 10, 11 and 12.

Of the above-described embodiments the recording method according to the third embodiment game particularly advantageous for a device in which, as in In the case of a video camera, a clock signal generator for the Er witnesses of the color subcarrier is included, namely because because the recording process with very little change tion of the known circuit arrangement is applicable.

The signal referred to here as the "synchronization signal part" cut contains the signals on the leading edge and the Rear flank of the synchronous base part.

As described above, the first time example of a recorded video signal by Pha comparison of the synchronizing signal part of the video signal n as a corresponding signal with a reference frequency signal and by correcting the time base fluctuations according to the Phase comparison result reproduced. Therefore, that enables first embodiment a sufficient correction of Time base fluctuations also in the case of a black and white video signals that does not contain a color synchronization signal.

In the second embodiment, the time base fluctuations according to a part of the synchronizing signal corrected signal. The second embodiment therefore enables sufficient correction of the time base fluctuations even with a black and white video signal that contains no color synchronization signal. This is one ensures higher quality of the playback video signal.

The following is a recording / reproducing device according to described a fourth embodiment:

Fig. 17 shows the recording part in the fourth exemplary embodiment. In Fig. 17, the same components and parts as those shown in Fig. 1 are designated with the same reference characters, while these components and parts are not described in the fol lowing. According to Fig. 17, an input signal, which is for example a composite color video signal or composite signal and which is received at the input terminal 8 , the clamping circuit 10 , in which the line synchronization signal part, namely part A of FIG. 6 to a predetermined DC voltage potential is set. The clamp pulse signal for this level is determined by the clamp pulse generator 32 by first generating the composite synchronizing signal from the input composite color video signal by the S signal separating circuit 28 , then separating the composite synchronizing signal or S signal by the line synchronizing signal. Isolation circuit 30, the line synchronization signal is picked out and the clamping pulses are formed at the times corresponding to the line synchronization signal.

The input signal determined by the clamping circuit 10 to the predetermined DC potential is processed by the lifting circuit 12 such that it receives a predetermined frequency characteristic or a predetermined frequency response (for example, by raising the level of the high-frequency component of the input signal). The input signal predistorted in this way is fed to the input of the frequency modulator 14 . In the fourth exemplary embodiment, the frequency modulator 14 modulates the signal by assigning frequencies which are twice as high as the predetermined assignment frequencies. After the frequency modulation, the frequency-modulated video signal is fed to the frequency divider 16 , in which the frequencies are divided in half. This gives the frequency-modulated video signal the desired frequency allocation. In this fourth embodiment, the inputted video signal is modulated by the frequency modulator 14 to a frequency which is twice as high as the predetermined frequency, after which the frequency is then divided in half by the frequency divider 16 . The reason for this is as follows: The subcarrier of the frequency-modulated video signal has a secondary harmonic component or harmonic (with the frequency 7.16 MHz if the video signal is a television signal according to the NTSC system, or 8.86 MHz if the signal is a television signal according to the PAL or SECAM system). The above-described method of dividing the frequency after the frequency modulation into the higher frequency band is first performed is for the purpose of preventing interference between this second harmonic and the carrier in frequency modulation.

The output signal of the frequency divider 16 is fed to a terminal L of a changeover switch 300 . A reference signal with the synchronous ground frequency is applied from a reference signal generator 301 to the other connection H of the changeover switch 300 . The changeover switch 300 is switched to the terminal H only for the period corresponding to the syn chronboden part of the video signal by a pulse signal which is generated by a Zeitimpulsgenera gate 302 and which has a high level only for the period A shown in FIG . Outside of this time, the changeover switch 300 remains switched to the L connection. The length of time during which the changeover switch 300 is switched to the H connection is determined by the timing pulse generator 302 in such a way that a signal part with a distorted curve shape resulting from the predistortion in the lifting circuit 12 is avoided.

In this way, a signal, the frequency of which corresponds to the synchronous bottom part of the video signal modulated in the frequency modulator 14 , is replaced by the reference signal generated by the reference signal generator 301 with a predetermined fixed frequency. The frequency-modulated video signal, in which the synchronous bottom part is replaced by the signal with the fixed frequency, is fed to the recording amplifier 18 .

The output signal of the recording amplifier 18 is supplied to the magnetic head 38 for recording on the magnetic disk 9 . The details of the recording timing control via the magnetic head 38 will not be described. When recording, of course, the Magnetspei cherplatte 9 is synchronously circulated with the image synchronization signal, which is separated by the image synchronization signal separation circuit 36 from the input composite video signal.

The playback part of the recording / playback device according to the fourth embodiment is the same as in gestal the first, second and third embodiment tet, so that the description is therefore unnecessary.

As described above, the fourth Embodiment instead of a the synchronization signal part of the signal representing the video signal is a normal or Reference frequency signal recorded. This arrangement enables light in the device the sufficient correction of the time base fluctuations even in the event that the video signal does not Color synchronization signal contains.

Fig. 18 shows the recording portion of a recording / reproducing apparatus according to a fifth embodiment. In Fig. 18, the same components and parts as those shown in Fig. 17 are denoted by the same reference numerals and are not described in detail hereinafter. Fig. 18 shows a switch 303, a switching member 304, a row synchronisierperioden- or horizontal period Retarded approximate circuit 305 for delaying a Zeilenabtastpe Riode H, monostable multivibrators 306 and 307, a zero crossing detector 308, a frequency divider 309 and a reference signal generator 310 .

In comparison to the fourth embodiment, a feature in the fifth embodiment is as follows: While a signal that is used instead of the synchronous bottom part of the frequency-modulated video signal is kept connected by switching with the other parts of the video signal, the frequency modulation of the Vi deosignals selected a frequency n f _H as the frequency of the synchronous base part. In this point, the fifth embodiment differs from the fourth embodiment shown in FIG. 17. The function in the fifth exemplary embodiment is as follows: The frequency-modulated video signal obtained from the frequency divider 16 is fed to a connection of the changeover switch 303 and the switching element 304 . The switching element 304 is switched on only during the period during which a signal from the monostable flip-flop 306 has the high level. When the switch is turned on, the frequency modulated video signal is supplied to the zero crossing detector 308 . The changeover switch 303 normally remains switched to the L terminal. During the period during which the monostable multivibrator 307 forms a high-level signal from a zero-crossing pulse OP emitted by the zero-crossing detector 308 , the changeover switch 303 is switched to the other terminal H at which the changeover switch establishes the connection for this period.

Further details of the function in the fifth exemplary embodiment are as follows: When the composite video signal is received at the input terminal 8 , the line synchronization signal is separated by the S signal separation circuit 28 and the line synchronization signal separation circuit 30 . The separated line synchronization signal is fed to the clamping pulse generator 32 and the 1 H delay circuit 305 .

The delay circuit 305 delays the line synchronization signal by one line scanning period H. The fall of the delayed by the delay circuit 305 and output line synchronization signal causes at the monostable Kipp generating step 306 a high level signal which is supplied to the switching element 304 via a sync tip period. Switch 304 also receives the frequency modulated video signal formed in the same manner as in the fourth embodiment. The switching element 304 supplies the frequency-modulated video signal to the zero crossing detector 308 only for the period of time during which the signal emitted by the mono-stable flip-flop 306 has the high level. Therefore, the zero crossing detector receives a signal that speaks ent the synchronous bottom part of the frequency-modulated video signal. The zero crossing detector 308 determines the polarity of the frequency-modulated video signal by signal integration. As a result, the zero crossing detector 308 either detects the rise or fall of the signal curve, whereupon the zero crossing detector generates the zero crossing pulse OP at the time of a first zero crossing, for example of the rising curve part. The zero crossing pulse OP is fed to the monostable multivibrator 307 and the frequency divider 309 . The zero crossing detector 308 can also be designed such that it generates the zero crossing pulse OP at the time of the zero crossing of the falling curve part instead of the rising curve part. The frequency divider 309 receives from the reference signal generator 310 a reference or normal signal with the frequency mf _SC , where m is an integer above "2". The frequency divider 309 divides the frequency of this signal into n / m (where n is a positive integer), to thereby obtain a reference signal with the frequency nf _SC , which is applied to the terminal H of the switch 303 .

Furthermore, the zero crossing pulse OP from the zero crossing detector 308 is also supplied to this frequency divider 309 to reset the frequency divider 309 at the time of input of this pulse. In particular, the frequency divider 309 is equipped with a counter and is designed in such a way that the reset at the time of the zero crossing of the frequency-modulated video signal enables the generation of a signal associated with the frequency-modulated video signal. In this case, the continuity of the signal can be accurately maintained by giving the reference signal output from the reference signal generator 310 a high frequency.

The monostable multivibrator 307 , which receives the aforementioned zero-crossing pulse OP , generates a high-level signal at the time of input of the zero-crossing pulse OP via a synchronous period. According to the preceding statements, the function of the switch 303 is controlled by the signal from the monostable multivibrator 307 . Therefore, the changeover switch 303 is switched to the terminal H for the period, namely for the one synchronous floor period during which the signal has the high level. Therefore, during the period corresponding to the synchronous bottom part of the frequency-modulated video signal output from the frequency divider 16 , the video signal is supplied to the recording amplifier 18 in a state in which a part is replaced with the continuous waveform by the signal which is common to the reference signal generator 310 and the frequency divider 309 is generated at a stable frequency. Thereafter, the video signal is recorded on the magnetic disk 9 in the same manner as in the fourth embodiment.

The playback part of the recording / playback device according to the fifth embodiment is the playback part at the first, second and third embodiment are the same tig, so that a further description is unnecessary.

When replacing the synchronous bottom part of the video signal this is ensured by a signal of predetermined frequency the fifth embodiment used method that the Signal with the predetermined frequency instead of the synchronous bottom part of the video signal is used in a state where the waveform is frequency modulated with the others Parts of the video signal is kept contiguous. Therefore can the frequency demodulation during playback without any what waveform distortions or disturbances to the ins points are accomplished. In this execution for example, each part of the synchronization signal contains not only that Synchronous bottom part, but also its front flank and rear flank. Furthermore, with the circuit arrangement according to this Embodiment the time base correction according to a Synchronizing signal part corresponding signal before be taken if the video signal is not color synchronized contains signal. As a result, in the embodiment playback of the video signal with higher quality safely posed.

In the case of an FBAS signal such as a color television signal according to the NTSC system, for example, a luminance signal in frequency division multiplexing is interleaved with a chrominance signal, which is generated by a color subcarrier signal (with 3.58 MHz) which is modulated in two-phase quadrature modulation with two color difference signals ( RY and BY ). is formed. When the CVBS signal is recorded by direct frequency modulation of the same, interferences between this color subcarrier signal and the lower sideband of the frequency-modulated color video signal result in Moire interference, since a color synchronization signal is added to the composite video signal, which corresponds to the color subcarrier. This could degrade the color video signal during playback.

A sixth embodiment is designed to solve this problem. Fig. 19 shows the recording part of the recording / reproducing apparatus according to the sixth example approximately exporting. A composite color video signal or composite signal, such as a color television signal according to the NTSC system, is received at an input terminal 400 according to FIG. 19. In a clamp circuit 401 , the synchronous bottom part of the input video signal is set to a predetermined level. 402 denotes a lifting circuit. A voltage-frequency converter 403 has two control inputs and serves as a frequency modulator. With a comparator 404 , the secondary distortion or harmonic of the curve of a frequency-modulated video signal is reduced. With a band pass filter 405 , an unnecessary frequency band is eliminated before a frequency conversion. With 406 a multiplier is designated. Another bandpass filter 408 only passes a certain band after the frequency conversion. With a comparator 409 , the secondary distortion or the second harmonic is eliminated. The Fig. 19 also shows a phase comparator 410, a switch 411, a Regelkreisfil ter 412 for a phase locked loop and a recording amplifier 413th The frequency-modulated video signal for recording is output at an output terminal 414 to which a magnetic head, not shown, is connected.

From an S signal separation circuit 415 , the composite synchronization signal is separated from the video signal applied to the input terminal 400 . Fig. 19 shows a line synchronizing signal separating circuit 416, a clamp pulse generator 417, a sync tip-Schaltimpulsgenera gate 418, a color burst switching pulse generator 419 and a Farbsynchronisiersignal- or burst switching member 420th

A band pass filter 421 passes the predetermined band of the color synchronizing signal part. A low pass filter 423 serves to output only a phase error signal. A pulse delay circuit 424 generates a poll / hold pulse by delaying a color synchronizing signal switching pulse. The Fig. 19 also shows a query / hold circuit 425, a loop filter 426 for a phase-locked loop, a voltage controlled oscillator 427, a Frequenztei ler 428, which divides the frequency of the input signal to a third, a frequency divider 429, of the frequency of a crossing signal divides half, and a bandpass filter 430 , which forms the output signal of the frequency divider 429 into a Si nut signal. The function of the recording part of the recording / playback device designed in this way is as follows:

A circuit part K framed by a dashed line in FIG. 19 represents a part for the generation of control signals. Specifically, in circuit part K a predetermined clamping pulse signal, a synchronous switching pulse signal, is generated from the CVBS signal received at input terminal 400 . which determines a synchronous bottom part, a clock signal with the frequency 6 f _SC , which is phase-coupled with the subcarrier of the color synchronizing signal part, and a clock signal with the frequency 2 f _SC , which is phase-coupled with the color synchronizing signal subcarrier. The function of this circuit part K is as follows:

The composite synchronizing signal obtained from the S signal separating circuit 415 is supplied to the line synchronizing signal separating circuit 416 . The separation circuit 416 passes on the separated line synchronization signal. Thereafter, according to the line synchronizing signal from the clamping pulse generator 417, the clamping pulse signal, from the synchronous switching pulse generator 418 the switching pulse signal for the synchronous bottom part and from the color synchronizing signal switching pulse generator 419, the switching pulse signal for the color synchronizing signal part is generated. The color synchronizing signal switching element 420 only takes out the color synchronizing signal part from the CVBS signal input at the input terminal 400 in accordance with the switching pulse signal from the switching pulse generator 419 . The signal of the color synchronization signal part picked out in this way is fed to the band-pass filter 421 , in which the frequency band regions which are not required are eliminated from the signal. Thereafter, the color synchronizing signal part signal is supplied to the phase comparator 422 . The phase comparator 422 , which is preferably a ring modulator, compares the phase of the color synchronizing signal part with the phase of the output signal of the bandpass filter 430 . The output signal of the phase comparator 422 is applied to the low-pass filter 423 in which high frequency parts that are not required are suppressed. The low pass filter 423 output signal thus obtained is a phase error signal. The phase error signal is supplied to the query / hold circuit 425 . A portion of the phase error signal corresponding to the color synchronization signal part is received and held by the interrogation / hold circuit 425 . The recorded output signal of the query / hold circuit 425 is fed to the control loop filter 426 of the phase locked loop. The polling time of the polling / holding circuit 425 is determined by the color synchronizing signal switching pulse signal, which is corrected by the pulse delay circuit 424 such that the delay caused by the low-pass filter 423 is compensated for. The phase signal corrected by the control loop filter 426 is supplied to the voltage-controlled oscillator 427 and is used to control the oscillation frequency thereof. The output signal of the voltage controlled oscillator 427 is fed to the frequency divider 428 and further via the next frequency divider 429 to the bandpass filter 430 . Bandpass filter 430 forms the oscillator output signal into a sine wave. The sinusoidal signal obtained in this way returns to the phase comparator 422 . The phase locked loop consists of the loop phase comparator 422 - low pass filter 423 - query / hold circuit 425 - control loop filter 426 - voltage-controlled oscillator 427 - frequency divider 428 - frequency divider 429 - bandpass filter 430 - phase comparator 422 and causes the oscillator frequency of the voltage-controlled oscillator 427 to be phase locked a frequency is set which is 6 times the frequency f _{SC of} the inputted color synchronizing signal part.

At the CVBS signal supplied via the input connection 400, the level is determined by the clamping circuit 401 by means of the clamping pulse signal which is generated by the clamping pulse generator 417 attached in the circuit part K. After the level has been set, the video signal is fed to the boost circuit 402 for predistortion. The predistorted CVBS signal is fed to frequency modulator 403 for frequency modulation. If the Fre achieved in the recording quenzzuteilung which is rich in Fig. 20 marked with a Frequency Ranges, the Fre obtained at the frequency modulation is frequency range of the _SC is assumed to be b designated region, wherein a imple f wetting carrier of frequency. 6

After the frequency modulation has ended, the now frequency-modulated video signal is fed to the comparator 404 , in which secondary harmonic components or second harmonics are eliminated. This increases the energy of the basic wave component of the video signal. The output signal of the comparator 404 is fed to the bandpass filter 405 , in which the useless frequency band range is suppressed (namely the range below 21.5 MHz, since there are only very low harmonics of the carrier at 3.58 MHz). As a result, only the fundamental component remains as shown as region b in Fig. 20. The output signal of the bandpass filter 405 is supplied to the multiplier 406 , in which it is multiplied by the signal obtained by shaping the voltage controlled oscillator 427 in the Circuit part K is formed under synchronization with the Farbsynchro nisiersignalteil signal obtained with the frequency 6 f _SC to a sinusoidal signal. As a result, a frequency-modulated video signal component with the assignment frequency range shown in FIG. 20 and a further component different from this component are obtained. From these components, only the frequency-modulated video signal component a according to FIG. 20 is picked out by means of the bandpass filter 408 . The frequency-modulated video signal component selected in this way is fed to the comparator 409 . Comparator 409 amplifies the energy of the frequency modulated video signal and reduces its second harmonic. The output signal of the comparator 409 is fed to the phase comparator 410 . The phase comparator 410 compares the phase of the output signal of the comparator 409 with the phase of the clock signal with the frequency 2 f _SC which is obtained synchronously with the color synchronizing signal from the frequency divider 428 in the circuit part K. The phase comparator 410 outputs an error signal as the phase comparison result. The error signal is fed to the switch 411 . The switch 411 is switched on by the switching pulse signal generated by the switching pulse generator 418 in the circuit part K for the period of time corresponding to the synchronous base part. Thus, the switch 411 only passes the error signal during this period. The error signal emitted in this way is fed to the control loop filter 412 of the phase locked loop, in which it is subjected to a predetermined correction. The corrected error signal is then fed back to the correction input of the frequency modulator 403 . In this way, the frequency-modulated video signal output by the comparator is precisely set to the frequency 2 f _SC synchronous with the color synchronization signal part. The frequency-modulated video signal is supplied from the comparator 409 to the recording amplifier 413 and further to a magnetic head, not shown, by which it is recorded on a magnetic disk used as a recording material. The magnetic head, the magnetic disk, the disk rotating drive device and the control device for the drive device are all designed in the same manner as in the other embodiments described above, so that further description is unnecessary.

The playback part of the recording / playback device according to the sixth embodiment is as follows tet:

Fig. 21 shows the circuit arrangement of the playback part. At an input terminal 431 , a frequency-modulated replay video signal picked up by a magnetic head, not shown, from a magnetic disk, also not shown, is received. The playback section includes a playback amplifier 432 , a playback equalizer 433 , a bandpass filter 434 for suppressing unnecessary band areas of the video signal before the frequency conversion, a multiplier 435 , a bandpass filter 436 , a further bandpass filter 437 , which only allows a predetermined frequency band to pass after the frequency conversion, a frequency demodulator 438 , a lowering circuit 439 for the equalization, an A / D converter 440 , a memory 441 , a D / A converter 442 , a crystal oscillator 443 for generating a read clock signal and an output terminal 444 for the output of the composite playback video signal.

A circuit part L framed by a dashed line in FIG. 21 is used to generate a clock signal with the frequency 6 f _SC , which is phase-locked to a signal with the frequency 2 f _SC , which contains the time base fluctuations of the synchronous bottom part of the frequency-modulated playback video signal . The clock signal 6 f _SC is formed both from the frequency-modulated playback video signal and from the demodulated playback video signal.

The circuit part L contains an S-signal separation circuit 445 , a line synchronization signal separation circuit 446 , an automatic frequency control circuit (AFC) 447 , a phase comparator 448 , a control loop filter 449 which is inserted into a phase control loop, a synchronous floor switching pulse generator 450 , a pulse delay circuit 451 for recording and holding the pulse signal by delaying it for a predetermined period of time, a synchronous-floor switching element 452 , a control amplifier 453 , a bandpass filter 454 , which only allows a portion of the video signal in the vicinity of the component with the frequency 2 f _SC , which passes through Modulation frequency of the synchronous bottom part of the video signal is a phase comparator 455 , a low-pass filter 456 which only allows a phase error signal to pass through, an interrogation / hold circuit 457 , a control loop filter 458 of a phase control loop, an adder 459 , a voltage-controlled oscillator 460 , a frequency divider 461 , which divides the frequency of an input signal down to a third, a bandpass filter 462 , which forms a clock signal from the frequency divider 461 into a sine signal, and a frequency divider 463 , which divides the frequency of an input signal to 1/455 and which is used from the Clock signal with the frequency 2 f _SC to form a signal with the line synchronization signal frequency.

The function of the circuit part L according to FIG. 21 is as follows:

From the frequency-modulated playback video signal from the playback equalizer 433 , the synchronous bottom switching element 452 picks out a part corresponding to the synchronous bottom part. The pull-out time is determined by a synchronous floor switching pulse signal generated by the switching pulse generator 450 as follows: First, the composite synchronizing signal is separated by the S-signal separating circuit 445 from the demodulated video signal, which was equalized by the lowering circuit 439 . Thereafter, the line synchronizing signal is extracted from the composite synchronizing signal by the separating circuit 446 . Thereafter, the switching pulse generator 450 generates the synchronous floor switching pulse signal from the line synchronization signal.

The switching element 452 only picks out the synchronous bottom part of the frequency-modulated playback video signal. Then the picked signal is adjusted by the control amplifier 453 to a predetermined amplitude and then fed to the bandpass filter 454 . The bandpass filter 454 suppresses unwanted interference signals. The synchronized bottom part of the frequency-modulated playback video signal prepared in this way is supplied to the multiplier phase comparator 450 as a reference input signal.

The phase comparator 455 compares the phase of the comparison signal fed back from the phase-locked loop with the phase of the reproduced reference signal and generates an error signal. Since the phase comparator 455 is a multiplier comparator, the error signal contains some useless components in the high frequency band. Therefore, the high-frequency components are suppressed by the low-pass filter 456 . The output signal of the low-pass filter 456 is supplied to the query / hold circuit 457 , in which the part corresponding to the synchronous bottom part is picked up and held from the output signal of the low-pass filter 456 . The time of recording and holding in the query / hold circuit 457 is determined by the synchronous floor switching pulse signal, which is generated by the switching pulse generator 450 . So that the optimal part of the error signal is recorded and recorded, the time of the switching pulse is set by means of the pulse delay circuit 451 .

The phase of the queried error signal is corrected by means of the control loop filter 458 of the phase control loop. The phase-corrected error signal is added in the adder 459 to another error signal which is obtained in the manner described below from the other control loop filter 449 . The sum of the error signals is fed to the voltage-controlled oscillator 460 , the oscillation frequency of which is set to 6 f _SC .

The oscillation frequency of the voltage-controlled oscillator 460 is increased or decreased away from the frequency 6 f _SC by the sum error signal from the adder 459 . The output signal from the voltage-controlled oscillator 460 is fed to the frequency divider 461 for frequency division to a third. The signal obtained in this way from the frequency divider 461 with the frequency 2 f _SC is fed via the bandpass filter 462 to the phase comparator 455 . The phase locked loop consists of the loop phase comparator 455 - low pass filter 456 - query / hold circuit 457 - control loop filter 458 - adder 459 - voltage controlled oscillator 460 - frequency divider 461 - bandpass filter 462 - phase comparator 455 and causes the output signal of the voltage controlled oscillator 460 to be at frequency 6 f _{SC is} phase locked to the signal with the frequency 2 f _SC , which contains the time base fluctuations of the synchronous bottom part of the frequency-modulated playback video signal received at the input terminal 431 . The output signal of the voltage-controlled oscillator 460 obtained in this way is fed to the band-pass filter 436 as a frequency conversion carrier signal for the multiplier 435 , the A / D converter 440 as a clock signal and the memory 441 as a write clock signal. This makes it possible to store a digital video signal in the memory 441 which does not contain any synchronization or synchronization errors.

Next, the circuitry for forming the error signal from the loop filter 449 for the adder 459 will be described: the phase comparator 455 receives the line synchronizing signal extracted from the playback video signal by the separation circuit 445 , the separation circuit 447 and the automatic frequency control circuit 447 , and compares the phase of this signal with the phase of a signal formed by dividing the frequency of the output signal of the voltage controlled oscillator 460 by one third in the frequency divider 461 and further by 1/455 in the frequency divider 463 . In this way, a phase-locked loop is formed for forming a line synchronizing signal, which is synchronized with the frequency-modulated playback video signal. The error signal obtained in this way as a comparison result is compensated for in phase in the control circuit filter 449 as a rule before it is fed to the adder 459 . To this error signal from the control loop filter 449 , the phase error signal is added in the adder 459 , which corresponds to the phase difference between the signal between the synchronous bottom part of the frequency-modulated playback video signal and the signal with the frequency 2 f _SC , which is obtained by dividing the frequency of the Is obtained from the output signal of the voltage-controlled oscillator 460 to a third. The voltage controlled oscillator 460 is controlled with the error signal formed in the adder 459 as the addition result. The addition of the phase-locked loop operating in accordance with the horizontal synchronization signal to the circuit arrangement of the reproducing part is made possible in that the video signal is recorded while observing the condition f _ST (synchronous floor part frequency) = nxf _H (line synchronizing frequency).

After the frequency-modulated playback video signal received at the input terminal 431 has been amplified by the playback amplifier 432 , it is fed to the playback equalizer 433 , in which it undergoes a prescribed correction, after which it is then fed to the bandpass filter 434 , in which unnecessary frequency band components outside the frequency range a according to FIG. 20 are eliminated. The output signal of the bandpass filter 434 is fed to the multiplier 435 . In the multiplier 435 , the video signal is multiplied by a signal which is formed by the output signal of the voltage-controlled oscillator 460 having the frequency 6 f _SC which is obtained in the circuit part L by synchronization with the playback synchronizing bottom part frequency 2 f _SC , is shaped into a sine signal by the bandpass filter 436 . As a result of the multiplication together with other components, a frequency modulated video signal component is obtained, which is shown in FIG. 20 as part or component b . Thereafter, only the frequency-modulated video signal component b of FIG. 20 is removed by the band-pass filter 437 and supplied to the frequency demodulator 438 . The frequency demodulator 438 demodulates the frequency-modulated playback video signal b according to FIG. 20. The demodulated signal is fed to the lowering circuit 439 for post-equalization. The playback video signal subjected to the equalization is then fed to the A / D converter 440 , in which it is converted into digital data which, for example, consist of 8 bits per query. The digital data is written into the memory 441 . In this case, a conversion clock signal with the frequency 6 f _{SC is} used for the D / A conversion, which is generated by the voltage-controlled oscillator 460 in the circuit part L in synchronism with the playback synchronizing bottom part frequency 2 f _SC . This clock signal with the frequency 6 f _SC is also used as a write clock signal for writing into the memory 441 . This design ensures that any time base fluctuations in the playback video signal are canceled when this signal is written into memory 441 .

The content of the memory 441 is read out with a clock signal with the fixed frequency 6 f _SC , which is output from the reference quartz oscillator 443 and is also applied to the D / A converter 442 , which is thus also under the control of the same clock signal is operated with the fixed frequency 6 f _SC . Thereafter, the analog signal generated by the D / A converter 442 is supplied to the output terminal 444 . Due to the above-described Zeitbasiskor rection discharged from the output terminal 444 composite color video signal or composite video signal is of course free of time base fluctuations.

In the sixth embodiment, the conversion carrier signal with the frequency 6 f _{SC is} used for the frequency modulated video signal, but this can be replaced by a conversion carrier signal with the frequency 12 f _SC .

In the case of this modification, an assignment frequency range c according to FIG. 22 results in the modulation or demodulation . The changes in the circuit arrangement required for this modification are as follows:

In the circuit arrangement according to FIG. 19, an inverting amplifier is additionally inserted between the lifting circuit 402 and the frequency modulator 403 . The frequency divider 428 is changed to a division of the frequency of the input signal to 1/6. Furthermore, the filters are changed as required.

In the circuit arrangement according to FIG. 21, an inverting amplifier is additionally inserted between the frequency demodulator 438 and the lowering circuit 439 . The frequency divider 461 is changed to 1/6 to divide the frequency of the input signal while the filters are changed as required.

The function of the modified circuit arrangement is the same that in the sixth embodiment, so that therefore a detailed description is unnecessary.

Furthermore, in the sixth exemplary embodiment, the frequency nf _{SC is selected} for the frequency conversion carrier signal and the frequency mf _SC for the synchronous bottom part. These frequency values can of course be changed to lf _H and pf _H or qfv and hfv , respectively, where f _{H is} the line synchronization frequency of the input signal, fv is the image synchronization frequency of the input signal and n, m, l, p, q and h are positive integers .

In the arrangement of the sixth off described above The baseband components of the Modula are exemplary tion signal and the sideband component of the frequency mod gated video signal very clearly in terms of each other the frequency during the recording separately, so that the derive from the interference between the signals during the Moire appearance resulting in frequency modulation reduced is. During playback, the baseband components of the Playback signals and the sideband component of the demodu gated video signal after the frequency conversion likewise very clearly separated from each other in terms of frequency, so that the interference between  resulting in the signals during frequency demodulation Moire appearance is diminished.

The frequency f _{SC of} the frequency-modulated playback video signal, the frequency conversion carrier frequency and the frequency of the synchronous bottom part of the frequency-modulated video signal are phase locked. Therefore, even if a moire phenomenon results from the interference between these signals, the moire pattern occurs in a fixed image pattern on the screen of a display device or the like when the reproduction signal is imaged thereon. Furthermore, the suppressed moiré is no problem with regard to the visual impression. Since the moiré component then continues to appear in a fixed pattern, it can be suppressed in a simple manner by means of any filter using the correlation of the image signal, such as, for example a comb filter.

The recording part in the first embodiment can be modified in such a way that the carrier frequency signal the synchronous bottom part of the video signal as a reference signal for the time base correction during playback by phases coupling the frequency modulation carrier with a reference clock signal during frequency modulation during recording of the video signal can be used. An example for such a modification is described below:

FIG. 23 is a block diagram of the circuit arrangement of the aforementioned modification of the first embodiment shown in FIG. 1. In FIG. 23, the same components and parts as those shown in FIG. 1 are given the same reference numerals, and a detailed description thereof is omitted. In the circuit arrangement according to FIG. 23, the video signal recorded at an input terminal A is placed on the synchronous bottom part or base part by the clamping circuit 10 at a fixed level. Then the video signal, the Synchronbo d part or base part is set by the clamping circuit 10 to the DC voltage level, the frequency modulator 14 is supplied. The frequency modulator 14 consists of an Addie rer 14 a and a voltage controlled oscillator 14 b . The video signal with the base level determined by the clamping circuit 10 passes through the adder 14 a to the voltage controlled oscillator 14 b . From the voltage-controlled oscillator 14 b , the video signal is frequency modulated in that a signal is generated whose frequency corresponds to the voltage level of the video signal. The frequency-modulated video signal is fed to a terminal D of a switch 464 and also to an input of the phase comparator 24 .

The other input of the phase comparator 24 is supplied with a reference clock signal, for example from the quartz oscillator 26 according to FIG. 1. As a comparison result, the phase comparator 24 emits an error signal which is transmitted via the analog switch 22 , the control loop filter 20 and the adder 14 a the voltage control input of the voltage controlled oscillator 14 b is applied. At the same time, the composite signal separated from the video signal received at the input terminal A is fed to the analog switch 22 via an input terminal B. The analog switch 22 is turned on at the synchronous bottom parts of the line synchronizing signals and the image synchronizing signals, which are contained in the composite synchronizing signal and the compensation pulses.

Therefore, during the time corresponding to a respective synchronous bottom part of the video signal input at the input terminal A , the circuit arrangement described above forms a phase-locked loop through which the frequency of the synchronous bottom part of the frequency-modulated video signal is brought to the same frequency as the above-mentioned reference clock signal at the input terminal C. . Outside of this particular time, the frequency modulator 14 carries out the frequency modulation in a normal manner, with its output signal being applied to one terminal D of the switch 464 .

The other terminal E of the switch 464 , the reference clock signal is supplied from the input terminal C. The switching process of the switch 464 is controlled by the composite synchronization signal supplied via the input terminal B. During the time period corresponding to the synchronous bottom part of the video signal input via the input connection A , the changeover switch 464 is switched to its connection E. Outside of this time, the changeover switch 464 is always switched to the other terminal D. This switching process replaces the synchronous base part of the frequency-modulated video signal with the reference clock signal before it is output at an output terminal F.

Furthermore, when the synchronous bottom part of the signal is replaced by the reference clock signal, the analog switch 22 is actuated during the exchange process in such a way that the output signal of the voltage-controlled oscillator 14 b is phase-coupled to the reference signal. Therefore, before and after the switch 464 is switched from the E terminal to the D terminal, the waveform of the frequency-modulated video signal output from the output terminal F is never disturbed. This circuit arrangement ensures that the reproduction of the waveform of the playback video signal obtained by frequency demodulation remains undistorted during reproduction.

In Fig. 24, a curve shape disturbance within the synchronous bottom part is shown in dashed lines. Such a waveform disturbance results from a phase discrepancy that could occur between the waveforms before and after switching the switch 464 from the D terminal to the E terminal during the recording. FIG. 25 shows the waveform of a playback video signal from the playback shown in FIG. 2 in accordance with the first embodiment. Compared with the curve shape according to FIG. 25, the curve shape disturbance shown in FIG. 24 on the synchronous bottom part is greater (with regard to the level). However, the duration of the disturbance is less. The response delay time when the frequency of the synchronous base part is stabilized is longer than the response delay time of the frequency modulator 14 . Therefore, the curve shape disturbance according to FIG. 24 results in a longer time period between times a and b during which the time base correction can be carried out during reproduction than the curve shape disturbance according to FIG. 25. In fact, the curve shape disturbance occurring over a certain period of time is the effect of a filter attributed, which is not Darge, but is included in the frequency modulator 14 .

Furthermore, although the curve shape disturbance shown in FIG. 24 on the synchronous bottom part in the reproduction part shown in FIG. 2 of the first exemplary embodiment is larger, the time duration is shorter. In addition, the location of the occurrence of the fault remains unchanged. Therefore, the curve shape disturbance can be suppressed in a simple manner, for example, by replacing this part of the curve by any other suitable signal or by setting a level.

FIG. 26 shows an example of the circuit arrangement for suppressing the waveform distortion of the synchronous bottom part of the playback video signal shown in FIG. 24. In Fig. 26, the same components and parts as those shown in Fig. 2 are given the same reference numerals, and a detailed description of these components and parts is omitted. FIG. 26 shows the frequency demodulator 106 , the line synchronization signal separating circuit 122 , an OR gate 645 , a first and a second pulse generator 646 and 647 , a clamping pulse generator 648 , a clamping circuit 649 , a reference voltage Vo and an interrogation / hold circuit 650 .

The arriving at an input terminal G frequency modulated playback video signal is first demodulated by the frequency de modulator 106 . The waveform of a demodulated signal a thus obtained is shown on a part (a) of FIG. 27. A black part of the curve shape (a) represents the curve shape disturbance described above, which occurs on the synchronous base part. A line synchronization signal b is separated from the demodulated signal a by the separation circuit 122 . The waveform of the line synchronizing signal b is shown on a part (b) of FIG. 27. As shown, there is a dropout in the line sync signal. The first pulse generator 646 is triggered by the rising edge of the line synchronization signal applied to it. As a result, the pulse generator 646 generates a pulse with a predetermined width as shown in FIG. 27. The triggering of the first pulse generator 646 does not take place again after the start of the generation of the pulse until its end. The curve shape of such an output pulse c of the first pulse generator 646 is shown in part (c) of FIG. 27 Darge.

The OR gate 645 , the line synchronization signal b is supplied. The OR gate 645 outputs an output pulse d , the waveform of which is shown on a part (d) of FIG. 27. As shown, the signal drop of the line synchronizing signal b is corrected in the pulse d having the same width as the line synchronizing signal b . The output pulse d of the OR gate 645 is supplied to the clamp pulse generator 648 , thereby supplying the clamp circuit 649 with a signal e , the waveform of which is shown on part (e) of FIG. 27 and which forms a clamp pulse signal. In response to this, the clamp circuit 649 sets the output signal a of the frequency demodulator 106 to the reference voltage Vo to thereby set a base part immediately after the color synchronizing signal or burst part.

The second pulse generator 647 receives the pulse d and forms therefrom a signal f , the curve shape of which is shown on part (f) of FIG. 27. The signal f is fed to the query / hold circuit 650 as a query / hold pulse signal. From the request / hold circuit 650 , only the part at which the signal f has the high level is picked up and held from a playback video signal g from the clamping circuit 649 . As a result, an output signal h of the interrogation / hold circuit 650 becomes a video signal which, as shown on part (h) of FIG. 27, has no curve shape disturbance on the synchronous bottom part.

In the circuit arrangement according to FIG. 26, the query / hold circuit 650 is connected downstream of the clamping circuit 649 . However, this arrangement can be changed so that the query / hold circuit 650 is switched before the clamp circuit 649 ge. Furthermore, the circuit arrangement of the interrogation / hold circuit 650 of FIG. 26 can be changed in the manner shown in FIG. 28. In the arrangement according to FIG. 28, the query / hold circuit consists of a switch S 1 and a reference voltage Vo ' . If one assumes that the voltage level of the reference voltage Vo according to FIG. 26 represents the base level of the video signal, then the reference voltage Vo ′ according to FIG. 28 gives the voltage level for the synchronous base part. Therefore effected in the arrangement of Fig. 28, the signal d in that each synchronous base part of the input signal g is replaced by the reference voltage Vo 'before the signal g is output as a signal h.

In the embodiment described above, the Synchronous floor part used as a synchronizing signal part. Regarding the usable synchronization signal part exists however no restriction to the synchronous bottom part, much the front part or the rear part can do more edge of each synchronizing signal part.

The embodiment is designed such that the Recording a curve shape disturbance on the frequency modulator th video signal is prevented by the synchronous bo part of the video signal is replaced by a reference signal, when the video signal is frequency modulated. When again gift is not only one in the embodiment correction of time base fluctuations on the playback Video signal, but also suppressing voltage pe gel fluctuations on the synchronous bottom part of the video signal after the correction of the time base fluctuations.

In the exemplary embodiment shown in FIG. 4, the clock signals for writing into the memory and reading out from the memory are compared with one another in order to prevent the write and read addresses of the memory from overlapping with one another. The circuit arrangement according to FIG. 4 can, however, be changed to that shown in FIG. 29. In the circuit arrangement according to FIG. 29, the counter values of address counters are compared with one another, which in each case determine the write address or the read address of the memory. In Fig. 29, the same components and parts as those shown in Fig. 4 are denoted by the same reference numerals, while a detailed description of these components and parts is omitted below.

Of FIG. 29 is a reproduction video signal is time base with the A / D converter 110 supplied to fluctuations. The converter 110 converts the input signal into digital video data, for example, from 8 bits. The data thus obtained are written into the image memory 112 . In the meantime, only a color synchronization signal switching element 651 picks out from the playback video signal its color synchronization signal and supplies this burst signal to a phase comparator 652 . In the phase comparator 652 , the phase of the picked-out color synchronization signal is compared with the phase of the output signal of a voltage-controlled oscillator 653 , which oscillates on the color subcarrier frequency f _SC . As a comparison result, the phase comparator 652 outputs an error signal. The oscillation frequency of the voltage-controlled oscillator 653 is controlled in accordance with the error signal. As a result, the oscillation of the voltage-controlled oscillator 653 follows the color synchronization signal, which is subject to the time base fluctuations, in order to generate a clock signal in synchronism with the time base fluctuations.

This clock signal from the voltage-controlled oscillator 653 is stepped up by means of a multiplier 654 and raised n times, where n is a positive integer. The up-switched clock signal is supplied to the A / D converter 110 and a write address counter 655 for the image memory 112 . The digital video data is thus written into the image memory 112 successively at write addresses determined by the write address counter 650 according to the clock signal which follows the time base fluctuations. The count value of the write address counter 655 returns to the initial address value after reaching a value corresponding to the upper limit address of the image memory 112 .

Meanwhile, a voltage controlled quartz oscillator 656 generates another clock signal for reading from the image memory 112 . The voltage controlled crystal oscillator 656 oscillates at a frequency mf _SC (with a positive integer, different from n, m ), which is different from the clock signal from the n multiplier 654 , and is controlled by a phase comparator 658 as described below. The clock signal from the voltage-controlled quartz oscillator 656 is fed to a read address counter 657 and the D / A converter 114 . In accordance with the read clock signal, the video data stored or written into the image memory 112 are read out and supplied to the D / A converter 114 . The D / A converter 114 then outputs from its output connection the video signal on which the time base fluctuations have been eliminated or corrected.

The oscillation frequency of the voltage-controlled quartz oscillator 656 in this exemplary embodiment is controlled as follows:

The phase comparator 658, a count value N 1 of the write address counter 655 and a further count value N 2 are supplied from the read address counter 658th The two count values N 1 and N 2 are positive integer data that determine the addresses of the image memory 112 .

The phase comparator 658 compares these input signals and outputs a signal that corresponds to an address deviation or an address error. The address error signal is applied to the voltage controlled crystal oscillator 656 for generating the read clock signal. As a result, the voltage-controlled quartz oscillator 656 generates a signal whose frequency is controlled by the error signal. To a sol chen stabilization of the output signal of the voltage sensors, controlled crystal oscillator 656, a tunable oscillator is used with a quartz oscillator as the oscillator 656th

Furthermore, the read clock signal generated by the voltage controlled crystal oscillator 656 need not necessarily have a predetermined phase relationship to the write clock signal. The control of the read clock signal is only necessary to easily prevent the read address from overlapping with the write address. By thus controlling the voltage controlled crystal oscillator 656 , the count values N 1 and N 2 of the address counters 655 and 657 are kept different from each other, while the time base fluctuations of the reproduction video signal are sufficiently corrected by stabilizing the writing and reading operations on the image memory can.

An information signal recording / reproducing device contains a recording part and a reproducing part. With the Recording part is on a recording material Information signal after its angular modulation in such a way records that a a period of the angle-modulated Information signal corresponding signal in a given is brought into connection with a reference signal. The Playback part is designed so that the angle-modulated Information signal is demodulated when it from the on drawing material is removed, and according to the Signal part of the angle-modulated information signal Time base correction is made. This allows them to time base fluctuations occurring during playback exactly balanced by the circuit arrangement who the without the information signal during recording any special signal is added.

Claims (55)

1. An apparatus for recording information signals on a recording material, characterized by a modulator ( 14 ) which modulates an input information signal to a win kelmodulated information signal, a correction device which compares a signal signal corresponding to a time period of the winkelmodiert th with a reference signal and the angle-modulated information signal corrected in accordance with the comparison result, and a recording device ( 18 , 38 ) which records the corrected angle-modulated information signal on the recording material ( 9 ). 2. Apparatus according to claim 1, characterized in that the information to be recorded on the recording material ( 9 ) information signal is a video signal. 3. Apparatus according to claim 2, characterized in that the correction means a reference signal generator ( 26 ; 44 ; 70 , 72 ) for generating the reference signal, a phase comparator ( 24 ) which compares the phase of the angle-modulated video signal with the phase of the reference signal and one Ver comparison result outputs corresponding phase error signal, a synchronization signal separating device ( 28 , 30 ), which separates a synchronizing signal contained therein from the recorded video signal, and a phase error signal feed device ( 22 , 34 ) which, in accordance with the separated synchronizing signal, the phase error signal to the modulator ( 14 ) during a period of time during which the synchronizing signal of the video signal is supplied to the modulator. 4. Apparatus according to claim 3, characterized in that the modulator ( 14 ) executes the angular modulation of the recorded video signal in accordance with the phase error signal from the phase error signal feed device ( 22 , 34 ) such that the phase of the synchronization signal part of the angle-modulated video signal is phase-locked with the Phase of the reference signal is coupled. 5. Apparatus according to claim 3 or 4, characterized in that the signal emitted by the reference signal generator ( 26 ; 44 ; 70 , 72 ) is a signal having a frequency which is an integer multiple of the frequency of a line synchronization signal of the video signal. 6. Apparatus according to claim 3 or 4, characterized in that the reference signal generated by the reference signal generator ( 26 ; 44 ; 70 , 72 ) is a signal with a frequency which is an integer multiple of a color subcarrier frequency of the video signal. 7. Device according to one of claims 3 to 6, characterized in that the correction device has a reference signal phase control device ( 40 to 46 ), the phase of the synchronizing signal separating means ( 28 , 30 ) separated synchronizing signal with the phase of loading train signal compares and controls the phase of the reference signal accordingly the comparison result. 8. Device according to one of claims 3 to 6, characterized in that the correction device a Farbsynchroni siersignal-Abtrenneinrichtung ( 50 , 58 ) for separating a color synchronization signal from the video signal corresponding to the synchronizing signal by means of the synchronizing signal separating device ( 28 , 30 ) and a reference signal phase control device ( 52 to 70 ) which compares the phase of the separated color synchronization signal with the phase of the reference signal and which controls the phase of the reference signal accordingly to the phase comparison result. 9. Apparatus according to claim 8, characterized in that the correction device comprises a first phase comparator ( 54 ) which compares the phase of the separated color synchronization signal with the phase of the reference signal and outputs a first phase error signal corresponding to the phase comparison result, a second phase comparator ( 74 ), which compares the phase of the separated synchronizing signal with the phase of the reference signal and emits a second phase error signal corresponding to the phase comparison result and has a reference signal phase control device ( 80 ) which controls the phase of the reference signal in accordance with the first and second phase error signals. 10. Device according to one of claims 1 to 9, characterized in that the modulator ( 14 ) is a frequency modulator which outputs the recorded information signal as a frequency-modulated information signal. 11. Device for reproducing a recorded on a recording material information signal, characterized by a playback device ( 38 , 102 ) for the acceptance of a modulated information signal, which was modulated at a time section to a predetermined frequency, from the recording material ( 9 ), a demodulator ( 106 ) for demodulating the modulated information signal into a demodulated information signal and a time base correction device for correcting the time base of the demodulated information signal in accordance with the time period of the modulated information signal. 12. Apparatus according to claim 11, characterized in that the information signal removed from the recording material ( 9 ) is a video signal. 13. Apparatus according to claim 12, characterized in that the playback device ( 38 , 102 ) from the recording material ( 9 ) decreases a frequency-modulated video signal with a frequency modulation in which a synchronizing signal section of the video signal has a predetermined frequency. 14. Apparatus according to claim 13, characterized in that the demodulator ( 106 ) is a frequency demodulator which demodulates the frequency-modulated video signal to a demodulated video signal. 15. Apparatus according to claim 13 or 14, characterized in that the time base correction means, a memory ( 112; 113 ) for storing the video signal from the frequency demodulator ( 106 ), a write clock signal generator ( 142 ) for generating a write clock signal ( WRCLK ), the on the memory determines the write-in time when the video signal is written from the frequency demodulator into the memory, a synchronizing signal separating device ( 120 , 122 ) for separating a synchronizing signal from the video signal from the frequency demodulator, a pull-out device ( 128 ) for picking out a synchronizing signal Signal part from the frequency-modulated video signal corresponding to the synchronized signal separated by means of the synchronization signal separating device, a write clock signal phase control device ( 134 to 144 ) which compares the phase of the signal part with the phase of the write clock signal and in accordance with the comparison result controls the phase of the write clock signal, and a read clock signal generator ( 16 ; 174 ; 184 ), which generates a read clock signal ( RDCLK ) which determines the read time when the video signal is read out from the memory. 16. Apparatus according to claim 15, characterized in that the time base correction means, a second synchronizing signal separating device ( 164 , 166 ) for separating a synchronizing signal from the video signal read out from the memory ( 112 ), a color synchronizing signal separating device ( 158 , 168 ) Separating a color synchronization signal from the video signal read out from the memory in accordance with the synchronization signal separated by means of the second synchronization signal separating device, a reference signal generator ( 146 ) for generating a reference signal and a read clock signal control device ( 170 ) having the phase of the separated color synchronization signal compares the phase of the reference signal and controls the phase of the read clock signal ( RDCLK ) accordingly ( FIG. 3). 17. The apparatus of claim 16, characterized in that the time base correction means a normal reading clock signal generator ( 116 ) which generates a normal reading clock signal which determines a normal reading time when reading the video signal from the memory ( 112 ; 113 ), and a Aufschalteinrich device ( 162 ) which detects the presence or absence of a color synchronization signal in the video signal output from the memory and, in the absence of this color synchronization signal, supplies the memory with the normal read clock signal. That the time base corrector, a read clock signal Phasenre gel means 18. A device according to claim 15, characterized in that (180 to 184) that compares the phase of the write clock signal (WRCLK) generated by the write clock signal generator (142) with the phase of the read clock signal and corresponding to the Comparison result controls the phase of the read clock signal ( Fig. 4). 19. Apparatus according to claim 18, characterized in that the memory is a line memory ( 113 ). 20. Apparatus according to claim 12, characterized in that the playback device ( 38 , 102 ) from a disc-shaped recording material ( 9 ) receives a frequency-modulated video signal which is frequency-modulated in such a way that a synchronizing signal part thereof has a predetermined frequency. 21. Apparatus according to claim 20, characterized in that the demodulator ( 106 ) is a frequency demodulator which demodulates the frequency-modulated video signal from the playback device ( 38 , 102 ) to a video signal for delivery. 22. Apparatus according to claim 16 and 21, characterized in that the time base correction device comprises a second phase comparator ( 190 ) which compares the phase of the synchronizing signal separated by means of the second synchronizing signal separating device ( 164 , 166 ) with the phase of the reference signal to generate a second phase error signal and having a read clock signal phase controller ( 194 ) which controls the phase of the read clock signal ( RDCLK ) in accordance with the first and second phase error signals ( Fig. 7). 23. The apparatus of claim 22, characterized in that the time base correction means a normal reading clock signal generator ( 116 ) which generates a normal reading clock signal which determines a normal reading time when reading the video signal from the memory ( 112 ; 113 ), and a Aufschalteinrich device ( 162 ) which detects the presence or absence of a color synchronization signal in the video signal output from the memory and, in the absence of this color synchronization signal, supplies the memory with the normal read clock signal. 24. Apparatus according to claim 22 or 23, characterized in that the playback device ( 38 , 102 ) has a rotary drive device ( 29 , 31 ) for the rotary drive of the disk-shaped recording material ( 9 ) with synchronization with the reference signal generated by the reference signal generator ( 146 ) points. 25. Apparatus according to claim 14, characterized in that the time correction device has a memory ( 112 ; 113 ) for storing the video signal from the frequency demodulator ( 106 ), a write clock signal generator ( 142 ) for generating a write clock signal ( WRCLK ) which the storage time at Storing the video signal in the memory determined, a line synchronization signal separating device ( 120 , 122 ) for picking out a line synchronization signal from the video signal from the frequency demodulator, a pull-out device ( 124 , 128 ) for pulling out the line synchronization signal in the frequency-modulated video signal from the playback device Corresponding signal part according to the line synchronization signal picked out by means of the line synchronization signal separating device, a first phase comparator ( 134 ) which compares the phase of the signal part with the phase of the write clock signal to deliver a first phase error signal, a two iten phase comparator ( 200 ), which compares the phase of the extracted line synchronization signal with the phase of the write clock signal to output a second phase error signal, a write clock signal phase control device ( 204 ) which controls the phase of the write clock signal according to the first and the second phase error signal, and one Read clock signal generator ( 116 ; 174 ; 184 ) which generates a read clock signal ( RDCLK ) which determines the time when the video signal is read out from the memory ( FIG. 9). 26. The apparatus of claim 25, characterized in that the time base correction means a synchronizing signal from separating means ( 164 , 166 ) for separating a synchronizing signal from the read out from the memory ( 112 ) video signal, a color synchronizing signal separating means ( 158 , 168 ) for Disconnecting a color synchronizing signal of the video signal from the memory in accordance with the synchronizing signal separated from the synchronizing signal separating means, a reference signal generator ( 146 ) for generating a reference signal and a read clock signal phase control device ( 170 ) having the phase of the color synchronizing signal with the phase of Reference signal compares and controls the phase of the read clock signal ( RDCLK ) according to the comparison result ( FIG. 10). 27. The apparatus of claim 26, characterized in that the time base correction means a normal reading clock signal generator ( 116 ) which generates a normal reading clock signal which determines a normal reading time when reading the video signal from the memory ( 112 ; 113 ), and a Aufschalteinrich device ( 162 ) which detects the presence or absence of a color synchronization signal in the video signal output from the memory and, in the absence of this color synchronization signal, supplies the memory with the normal read clock signal. 28. Apparatus according to claim 25, characterized in that the time base correction device comprises a read clock signal phase control device ( 180 to 184 ) which compares the phase of the write clock signal ( WRCLK ) with the phase of the read clock signal ( RDCLK ) and the phase of the read clock signal in accordance with the comparison result controls ( Fig. 11). 29. Apparatus according to claim 28, characterized in that the memory ( 113 ) contains a line memory. 30. Apparatus according to claim 26, characterized in that the time base correction device comprises a first phase comparator ( 170 ) which compares the phase of the color synchronization signal of the video signal with the phase of the reference signal in order to generate a first phase error signal, a second phase comparator ( 190 ), which compares the phase of the synchronizing signal separated by means of the synchronizing signal separating device ( 164 , 166 ) with the phase of the reference signal to generate a second phase error signal, and has a reading clock signal phase control device ( 194 ) which corresponds to the first and the second phase error signal controls the phase of the read clock signal ( RDCLK ) ( Fig. 12). 31. The apparatus of claim 30, characterized in that the time base correction means a normal read clock signal generator ( 116 ) which generates a normal read clock signal which determines a normal read time when reading the video signal from the memory ( 112 ; 113 ), and a Aufschalteinrich device ( 162 ) which detects the presence or absence of a color synchronization signal in the video signal output from the memory and, in the absence of this color synchronization signal, supplies the memory with the normal read clock signal. 32. Device according to one of claims 25 to 31, characterized in that the playback device ( 38 , 102 ) has a rotary drive device ( 29 , 31 ) for the rotary drive of the disk-shaped recording material ( 9 ) with synchronization with that of the reference signal generator ( 146 ) generated reference signal. 33. Apparatus for recording information signals on a recording material, characterized by a modulator ( 14 ) which modulates the received information signal into an angle-modulated information signal, a reference frequency signal generator ( 301 ; 310 ) for generating a reference frequency signal, an exchange device for replacing one Time period of the angle-modulated video signal by the reference frequency signal and a recording device ( 18 , 38 ) for recording the angle-modulated information signal, in which the signal corresponding to the time period is replaced by the reference frequency signal, on the recording material ( 9 ). 34. Apparatus according to claim 33, characterized in that the information signal to be recorded on the recording material ( 9 ) tion signal is a video signal. 35. Apparatus according to claim 33 or 34, characterized in that the exchange device has a synchronizing signal separating device ( 28 , 30 ) which separates a synchronizing signal contained therein from the recorded video signal, and has a switching device ( 300 , 302 ), which receives the angle-modulated video signal from the modulator ( 14 ) and the reference frequency signal from the reference frequency signal generator ( 301 ) and outputs the reference frequency signal in accordance with the synchronizing signal during the period of supply of the synchronizing signal of the video signal to the modulator ( FIG. 17). 36. Apparatus according to claim 33 or 34, characterized in that the exchange device comprises a synchronization signal separating device ( 28 , 30 ) for separating a synchronization signal contained in the video signal from the received video signal, a signal curve condition monitoring device ( 304 to 307 ), the corresponding to the separated synchronizing signal monitors the waveform state of the angle-modulated video signal output by the modulator ( 14 ) in order to emit a detection signal upon detection of a predetermined waveform state, and has a switching device ( 303 ) which has the angle-modulated video signal from the modulator and that Reference frequency signal receives from the reference frequency signal generator and emits the reference frequency signal for a predetermined period after the emission of the detection signal from the detection device ( FIG. 18). 37. Apparatus according to claim 35 or 36, characterized in that the signal emitted by the reference signal generator ( 301 ; 310 ) is a signal with a frequency which is an integer multiple of the frequency of a line synchronization signal of the video signal. 38. Apparatus according to claim 35 or 36, characterized in that the reference signal emitted by the reference signal generator ( 301 ; 310 ) is a signal with a frequency which is an integer multiple of a color subcarrier frequency of the video signal. 39. Apparatus according to one of claims 33 to 38, characterized in that the correction device has a reference signal phase control device ( 40 to 46 ) which detects the phase of the synchronizing signal separated by means of the synchronizing signal separating device ( 28 , 30 ) with the phase of the loading train signal compares and controls the phase of the reference signal accordingly the comparison result. 40. Apparatus for reproducing information signals recorded on a recording material, characterized by a reproducing device ( 38 , 102 ) for accepting a modulated information signal with a special time period replaced by a predetermined frequency signal from the recording material ( 9 ), a demodulator for demodulating the removed information signal to a demodulated information signal and a time base correction device for correcting the time base of the demodulated information signal in accordance with the particular time period of the modulated information signal. 41. Device for recording video signals on a recording material, characterized by an angle modulator ( 403 ) which modulates the recorded video signal to an angle-modulated video signal in a frequency band which is higher than a desired frequency band, a control device ( K ) a frequency converter ( 405 to 408 ) for controlling the modulator in such a way that the phase of a part of the angle-modulated video signal from the modulator corresponding to a synchronization signal corresponds to the phase of a first signal related to the video signal in accordance with a second signal related to the video signal, the frequency modulated video signal from the modulator into the target frequency band, and recording means ( 413 ) for recording the angle modulated video signal subjected to frequency conversion into the target frequency band on the recording material l ( Fig. 19). 42. Apparatus according to claim 41, characterized in that the control device ( K ) a Synchronisiersignal-Abtrennein direction ( 415 , 416 ), which separates the synchronizing signal from the recorded video signal, a color synchronizing signal separating device ( 419 , 420 ), which consists of the recorded video signal in accordance with the separated synchronization signal, a color synchronization signal, a reference signal generator ( 427 ) for generating a reference signal, a reference signal phase control device ( 422 to 430 ) which compares the phase of the extracted color synchronization signal with the phase of the reference signal and the phase of the reference signal controls in accordance with the comparison result, a phase comparator ( 410 ) which compares the phase of the angle-modulated video signal shifted into the desired frequency band by the frequency converter ( 405 to 408 ) with the phase of the reference signal in order to obtain a phase error signal corresponding to the phase comparison result generate, and a Pha senfehlersignalzuführeinrichtung ( 411 , 418 ), which according to the separated synchronizing signal to the modulator gate supplies the phase error signal during the time during which the synchronizing signal of the video signal is supplied to the modulator ( Fig. 19). 43. Apparatus according to claim 42, characterized in that the frequency converter ( 405 to 408 ) converts the angle-modulated video signal obtained from the modulator ( 403 ) with respect to the frequency corresponding to the reference signal generated by the reference signal generator ( 427 ). 44. Apparatus according to claim 42 or 43, characterized in that the angle modulator ( 403 ) modulates the recorded video signal in accordance with the phase error signal feed device ( 411 , 418 ) supplied in such a way that the phase of the synchronization signal part of the angle-modulated video signal with the phase the reference signal generated by the reference signal generator ( 427 ) is coupled. 45. Device according to one of claims 42 to 44, characterized in that the signal emitted by the reference signal generator ( 427 ) is a signal having a frequency which is an integer multiple of the frequency of a line synchronization signal of the video signal. 46. Apparatus according to any one of claims 42 to 44, characterized in that the reference signal generated by the reference signal generator ( 427 ) is a signal having a frequency which is an integer multiple of a color subcarrier frequency of the video signal. 47. Apparatus according to claim 43, characterized in that the angle modulator ( 403 ) contains a frequency modulator which modulates the recorded video signal into a frequency-modulated video signal. 48. Apparatus for reproducing video signals recorded on a recording material, characterized by a reproducing device ( 432 ) for taking an angle-modulated video signal from the recording material, a frequency converter ( 434 to 437 ) which corresponds to a first signal related to the angle-modulated video signal converts the angle-modulated video signal into a frequency band that is higher than a target frequency band, a frequency demodulator ( 438 ) that demodulates the frequency-converted angle-modulated video signal to the target frequency band in order to recover the video signal, and a time base correction device that Corrected time base of the recovered video signal corresponding to a part of the acquired angle-modulated video signal, which speaks to a synchronizing signal of the video signal ( FIG. 21). 49. Apparatus according to claim 48, characterized in that the time base correction means, a memory means ( 440 to 442 ) for storing the video signal from the frequency demo dulator ( 438 ), a write clock signal generator ( 460 ) for generating a write clock signal which write the time when the Determines video signal from the frequency demodulator in the storage device, a synchronizing signal from separating device ( 445 , 446 ) which separates a synchronizing signal from the video signal from the frequency demodulator, a pull-out device ( 450 , 452 ) which picks out a signal part in accordance with the separated synchronizing signal corresponds to the synchronization signal of the angle-modulated video signal from the playback device ( 432 ), a first phase comparator ( 455 ) which compares the phase of the selected signal part with the phase of the write clock signal from the write clock signal generator to generate a first phase error signal, a second phase comparator ( 448 ) which compares the phase of the separated synchronizing signal with the phase of the write clock signal from the write clock signal generator to generate a second phase error signal, a write clock signal phase controller ( 459 ) corresponding to the first and second Phase error signal controls the phase of the write clock signal and has a read clock signal generator ( 443 ) which generates a read clock signal which determines the time when the video signal is read out from the memory device ( FIG. 21). 50. Apparatus according to claim 49, characterized in that the frequency converter ( 434 to 437 ) converts the angle-modulated video signal from the playback device ( 432 ) with respect to the frequency corresponding to the write clock signal generated by the write clock signal generator ( 460 ). 51. Apparatus for recording video signals on a recording material, characterized by a reference signal generator ( C ) for generating a reference signal, an angle modulator ( 14 ) which modulates the recorded video signal with phase coupling with the reference signal to form an angle-modulated video signal Exchange device ( 464 ), which sets a signal part of the angle-modulated video signal which corresponds to a synchronization signal by the reference signal, and a recording device ( F ) which records the angle-modulated video signal on the recording material, in which the signal part corresponding to the synchronization signal by the reference signal is replaced ( Fig. 23). 52. Apparatus according to claim 51, characterized in that the angle modulator ( 14 ) contains a frequency modulator. 53. Apparatus for reproducing video signals recorded on a recording material, characterized by a playback device ( G ) which takes an angle-modulated video signal from the recording material in which a part corresponding to a synchronization signal is replaced by a signal of a predetermined frequency, an angle demodulator ( 106 ), which demodulates the angle-modulated video signal, a time base correction device ( 645 to 648 , 650 ) which corrects the time base of the demodulated video signal in accordance with the part of the angle-modulated video signal corresponding to the synchronization signal, and a voltage level correction device ( 649 ) which a level-bottom part of the synchronizing signal of the the time base corrected demodulated video signal corrected to a predetermined voltage level ( Fig. 26). 54. Apparatus according to claim 53, characterized in that the voltage level correction device ( 649 ) has a clamping circuit. 55. Apparatus for reproducing information signals recorded on a recording material, characterized by a reproducing device which takes from the recording material a modulated information signal which is modulated at certain periodic sections to a predetermined frequency, a demodulator for demodulating the modulated information signal, a storage device ( 110 to 114 ) for storing the demodulated information signal, a write address command device ( 651 to 655 ), which generates synchronously with the special periodic sections of the modulated information signal serial write address signals for determining write addresses of the memory device for writing the demodulated information signal, a read synchronization signal generator ( 656 ) for generating a read synchronization signal for reading out from the storage device, a read address command device ( 652 ) which is synchronous with the read syn Chronizing signal serial read address signals for determining read addresses of the storage device, from which the stored demodulated information signal is to be read out, and a control device ( 658 ), which receives and compares the serially generated write address signals and the serially generated read address signals, and which controls the read synchronizing signal generator in this way that the determination of the same address of the memory device by the write address signal and the read address signal is prevented ( Fig. 29).