JPS5573981A - Memory control circuit - Google Patents

Memory control circuit

Info

Publication number
JPS5573981A
JPS5573981A JP14633578A JP14633578A JPS5573981A JP S5573981 A JPS5573981 A JP S5573981A JP 14633578 A JP14633578 A JP 14633578A JP 14633578 A JP14633578 A JP 14633578A JP S5573981 A JPS5573981 A JP S5573981A
Authority
JP
Japan
Prior art keywords
supplied
signal
read
write
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14633578A
Other languages
Japanese (ja)
Other versions
JPS6144333B2 (en
Inventor
Kentaro Odaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP14633578A priority Critical patent/JPS5573981A/en
Publication of JPS5573981A publication Critical patent/JPS5573981A/en
Publication of JPS6144333B2 publication Critical patent/JPS6144333B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

PURPOSE:To perform write and read asynchronously with a simple circut constitution by detecting phase difference between write CP and read CP different in frequency on a basis of the lower-frequency one and inverting the phase of control pulses of a RAM by the detection output. CONSTITUTION:RC of read CP of period tR and 2WC twice as high as WC of write CP of period tW (tW>tR, for example, tW=1.2tR) are supplied to AND gate 11 to form phase detection pulse P10. This pulse P10 becomes high-level tW/4 before the reference timing of rise of WC, and a R/W signal has the phase inverted when the time of RC ''1'' is not overlapped for P10. Break of the R/W signal is used as a clock to operate FF13, and output Q1 of FF13 is supplied to FF14, and output Q2 of FF14 and RC are supplied to exclusive OR gate 16, thus generating the R/W signal.
JP14633578A 1978-11-27 1978-11-27 Memory control circuit Granted JPS5573981A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14633578A JPS5573981A (en) 1978-11-27 1978-11-27 Memory control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14633578A JPS5573981A (en) 1978-11-27 1978-11-27 Memory control circuit

Publications (2)

Publication Number Publication Date
JPS5573981A true JPS5573981A (en) 1980-06-04
JPS6144333B2 JPS6144333B2 (en) 1986-10-02

Family

ID=15405353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14633578A Granted JPS5573981A (en) 1978-11-27 1978-11-27 Memory control circuit

Country Status (1)

Country Link
JP (1) JPS5573981A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61243527A (en) * 1985-04-19 1986-10-29 Nec Corp Bit buffer circuit
JPH02182662A (en) * 1988-11-28 1990-07-17 Xerox Corp Batch shift loader/deliverer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61243527A (en) * 1985-04-19 1986-10-29 Nec Corp Bit buffer circuit
JPH02182662A (en) * 1988-11-28 1990-07-17 Xerox Corp Batch shift loader/deliverer

Also Published As

Publication number Publication date
JPS6144333B2 (en) 1986-10-02

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