JPS5517855A - Electrnic computer - Google Patents
Electrnic computerInfo
- Publication number
- JPS5517855A JPS5517855A JP8973378A JP8973378A JPS5517855A JP S5517855 A JPS5517855 A JP S5517855A JP 8973378 A JP8973378 A JP 8973378A JP 8973378 A JP8973378 A JP 8973378A JP S5517855 A JPS5517855 A JP S5517855A
- Authority
- JP
- Japan
- Prior art keywords
- register
- cpu4
- oscillator
- electrnic
- computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To perform efficiently the control dependent upon a CPU to shorten the whole of the operation time by providing an oscillator which refreshes a data register. CONSTITUTION:Main memory unit 1, dynamic memory register 2 and CPU4 are provided, and register 2 is controlled by clock signals from CPU4. Then, oscillator 7 which refreshes data of register 2 is used to supply the output of oscillator 7 to register 2 when it is unnecesary that register 2 is synchronized with clock signals from CPU4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53089733A JPS6048078B2 (en) | 1978-07-21 | 1978-07-21 | Electronic computer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53089733A JPS6048078B2 (en) | 1978-07-21 | 1978-07-21 | Electronic computer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5517855A true JPS5517855A (en) | 1980-02-07 |
JPS6048078B2 JPS6048078B2 (en) | 1985-10-25 |
Family
ID=13978956
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53089733A Expired JPS6048078B2 (en) | 1978-07-21 | 1978-07-21 | Electronic computer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6048078B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5968893A (en) * | 1982-10-13 | 1984-04-18 | Fujitsu Ltd | Memory control system |
-
1978
- 1978-07-21 JP JP53089733A patent/JPS6048078B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5968893A (en) * | 1982-10-13 | 1984-04-18 | Fujitsu Ltd | Memory control system |
Also Published As
Publication number | Publication date |
---|---|
JPS6048078B2 (en) | 1985-10-25 |
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