JPS5968893A - Memory control system - Google Patents

Abstract

PURPOSE:To attain high speed readout and write even with a slow response speed memory by attaining refresh operation only during the pause period, in a memory control system consisting of an access period to a dynamic memory accessed at random and a pause period. CONSTITUTION:A refresh gate circuit F outputs the signal of an H level by receiving a carry signal outputted from a video counter C, and when a count value of the incorporated counter reaches a prescribed value, a signal of an L level is outputted. The refresh control circuit H receives this L level signal, outputs a refresh signal and a memory M receives the refresh operation during each refresh signal period. The information readout and print from the memory M are attained during the video gate signal output period, and since no refresh operation to the memory M is inserted and only the readout from the memory M is executed to increase the number of readout operator during the gate signal output period and to attain the high speed print.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to a memory control system, and particularly to a memory control system that requires a refresh operation.

(B) Background of the Technology Various types of memories are used to store display information and recorded information in display devices, printing devices, and other various devices.

These memories are broadly divided into study memory and dynamic memory. Dynamic memory is widely used because it is cheap and consumes little power, but it requires refresh operations at regular intervals to retain stored information. There is a need.

Therefore, this refresh operation is required in addition to the operation of reading information stored in the memory or storing information in the memory, and as information is processed at high speed, a high speed response of the memory is also required.

(Q) Prior Art and Problems FIG. 1 is a time chart of printing operations in a conventional printing apparatus, and shows the case where printing is performed on printing paper.

Periods T1 to Tn#Tn+1 are periods in which data is read from the memory and printing is performed, and TFi to TFm are memory refresh periods TP is a rest period.

During the period T1 to Tn l Tn+:L, data is read from the memory, and printing is performed on paper K by a printing device (not shown) based on this read data.

By the way, as the printing speed becomes faster, the interval between the data read periods T1 to Tn becomes narrower (the interval between the data reading periods T1 to Tn becomes narrower).
Fm becomes shorter. ) Refresh T, B, l~TF
If an additional period of m is added between these read periods T1 to Tn, the read and refresh operations cannot be performed unless the response speed of the memory is high.

Therefore, in the case of high-speed printing, high-speed responsiveness is required of the memory, which has the drawback of making the memory expensive.

(I)) Object of the Invention The present invention has been made in view of the above points, and an object of the present invention is to provide a memory control method that can handle high-speed reading and pledge operations even for a memory with a slow response speed.

According to the present invention, in a memory control system in which an access period for a randomly accessed dynamic memory and an idle period are provided, the refresh operation is performed only during the idle period. 4) (F) Embodiments of the Invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a configuration diagram of an embodiment of the present invention, where N is an arithmetic circuit that determines the video gate range, 1 is a scanning synchronization signal generation circuit, C is a video counter, G is a video game 1 circuit, and F
1 is a refresh gate circuit, H is a refresh control circuit, and M is a memory in which information is stored.

Scanning synchronizing signals 81 to 84 shown in FIG. 3(a) are output from the scanning synchronizing signal generating circuit and input to the video counter C and the video gate circuit G.

Video counter C receives scanning synchronization signals S, ~S, starts counting operation 1, and after a certain period of time, carries signal all
~S'+3 is output (Fig. 3(b)).

On the other hand, when the video gate circuit G receives the scanning synchronization signal, it becomes H.
(High) level signal is output, and upon receiving the carry signal output from the video color/receiver C, an L (Low) level signal is output (see FIG. 3(C)).

This period TII+ T12+ TIs ・・・・・・
Information is read out from the memo IJM and printed on paper as described above.

The refresh gate circuit F receives the carry signal output from the video counter C and outputs an H signal as shown in FIG. 3(d).
It outputs a level signal, and when the count value of a built-in counter reaches a certain value, it outputs an L level signal (refresh enable signal).

The refresh control circuit H receives this refresh energy signal and generates a refresh signal R shown in FIG. 3 (θ).
11-RI3*R21~"!3+R□~Outputs RRB.

The memory M undergoes a refresh operation during the period of the refresh signal.

In this way, during the video gate signal output period, Memo I)
Information reading and printing operations from M are performed, and during this gate signal output period, refresh operations are performed on the memory M. Since only reading from the memory M can be executed without any intervention, the number of reading operations during the gate signal output period can be increased and high-speed printing becomes possible.

Incidentally, as shown in FIG. 2, the error data correction operation in the memory M by the patrol circuit P may also be performed after the video gate signal output period, as shown in FIG. 3(f). This correction operation is performed as follows.

In other words, video and gate signal output period TII * T1
2 r After Tl1l, the above-mentioned freshy operation is performed, but this is followed by a patrol signal output period T31.
* T32 * During T1S, the patrol circuit P outputs a patrol read signal to the memory M, and the memory M
The data therein is read word by word and input to the error correcting code processing circuit E. If there is an error 9 in the input data, the error correction code processing circuit E corrects it, sends out an error flag, and stores the corrected data in the original storage area of the memory M.

If there is no error in the data input to the error correcting code processing circuit E, the data is stored as is in the original storage area of the memory ljM.

Note that the data output from Process 2-Collecting code processing E is sent to a printing section (not shown) for printing.

In the above embodiment, the memory control method in the printing device was explained, but the present invention is not limited to this, and it goes without saying that the data output from the memo IJM may be displayed on the display device. In this case, the display operation is performed using the data from memory M during the above-mentioned video gate signal output period, and the memo +
7 Perform refresh operations and data error correction operations on M.

(C)) As described in detail, the memory control method according to the present invention performs read operations on the memory all at once over a fixed period of time, and performs refresh operations and error correction operations on the memory separately from this fixed period. Since it is performed within the period, high-speed reading to the memory becomes blind.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a conventional memory control system, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIGS. 3(a) to 3(f) are diagrams for explaining operation. N: Arithmetic circuit, Engineering: Scanning synchronization signal generation circuit, C: Video counter, G: Video gate circuit, F: Refresh gate circuit, M: Memory, H: Refreshing control + a[,
P: Pa roll circuit. Agent Patent Attorney Hiroshi Matsuoka

Claims (2)

[Claims] (1) A memory control method in which a randomly accessed dynamic memory is provided with an access period and an idle period, characterized in that the refresh operation is performed only during the idle period. (2) The memory control method according to claim 11, characterized in that a patrol operation is performed on the memory during the idle period.