JP2817154B2 - Still image receiving device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a still image receiving apparatus in an information service of a program composed of color still image video and audio such as characters, figures, and photographs.

2. Description of the Related Art As a conventional still image receiving apparatus, for example,
No. 6284.

FIG. 5 shows a configuration diagram of this conventional still image receiving apparatus. Reference numeral 10 denotes input of program information composed of coded still image information, which is program information, memory control information, and screen control information. Terminal, 20 is a decoding circuit for supplying to the memory control circuit 50 a decoding process operation signal 115 indicating that decoding of the coded still image information and the decoding process are in progress, and 30 and 40 are the still image output signals of the decoding circuit 20. First and second frame memories to be stored, 50
Is a memory control circuit that controls writing and reading of the memory from the contents of the memory control information, and 60 is a control circuit that is composed of a timer circuit and the like, and switches output signals of the first and second frame memories 30 and 40 from the contents of the screen control information A screen control circuit for generating a signal; 70 is a first and second frame memory 30;
This is a switching circuit for switching the output signal of 40 with the screen control signal of the screen control circuit 60. Reference numeral 80 denotes a still image signal output terminal.

The operation of the conventional still image receiving apparatus configured as described above will be described with reference to the time charts of FIGS. 6 and 7. The program information signal 100 input to the input terminal 10 includes a no-signal period 101, a still image information period 102,
, And is supplied to the decoding circuit 20, the memory control circuit 50, and the screen control circuit 60. After the decoding signal processing (delay time TD1) 111, the decoding circuit 20 stores the decoded still image information (shown at 110) in the first and second frame memories 30, 40.
A decoding operation signal 115 indicating that decoding is being performed is supplied to the memory control circuit 50. The memory control circuit 50 controls the program information period 103
A memory designation signal 120 is detected from the memory control information included in the first and second frame memories 30 and 40, and the designated signal
0 is supplied to control writing and reading of still image information. For example, the first frame memory 30 and the second frame memory 40 are memory designation signals output from the memory control circuit 50.
In the "1" period 121 of 120, the decoded still image information (A) from the decoding circuit 20 is written at the speed at which it is transmitted to the first frame memory 30, and in the "0" period 122 of the memory designation signal 120, , The still image information (B) decoded from the decoding circuit 20 is the second
The data is written to the frame memory 40 at the transmission speed. Reading is performed at the display speed after writing is completed.

Next, the screen control circuit 60 controls the start and the switching time 131 of the display of the still image information from the screen control information of the program information 103 by the falling period of the output signal 130 of the timer circuit of the screen control circuit 60, and the memory switching signal 140 Is supplied to the memory switching circuit 70. The memory switching circuit 70 displays the content (A) of the first frame memory 30 when the memory switching signal 140 is, for example, "1" (period 141). "0" (shown)
The content (B) of the second frame memory 40 is displayed. (The second RD indicates that the second frame memory 40 is being read out.) The display state on the monitor is shown at 150 in FIG.

However, in the configuration as described above, when the number of still images constituting the program is an odd number, when switching the program, the still image information is written to the currently displayed frame memory. The displayed screen is distorted. For example, when five programs 401 and 402 composed of five still image information shown in 100 of FIG. 7 are transmitted, at the time of switching 403, if the memory designation information always starts from the first frame memory 30, the first Since the writing of the still image information (a) is controlled while the frame memory 30 is displaying the still image information (E), the first frame memory
30 overlaps (E) and (a). Therefore, if the memory configuration of the first frame memory 30 is, for example, the same as the input and output, there is a problem that the screen being displayed is disturbed (shown by a hatched portion 151 in FIG. 7) because the writing control state is set in spite of the reading. Was. Such a state is also caused by erroneous detection of screen control information due to transmission noise when switching channels.

In view of the above, the present invention provides a still image receiving apparatus that receives still image information without disturbing the currently displayed screen even when the control of writing the still image information to the currently displayed frame memory occurs. Aim.

Means for Solving the Problems The present invention receives program information including at least still image information, memory control information for controlling a plurality of memories, and screen control information for controlling a display screen, and receives the program information from the memory control information. A memory control circuit that specifies a memory, a plurality of memories that store the still image information, a screen control circuit that controls reading of the plurality of memories from the screen control information and supplies a memory switching signal to a switching circuit, A switching circuit for controlling switching of reading of the plurality of memories; a memory designation detecting circuit for detecting designation of writing and reading of memory from the memory control information; and a memory designation circuit comprising a plurality of flip-flop circuits and logic circuits. A duplication detection circuit for detecting whether or not the output signal of the detection signal designates a memory being displayed; and The still image receiving apparatus includes a memory control circuit and an exclusive OR circuit for inverting an output signal of the screen control circuit.

Operation The present invention enables the above-described configuration to prevent the display memory specification and the write memory specification from being duplicated when switching between odd-numbered programs or when switching channels.
A memory designation detection circuit that detects designation of writing and reading of memory from the memory control information, and is configured with a plurality of flip-flop circuits and logic circuits, and whether an output signal of the memory designation detection signal designates a memory being displayed And an exclusive OR circuit for inverting the outputs of the memory control circuit and the screen control circuit with the output of the duplication detection circuit to prevent duplication of memory designation and disturb the displayed image. A still image receiving apparatus can be provided.

Embodiment FIG. 1 shows a configuration diagram of a still image receiving apparatus according to a first embodiment of the present invention. In FIG. 1, components that operate in the same manner as in the related art are given the same reference numerals and description thereof is omitted.
Reference numeral 90 denotes a duplication detection circuit provided for the present invention, and a memory designation detection circuit 91 and a first flip-flop circuit 92 (hereinafter referred to as a first flip-flop circuit).
1FF circuit), 93 second flip-flop circuit (hereinafter referred to as second FF circuit), 94 exclusive-OR circuit (hereinafter referred to as EXOR circuit), and 95 third flip-flop circuit (hereinafter referred to as 3F circuit).
F circuit). Reference numerals 96, 97, and 98 denote EXOR circuits for controlling the inversion of the output signals of the memory control circuit 50 and the screen control circuit 60 with the output signals of the overlap detection circuit 90.

The operation of the still image receiving apparatus according to this embodiment configured as described above will be described below with reference to the time chart of FIG. In FIG. 2, components operating in the same manner as in the prior art are denoted by the same reference numerals, and description thereof is omitted. 200 is a memory designation detection circuit 91, 210 is a first FF circuit 92, 220 is an EXOR circuit 94, 2
30 is an output signal of the second FF circuit 93, and 240 is an output signal of the third FF circuit 95.

The duplication detection circuit 90 that detects duplication of memory designation is included in the conventional memory control circuit 50 when, for example, a program 401 composed of five still images and a next program 402 are supplied from the program information input terminal 10. A memory designation detection circuit 91 similar to the above detects a designation signal of the frame memory and decodes a decoding operation signal 115.
Is supplied to the first FF circuit 92 and the EXOR circuit 94. The first FF circuit 92 receives the decoding processing operation signal 115 supplied from the decoding circuit 20 as a clock input and outputs the output signal of the EX 210
It is supplied to the OR circuit 94. The EXOR circuit 94 sets the LOW level when the memory specification does not overlap (221) and sets the H level when the memory specification overlaps (222).
The signal becomes the IGH level and the signal shown at 220 is input to the clock terminal of the second FF circuit 93. The second FF circuit 93 outputs a signal 230 opposite to the previous state according to the output signal 220 of the EXOR circuit 94. 2nd floor
The output signal 230 of the F circuit 93 is the third FF circuit 95 and the EXOR circuits 96 and 97.
To supply. The EXOR circuit 97 outputs the output signal 230 of the second FF circuit 93.
As a result, the memory designation signal 120 is inverted from the point of time 404, the signal indicated by 121 is supplied to the first frame memory 30, and the operation switches from writing to reading. Therefore, a continuous writing operation can be prevented. The third FF circuit 95 operates at the timing of the timer output signal 130 and supplies a signal indicated by 240 to the EXOR circuit 98. The EXOR circuit 98 inverts the memory switching signal 140 from the point of time 405 in response to the output signal 240 of the third FF circuit 95 and supplies the signal indicated by 141 to the switching circuit 70 to read from the first frame memory to the second frame memory. Switch. Therefore, the reading operation of the first frame memory can be continuously prevented.

As described above, according to this embodiment, the overlap between the display frame memory specification and the write frame memory specification that occurs when a program composed of an odd number of programs or a channel is switched is determined based on the memory control information. A memory designation detecting circuit for detecting designation of reading and reading, a duplication detecting circuit comprising a plurality of flip-flop circuits and a logic circuit and detecting whether or not the output signal of the memory designation detecting signal designates a memory being displayed By providing an exclusive OR circuit that inverts the outputs of the memory control circuit and the screen control circuit with the output of the duplication detection circuit, a still image receiving device that prevents duplication of memory designation and does not disturb the displayed image is provided. Can be provided.

In this embodiment, the decoding operation signal 115 is used as a clock signal under the control of the first FF circuit 92, but a signal indicating that the still image receiving apparatus has detected the still image information 102 or the program information 103 is used. You may. Also, during the overlapping period, a blanking circuit for blanking the output of the switching circuit is provided to prevent screen disturbance.

FIG. 3 shows a configuration diagram of a still image receiving apparatus according to the second embodiment of the present invention. In FIG. 4, components that operate in the same manner as in the related art are given the same reference numerals, and description thereof is omitted.
Reference numerals 51 and 61 denote a frame memory sequential control circuit and a screen sequential switching signal control circuit provided for the present invention.

The operation of the still image receiving apparatus according to the present embodiment configured as described above will be described below with reference to the time chart of FIG. In FIG. 4, components that operate in the same manner as in the related art are given the same reference numerals, and description thereof is omitted. 510 is an output signal of the frame memory sequential control circuit 51, and 610 is an output signal of the screen sequential switching signal control circuit 61.

The frame memory sequential control circuit 51 includes a detection circuit for detecting still image information to be sequentially displayed and program information for sequentially controlling the display screen, a flip-flop circuit, and the like, and an input signal 100 supplied from the program information input terminal 10. The frame memory control signal 510 is switched to the first and second frame memories 30 and 40 by the flip-flop circuit which inverts the state each time the still image information to be sequentially displayed and the program information for sequentially controlling the display screen are detected. It is supplied to the switching signal control circuit 61. The first and second frame memories 30 and 40 write the input still image information 102 to the first frame memory 30 for a period of “1” by the frame memory control signal 510 supplied from the frame memory sequential control circuit 51, 0 "period 122 is the second
The data is written and stored in the frame memory 40. The screen sequential switching signal control circuit 61 is composed of a timer circuit, a flip-flop circuit and the like, and includes a frame memory control signal 510 and a timer output signal 1
Switching circuit 7 for image sequential switching signal shown from 30 to 610
Supply 0. Therefore, the reading operation of the same frame memory can be prevented continuously.

As described above, according to this embodiment, the overlap between the display frame memory specification and the write frame memory specification that occurs when a program is switched or a channel is switched is determined by the frame memory sequential control circuit 51 and the screen sequential switching signal control. By sequentially displaying the still image information transmitted by the circuit 61, it is possible to provide a still image receiving apparatus that prevents duplication of memory designation and does not disturb the image being displayed. Further, since there is no need to add information specifying the memory, the number of processing circuits on the transmitting and receiving sides can be reduced.

Effects of the Invention As described above, according to the present invention, it is possible to provide a still image receiving apparatus that prevents a memory specification from being duplicated when a program is switched or a channel is switched and does not disturb a displayed image. Yes, its practical effect is great.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a still image receiving apparatus according to an embodiment of the present invention, FIG. 2 is an operation waveform diagram of the embodiment, FIG. 3 is a configuration diagram of a still image receiving apparatus according to another embodiment of the present invention, FIG. 4 is an operation waveform diagram of the embodiment, and FIG. 5 is a configuration diagram of a conventional still image receiving apparatus. 6 and 7 are operation waveform diagrams of a conventional example. 10 ... program information input terminal, 20 ... decoding circuit, 30, 40 ...
1st and 2nd frame memory, 50 ... Memory control circuit, 51 ...
Frame memory sequential control circuit, 60 Program control circuit, 61
…… Screen sequential switching signal control circuit, 80 …… Still image output terminal, 90 …… Discontinuity detection circuit, 92,93,95 …… First, second, third flip-flop circuits, 94,96,97,98… ... Exclusive OR circuit.

Claims (2)

(57) [Claims] 1. A memory for receiving program information including at least still image information, memory control information for controlling a plurality of memories, and screen control information for controlling a display screen, and specifying a memory from the memory control information. A control circuit, a plurality of memories for storing the still image information, a screen control circuit for controlling reading of the plurality of memories from the screen control information and supplying a memory switching signal to the switching circuit, and reading the plurality of memories A switching circuit for controlling the switching of the memory, a memory designation detecting circuit for detecting designation of writing and reading of the memory from the memory control information, and a plurality of flip-flop circuits and a logic circuit. A duplication detection circuit for detecting whether or not a memory being displayed has been designated; and an output signal of the duplication detection circuit, the memory control circuit and a screen Still picture receiving device, characterized by comprising an exclusive OR circuit for inverting the output signal of the control circuit. 2. The still image receiving apparatus according to claim 1, further comprising a blanking circuit for prohibiting screen display during an overlap period detected by the overlap detection circuit.