JPS62165790A - Dram refresh circuit - Google Patents

Abstract

PURPOSE:To output a picture data at a high speed by applying prescribed number of times of refresh of a DRAM at once at the outside of an image area. CONSTITUTION:When the inverse of LDREQ signal is not inputted to a detection section 12 of a refresh control circuit 11 for a prescribed period, its output signal the inverse of NOREQ is brought into 'L' level and a generating section 13 outputs a refresh signal the inverse of REF for a DRAM to a bit map memory at each 500ns. Further, a refresh counter is decremented by one at every input of the inverse of REF signal and when the count reaches '0', the counter 14 is preset. When the inverse of REFEND signal of the detection section 12 goes to 'L' at the same time, the signal the inverse of NOREQ goes to 'H' to complete the refresh at SOS period. The refresh number of times at one blanking period of the counter 14 is set by a CPU or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a dynamic random access memory (hereinafter abbreviated as DRAM) circuit used as an image memory.

(Prior Art) In an image output device such as a laser beam printer, there is a method in which image data to be output is temporarily stored in an image memory. When the Bi-Sotomasob method is used as a character image generation method, usually one page's worth of image data is stored in an image memory (bitmap memory).

Since the image memory has such a large capacity, it is generally
RAM is used.

DRAM is a type of memory in which stored information corresponds to the presence or absence of charge on a capacitor. To compensate for this charge loss, DRA
It is necessary to periodically restore the information held by the memory cells that make up M. This operation is called refresh. Normal memory operations cannot be performed while the reflex song is being performed.

(Problem to be Solved by the Invention) In order to allocate this refresh cycle (period) within the period (for example, 2 ms) that requires refresh, for example, refresh cycles for all memory cells must be consecutively performed. There are two methods: a method that performs this, and a method that disperses data over a period of 2 ms.

By the way, in an image output device, if refresh is performed during the image output period (within the image area), (output time + refresh time) it is necessary to send out monthly data units (for example ■ bytes), and the speed cannot be increased. do not have.

Therefore, if refresh is performed outside the image area (also called blanking time), the speed can be increased. For example, in the image output device of Japanese Patent Application Laid-Open No. 59-143472, there is a description that refreshing is performed during the blanking period. (However, there is no description of the specific circuit configuration.) The image data output speed to laser printers, etc. will be determined in the future.
It is expected that the speed will continue to increase.

Therefore, refresh of the DRAM must be performed outside the image area so as not to impede speeding up.

An object of the present invention is to provide a RAM refresh circuit that is useful in an image output device that outputs the contents of DRAM at high speed.

(Means for Solving the Problems) A DRAM refresh circuit according to the present invention includes an image memory made of DRAM, and outputs image data from the image memory to a printer in response to input of an image data request signal from the printer. In the DRAM refresh circuit in the image generation section, a detection means for generating a first signal when an image data request signal is not input for a certain period of time;
refresh signal generating means for generating a predetermined number of second signals for refreshing the above-mentioned DRAM at fixed time intervals when a signal is generated and outputting them to the above-mentioned DRAM; The signals are counted, and when a predetermined number is reached, the second
and stop means for stopping the generation of the signal.

(Function) In image output, when it is detected that the image is outside the image area of the image output by not generating an output request signal from the print engine for a certain period of time, the necessary refresh is performed on the DRAM constituting the image memory at once. Do it several times. This predetermined number of times is determined based on the DRAM standard, etc., and is set in the refresh signal generating means.

(Example) Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows a block diagram of a laser beam printer that generates character images using a bitmap method.

The graphic information from host l is sent to character image generator 2.
The image data is stored in the bitmap memory (image memory) 3 as l pages of bit image data. This bit image data is output to the print engine 7 via the print engine control section 6 in response to an output request. The print engine uses a laser beam to write on the photoreceptor in accordance with this human image data.
Printed using electrophotography. The character code information from middle strike 1 is stored in the text buffer 4 as a character code string for one page, and this character code string is converted into a dot pattern for each font stored in the font memory 5. and stores it in the bitmap memory 3.

The bitmap memory 3 is a large capacity DRAM and needs to be refreshed periodically.

Refresh specifications vary depending on the type of DRAM used, but are stipulated to be refreshed once every 4 ms or more for each memory cell, for example. Refresh is usually done in DRAM
This is performed sequentially for each row of the chip's memory cell array.

For example, a DRAM with 256 arrays requires 256 refreshes within 4 ms. To speed up image output, each refresh is performed outside the image area (
blanking period).

FIG. 1 shows a refresh control circuit for refreshing a DRAM, and FIG. 3 shows a refresh timing chart. When the print engine control unit 6 receives a signal 5O8 (generated at a timing (period t2) specific to the print engine 7) indicating the start of scanning one line from the print engine 7 during image output, the print engine control unit 6 outputs an L signal.
A DREQ signal (1-byte image data request signal) is output to the character generating section 2. In response to this, the character generation unit 27 - reads the bit image data from the bitmap memory 3 by the image memory access unit 15 , and outputs each 1-byte data to the print engine 7 via the print engine control unit 6 . At the time of output, the image data for page 1 is stored in the bitmap memory 3, and then the print engine 7 sends LDREQ signals equal to the number of main scanning lines for one page. (Therefore, [one period L2 of the DREQ signal
The number within varies depending on the size of the vane. ) The LDREQ detection section 12 of the refresh control circuit 11 is
If the LDREQ signal is not input even after a certain period of time t3, it is the refresh period, so the output signal N0R
Lower your EQ to a lower level. Refresh signal generator 13
In this embodiment, when the N0REQ signal becomes low level, the DRAM refresh signal REF is set to about 500.
It is output to the bitmap memory 3 every ns. This memory 3 is stored once for each positive signal.

1' (EF scratch signal) is also input as a down count clock to the refresh counter 14, which is a down counter.The refresh counter 14 is preset to a predetermined number (64 in this example), and One is subtracted for each input.

When the REF signal is turned on a predetermined number of times, the count value becomes "0" and the REFEND signal, which is a borrow, becomes low level. As a result, the refresh counter 14 is preset. At the same time, when the REFEN D signal becomes low level, the L D REQ detection unit 12 makes the output signal N0REQ high level, and ends the refresh in this SO8 period.

The preset value of the refresh counter 14 (i.e.
(2) The number of refreshes during the blanking period) is normally set by a CPU (not shown) or by a DIP switch or the like. Further, this value is determined from the period t2 of the SOS signal and tl, which substantially corresponds to the period outside the image area.

Since we are currently using a DRAM that requires 256 refreshes within 41+18, if t2=Ims, refresh must be performed 64 times or more in 1 ms. Therefore, period t2 is 64×500ns
= 32 μs or more, refresh can be performed 64 times. Note that these values, such as 500 ns and the period, may be determined depending on the characteristics of the DRAM used and the peripheral circuit configuration.

(Effects of the Invention) Since the DRAM constituting the image memory is refreshed a predetermined number of times outside the image area, high-speed output of image data is not hindered.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the number of refreshes. FIG. 2 is a block diagram of a laser beam printer. FIG. 3 is a refresh timing chart. 3... Image memory (bitmap memory), 11.
...Refresh control circuit, I2...LDREQ detection unit 13...Refresh signal generation unit, 14...Refresh counter.

Claims (1)

[Claims] (1) Dynamic RAM (hereinafter abbreviated as DRAM)
In a DRAM refresh circuit in a character image generation section, which is equipped with an image memory consisting of a detection means for generating a first signal; refresh signal generation means for generating a predetermined number of second signals for refreshing the DRAM at regular intervals when the first signal is generated and outputting them to the DRAM; counting the second signals generated after the first signal;
A DRAM comprising a stop means for stopping the generation of the second signal in the signal generation circuit when a predetermined number is reached.
refresh circuit.