JPH0319047A - Memory control system and its device - Google Patents

Abstract

PURPOSE:To prevent such mistakes where the data are wrongly written into or read out of the addresses different from the due one to receive an access by forcibly switching the action mode to a normal access mode before the RAS pulse width time does not satisfy the memory specifications. CONSTITUTION:The upper limit value of the allowable RAS active time is previously set to a storage means 31. Then the RAS active time is measured by a measuring means 32 at a memory access, and this measured value 36 is compared with the upper limit value 36. Based on the result of this comparison, a high speed access mode is suppressed. Thus the RAS pulse width always satisfies a memory 16 even if the accesses are continuously given to the memory 16 in a high speed memory access mode. Then it is possible to prevent such malfunctions where the data are written into or read out of the wrong addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control method for an information processing device, and relates to a memory suitable for DRAM memory access having high-speed access modes such as page mode and static column mode. Regarding control method.

[Prior art] In recent years, due to the increase in the speed of semiconductor memory, 1MO3 DRAM
Even so, devices with an access time of 100 nanoseconds or less than 5 degrees are commercially available. Among these DRAMs, in addition to the normal access mode, some have been developed that have a high-speed access mode in which read and write operations can be performed at high speed.

In the normal access mode of the DRAM, the address to be accessed needs to be given to the DRAM twice: a row address and a column address. On the other hand, in a DRAM equipped with a high-speed access mode such as a page mode, when the row address to be accessed matches the row address accessed immediately before, high-speed access can be performed simply by providing a column address.

Conventionally, as a control method for memory consisting of DRAM equipped with these high-speed access modes, Japanese Patent Application Laid-Open No. 61-427
There is one described in Publication No. 93. This is because the last accessed row address is stored in the auxiliary memory in advance, and the part of the address given to the main memory at the time of the primary access that corresponds to the row address matches the storage content of the auxiliary memory. It is configured so that only the column address is given if there is a hit. This allows the DRAM to operate in high speed access mode when the row address is hit.

The configuration and operation of such a conventional memory system will be explained using FIG. 6.

In the figure, 10 is a CPU. 11 is a hit determination circuit, which stores the last accessed row address;
If the row address of the next access matches the row address of the previous access, a control signal 17 is given to the timing control circuit 12.

12 is a timing control circuit that controls the memory 16, generates control number 48 for the address selector 13, etc. 13 is an address selector, and the CPU 10 or D
The memory 16 is planted at the address 18 output by the MAC 14.
Switches the row address and column address given to the address. The memory 16 receives a control signal RA from the timing control circuit 12.
S21, CAS22, and multiplexed address 23 are input. 26 is a bus hold request signal (hereinafter referred to as -HRQ) for CPUl0, 27 is a DMA
Hold acknowledge signal for C14 (hereinafter referred to as H
When this HLDA is active, the DMAC 14 becomes a bus mask. Note that the bar above each signal name represents negative logic, but this will be omitted below.

Next, its operation will be explained. Assume that the row address stored in the hit determination circuit 11 has been cleared.

The address 18 output by CPUl0 is sent to the hit judgment circuit 1.
1 is compared with the last accessed row address. Since the row address accessed last time has been cleared, the previous row address and the current row address do not match (hereinafter referred to as a mishit). The hit determination circuit 11 outputs a control signal 17 to the timing control circuit 12 to inform it that there is a miss. In response to this, the timing control circuit 12
accesses the memory 16 in normal access mode rather than high-speed page mode access. Its operation is
Before RAS21 falls, the switching signal 25 is output to the address selector 13, selects the address 18 from the CPU10, and transfers the row address to the memory 16 through the address bus 23.
give to The memory 16 stores the given row address in RA.
It is taken into the internal memory at the falling edge of S21. after that.

The timing control circuit 12 controls the switching signal 25 outputted to the address selector 13 so that the column address is selected. This column address also passes through the address bus 23,
It is input into memory 16. As with the row address, the memory 16 takes in the column address internally at the falling edge of CAS22, and the memory 16 selects data corresponding to the given row address and column address.
0's access to memory 16 ends. Further, the hit determination circuit 11 compares the address 18 output from the CPU 10 in the next access with the row address held internally at the previous access and the current row address. if,
In the case of a miss, a control signal 1 is sent to the timing control circuit 12 to control the memory 16 in the normal access mode.
Give 7.

In response, in the case of a hit, the timing control circuit 12 changes the column address from C0L1 to C0L2 in FIG. 7 while keeping the RAS 21 active, and controls the column address to be given to the memory 16 for page mode access. .

If the row address matches the last accessed row address, set the column addresses C0L2 and C0L3 while keeping RAS21 active as shown in Figure 7.
, C0L4. . . , and by simply importing it into the CAS 22, the memory 16 can be accessed at high speed. This is because there is no need for precharging time for the RAS 21 unlike in the 1 normal access mode. Also, CPUl0 is not a bus mask but a DMAC1
A similar operation can be performed when 4 is a bus mask.

[Problems to be Solved by the Invention] In such a high-speed memory system, for example, if an IM bit DRAM with a 1-bit configuration is used and the memory is accessed using consecutive addresses, in principle there will be 21
The memory can be accessed continuously o=1024 times in high-speed page mode. because.

This is because in a 1-bit configured IM bit DRAM, both the row address and the column address are 10 bits (=2-0 address). Therefore, if one memory access is completed in 200 ns, 200 ns x 102
4 times = 204800 ns = 204, 8 L1
8, the RAS signal needs to be active (“L” level). However, there is a limit to this RAS pulse width time.
In the case of RAM, it is 10000ns (=10μs).

On the other hand, DRAM conventionally performs refresh operations periodically at a rate of once every fixed period of time, such as 8 μs, and as a result, the RAS is not kept active for more than the above fixed period of time, resulting in the above-mentioned problems. did not occur.

However, due to improvements in DRAM elements themselves or improvements in refresh technology to improve memory access efficiency, the refresh interval has become longer.
Along with this, a situation has arisen in which accessing the memory in successive page mode cycles exceeds the RAS pulse width time limit.

Therefore, if you try to continue the high-speed access mode beyond the RAS pulse width time limit, there is a risk of malfunctions such as writing data to a different address than the intended address or reading data from a different address. occurred.

An object of the present invention is to provide a memory control method and device that does not cause malfunctions in reading and writing of DRAM even if the memory is accessed continuously in a high-speed memory access mode such as page mode. [Means for Solving the Problems] In order to achieve the above object, a memory control method according to the present invention determines whether the row address of the address to be accessed matches the row address of the address accessed immediately before. , in a memory control method that accesses the dynamic RAM in a high-speed access mode if they match, the active time during which the row address capture signal is active is measured, and when the measured time reaches a predetermined time, the above The high-speed access mode is switched to the normal access mode.

Another memory control method according to the present invention determines whether the row address of the address to be accessed matches the row address of the address accessed immediately before, and if they match, the memory is accessed in a high-speed access mode. In the control method.

Count the number of times the above line address matches consecutively.

When the counted value reaches a predetermined constant value, the high speed access mode is switched to the normal access mode.

A memory control device according to the present invention is a memory control device that controls a dynamic RAM having a high-speed access mode, and includes address selection means for switching row and column addresses applied to the dynamic memory, a switching control signal for the address selection means, Timing control means for generating a row address capture signal and a column address capture signal of the dynamic memory, and determining whether or not the row address of the address to be accessed matches the row address of the address accessed immediately before, and determining the determination result. a hit determination means for switching between a high-speed access mode and a normal access mode by controlling the timing control means according to the above; a measurement means for measuring the active time of the row address capture signal; and a measurement value of the measurement means; The apparatus includes a comparison means for comparing with a predetermined constant value, and a masking means for invalidating the output of the determination means based on the comparison result of the comparison means.

Another memory control device according to the present invention is a memory control device for controlling a dynamic RAM having a high-speed access mode, which includes address selection means for switching row and column addresses given to the dynamic memory, and switching control for the address selection means. a timing control means for generating a row address capture signal and a column address capture signal of the dynamic memory, and a timing control means for generating a row address capture signal and a column address capture signal of the dynamic memory, and a timing control means that determines whether the row address of the address to be accessed matches (hits) the row address of the address accessed immediately before. judge,
Hit determination means for switching between high-speed access mode and normal access mode by controlling the timing control means in accordance with the determination result; measurement means for counting the number of consecutive hits of the hit determination means; and measurement means for counting the number of consecutive hits of the hit determination means. The apparatus includes a comparison means for comparing the value with a predetermined constant value, and a masking means for invalidating the output of the determination means based on the comparison result of the comparison means.

When the device that accesses the dynamic RAM is a direct memory access control device, means may be provided for always invalidating the coincidence output of the hit determination means.

Note that examples of the high-speed access mode include page mode and static column mode, but the present invention is not limited to these, and the present invention can be applied as long as there is an upper limit to the duration of the high-speed access mode. I can do it.

[Function] In the memory control method according to the present invention, the allowable RA
Set the upper limit value of S active time in the storage means,
At the time of memory access, the RAS active time is measured by a measuring means, the measured value is compared with an upper limit value, and the high-speed access mode is inhibited according to the result of this comparison. In other words, if the measured value becomes larger than the set upper limit, even if the high-speed access mode is applicable,
Control memory in normal access mode instead of fast access mode.

The determination to suppress the high-speed access mode may be made based on the number of consecutive hits of the hit determining means instead of using the RAS active time as the reference.

According to the present invention, even if the memory is accessed continuously in high-speed memory access mode, the RAS pulse width will not fail to satisfy the memory specifications. No malfunctions such as reading occur.

[Embodiments] Hereinafter, embodiments of the memory control device according to the present invention will be described in detail.

First, FIGS. 1 and 2 show the configuration of a first embodiment.

In the same figure, as in the conventional device shown in FIG. 6, 1o is a CPU, 11
is a hit determination circuit which stores the last accessed row address and outputs a control signal 17 if the next accessed row address matches the previous accessed row address. A timing control circuit 12 controls the memory 16 and generates a control signal for the address selector 13.

13 is an address selector, CPU10 or DM
The row address and column address to be given to the memory 16 are switched and selected from the address 18 output from the AC 14. memory 16
, a control signal RAS2 is sent from the timing control circuit 12.
1, CAS 22, and multiplexed address 23 are input.

26 is the bus hold request signal HRQ of DMAC14 for CPUl0, 27 is the CPU for DMAC14
This is the hold acknowledge signal HLDA of l0, and when this signal is active, the DMAC14 is
In this embodiment, the following elements are further added to this configuration. That is, 31 is a storage means for setting the time of the RAS pulse width. 32 is a total of 1fl11 means for measuring the RAS signal 21 output from the timing control circuit 12, and is initialized when the RAS signal 21 is at the t4H" level. 33 is a set value 3 of the storage means 31.
5 and the measured value 36 of the measuring means 32, and when the measured value 36 is larger than the set value 35, it outputs the control signal 30 to the masking means (logical product circuit) 34 and controls the Mask (invalidate) signal 17. Measuring means 3
2 can be composed of a counter 321 and a clock generator 322, for example, as shown in FIG. That is, the counter 32
The clock signal output from the clock generator 322 is connected to the clock input of 1, and the RAS signal 21 is connected to the clear input.

Next, the operation of the device of the first embodiment will be explained. 1st
The shaded portion of the bus 18 in the figure indicates that CPU10 is the bus master.

First, the storage means 31 stores an RAS that matches the specifications of the memory.
Set the pulse width time. It is also assumed that the row address stored in the hit determination circuit 11 has been cleared. The hit determination circuit 11 compares the row address of the address 18 from which the CPU 10 appeared with the row address accessed last time.

The last accessed row address has been cleared, so
The previous row address and the current row address do not match, resulting in a miss. At this time, the hit determination circuit 11 notifies the timing control circuit 12 that there is a miss through the control signal 17 to the masking means 34 . At this time, the setting value is 35
is larger than the measured value 36. Because RAS signal 21
is II Fr 1 lebel, and the measuring means 32 has been initialized. Therefore, since the control signal 17 is not masked by the masking means 34, a miss is transmitted to the timing control circuit 12. At this time, the timing control circuit 12 accesses the memory 16 in normal access mode instead of page mode access.
This operation is performed by switching the switching signal 25 before the RAS signal 21 falls.
is output to the address selector 13, selects the address 18 from the CPU 10, and provides the row address to the memory 16 via the address bus 23. The memory 16 takes in the given row address at the falling edge of the RAS signal 21. At this time, the measuring means 32 starts measuring from the falling edge of the RAS signal 21. That is, the counter 321 inside the measuring means 32 is cleared, and the clock generator 322 starts counting. After that, the timing control circuit 12
is the switching signal 25 that was output to the address selector 13.
, so that the column address is selected. This column address is also input to the memory 16 via the address bus 23. The memory 16 contains CAS as well as the row address.
Memory 1 takes in the column address internally at the falling edge of 22.
6 completes one access to the memory 16 of the CPU 10 with 0 or more selecting data corresponding to the given row address and column address.

The hit determination circuit 11 receives the address 18 outputted from the CPU 10 in the next access, and compares the row address held internally from the previous access with the current row address. If there is a mishit, a control signal 1 is sent to the timing control circuit 12 to control the memory 16 in the normal access mode.
Give 7.

In this case, the measuring means 32 is initialized. In addition, in the case of a hit, the timing control circuit 12 controls the RAS2
1 and set the 1st column address to CO in Figure 7.
It changes from L1 to C0L2 and applies it to the memory 16 to control page mode access.

In this way, if the row address matches the last accessed row address, the column address is changed to C0L2. C0L
3. By simply changing it to C0L4... and importing it into the CAS 22, it is possible to access the memory 1G at high speed. In this case, the measuring means 32 continues to measure the RAS active time. If the memory 16 continues to be accessed in page mode and the measured value 36 becomes larger than the set value 35, the comparing means 33 outputs a mask signal 30 to the masking means 34. Even if the access after the mask signal 30 is output is a hit, it is masked by the masking means 34 and is transmitted to the timing control circuit 12 as a miss. In response to this, the timing control circuit 12 controls the memory 16 in normal access mode by inactivating the RAS signal 21 instead of in page mode access.

At this time, the measuring means 32 is initialized again. In this way, even if page mode access is performed to the memory 16 continuously, the memory 16 is controlled in one normal access mode before the RAS pulse width no longer satisfies the memory specifications, thereby preventing memory access problems. can be resolved.

Therefore, data will not be written to an address different from the write and read addresses, or data will not be read from a different address.

In addition, as shown in the shaded area of the bus 18 in FIG.
Even when C14 is a bus master, the same effect can be obtained through the same operation as in FIG.

FIG. 3 shows the configuration of a second embodiment of the memory control device according to the present invention.

In this embodiment, the control signal 17 output from the hit determination circuit 11 is measured instead of the means for measuring the RAS pulse width time shown in FIG. For this purpose, a measuring means 32 is provided. This measuring means 32 is, for example, as shown in FIG.
It can be configured with a counter 321. That is, the counter 32
A control signal 17 is input to the clock input of 1, and the number of pulses is counted. Further, the initialization signal 91 from the timing control circuit 12 is input to the clear input.

The counter 321 is initialized. Further, a storage means 31 is provided as a means for setting an upper limit value of the number of consecutive accesses in page mode, that is, the number of consecutive hits. The comparison means 33 compares the set value 35 of the storage means 31 and the measured value 36 of the measurement means 32, and outputs the result to the masking means 34 as a mask signal 30.

When the memory 16 is continuously operated in page mode, the measuring means 32 counts the control signal 17 from the hit determination circuit 11 until a miss occurs.

When this measured value 36 becomes larger than the set value 35, the comparison means 33 outputs a mask signal 30.

The control signal 17 is masked by the masking means 34. Therefore, even if the hit determination circuit 11 determines that the hit is a hit, the timing control circuit 12 is notified that the hit is a miss. Therefore, the timing control circuit 12 controls the memory 16 in normal access mode instead of page mode access, and also sends an initialization signal 91 to the measuring means 32.
Output and initialize.

Furthermore, as shown in FIG. 4, when the DMAC 14 is the bus master, the same effect can be obtained through the same operation as when the CPU 10 of FIG. 3 is the bus master.

FIG. 5 shows the configuration of yet another embodiment. In this embodiment, when the DMAC 14 is the bus master, the memory 16
is forcibly controlled by normal mode access.

For that purpose, HLD A (No. 3 27 is masked by mask means 3)
4 is entered. Mask signal 30 to mask means 34
Although not shown in the drawing, the generating means may be based on the RAS pulse width shown in FIG. 1 or based on the number of hits shown in FIG. 3.

In this embodiment, when the DMAC 14 activates the HRQ signal 26 for CPUl0, CPtJlo activates the HLDA signal 27 and transfers bus control to DM.
Pass it to AC14. At the same time, the HLDA signal 27 is input to the masking means 34 as a mask signal. Therefore, even if the hit determination circuit 11 determines that there is a hit, the timing control circuit 12 is informed that there is a miss I-.

As a result, timing control circuit 12 controls memory 16 in normal access mode rather than page mode access while DMAC 14 is the bus master.

Although page mode access has been described in each of the above embodiments, the same applies to other high-speed access modes such as static column mode.

Further, for example, in static column mode access, the present invention can be applied not only to RAS signals but also to CAS signals.

[Effects of the Invention] According to the present invention, when the RAS pulse width no longer satisfies the memory specifications even if the memory is accessed continuously in the high-speed access mode, the mode is forcibly switched to the normal access mode. This prevents memory from being accessed in page mode beyond the RAS pulse width time limit, and as a result, data may be written to a different address than the address to which it should be accessed, or data may be written to the wrong address. Data will no longer be read out.

[Brief explanation of drawings]

1 and 2 are block diagrams showing the structure of a first embodiment of the present invention, FIGS. 3 and 4 are block diagrams showing the structure of a second embodiment of the present invention, and FIG. 5 is a block diagram showing the structure of a second embodiment of the present invention. FIG. 6 is a block diagram showing the configuration of another embodiment of the present invention. FIG. 6 is a block diagram of a conventional high-speed memory system. FIG. 7 is a timing chart of DRAM page mode access.
FIG. 9 is a block diagram showing an example of the structure of the measuring means of the second embodiment. FIG. 9 is a block diagram showing an example of the structure of the measuring means of the second embodiment. DESCRIPTION OF SYMBOLS 11... Hit determination circuit, 12... Timing control circuit, 31... Storage means, 32... Measuring means, 33
Comparison means, 321... Counter, 322... Clock generator.

Claims (1)

[Claims] 1. Memory control that determines whether the row address of the address to be accessed matches the row address of the address accessed immediately before, and if they match, accesses the dynamic RAM in high-speed access mode. A memory control method, characterized in that: an active time during which a row address capture signal is active is measured, and when the measured time reaches a predetermined time, the high-speed access mode is switched to a normal access mode. 2. In a memory control method that determines whether the row address of the address to be accessed matches the row address of the address accessed immediately before, and if they match, the memory is accessed in high-speed access mode. A memory control method characterized in that the number of consecutive matches is counted, and when the counted value reaches a predetermined constant value, the high-speed access mode is switched to a normal access mode. 3. A memory control device for controlling a dynamic RAM having a high-speed access mode, comprising address selection means for switching row and column addresses given to the dynamic memory, a switching control signal for the address selection means, and a row address of the dynamic memory. timing control means for generating a capture signal and a column address capture signal; and determining whether a row address of an address to be accessed matches a row address of an address accessed immediately before, and controlling the timing according to the determination result. hit determination means for switching between a high-speed access mode and a normal access mode by controlling the means; a measuring means for measuring the active time of the row address capture signal; A memory control device comprising: a comparing means for making a comparison; and a masking means for invalidating the output of the determining means based on the comparison result of the comparing means. 4. A memory control device for controlling a dynamic RAM having a high-speed access mode, comprising address selection means for switching row and column addresses given to the dynamic memory, a switching control signal for the address selection means, and a row address of the dynamic memory. A timing control means that generates a capture signal and a column address capture signal, and determines whether the row address of the address to be accessed matches (hits) the row address of the address accessed immediately before, and determines whether or not the row address of the address to be accessed matches (hits) the row address of the address accessed immediately before. a hit determining means for switching between a high-speed access mode and a normal access mode by controlling the timing control means; a measuring means for counting the number of consecutive hits of the hit determining means; and a measuring means for predetermining the measured value of the measuring means. A memory control device comprising: comparing means for comparing with a constant value; and masking means for invalidating the output of the determining means based on the comparison result of the comparing means. 5. When the device that accesses the dynamic RAM is a direct memory access control device, the memory control according to claim 3 or 4, further comprising means for always invalidating the coincidence output of the hit determination means. Device.