JPS6139298A - Control device of dynamic random access memory - Google Patents

Abstract

PURPOSE:To decrease queuing time of an access and to speed up a memory system by making a method of refreshing special. CONSTITUTION:DRAM8 is divided into two banks B0 and B1, an address on an address bus of a system is changed over to a row and a column and respective banks have a selector 7 which changes over a refreshing address. Thus, an address of a system is inputted to one side bank and the refreshing address is inputted to another bank and input is executed simultaneously for the bank in which a usual access is different from the refreshing. As one means of the method to divide the tank, in many cases the above-mentioned action is executed by using a binary condition of the least significant address ''0'' and ''1'' at the address of the system after the bank is changed. As the result, the usual access and the refreshing are alternately executed. After two banks are alternately refreshed, occurrence of a refreshing request is controlled by resetting a refreshing request counter 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a dynamic random access memory (Dyn
amic Random Access Memory
The present invention relates to a control device for DRAM (hereinafter abbreviated as DRAM).

(Prior Art) DRAMs are used in various memory systems because they can store large amounts of data in small chips. In recent years, while there has been a demand for larger capacity systems, the price of DRAMs has been rapidly decreasing, so DRAMs are being used in a wide range of areas.

FIGS. 5 and 6 are time frames showing the basic operating modes of the DRAM, with FIG. 5 showing the read time and FIG. 6 the refresh time, respectively.

DRAM has normal access (read, write) and refresh cycles, but refresh cycles are 2+
It is necessary to perform 128 times with 113. Therefore, while the DRAM is being refreshed, the DRAM cannot be accessed.
There will be time.

FIG. 7 is a block diagram showing an example of a conventional DRAM control device. In the case of normal access to DRAM8, the microprocessing unit (hereinafter referred to as MP)
The address on the address bus connected to
The selector 6 decomposes the address into a row address and a column address, which are commonly input to all DRAMs. D R
A M 8 control signal RA S (row addr
ess 5trobe), CA S(coluw
+n address 5trobe),
WE (writeenable) is output from the timing generator 4, is switched by the bank selector 7 according to the upper address, and one bank is accessed.

Further, in the case of refreshing the DRAM 8, the refresh address from the refresh 1 address counter 5 is selected by the selector 6 and commonly input to all DRAMs. At this time, the RAS signal is also input to all DRAMs to perform refresh.

(Problems to be Solved by the Invention) Therefore, in the conventional control device having such a configuration,
There is a problem in that DRAM8 cannot be accessed until the refresh of the DRAM is completed, which has a negative effect on memory speed and system performance.

The present invention was made in view of the problems in the prior art, and its purpose is to reduce the access time and speed up the memory system by devising a refreshing method. The aim is to realize a RAM control device as much as possible.

(Means for Solving the Problems) The configuration of the present invention for achieving such an object includes a microprocessing unit, a dynamic random access system coupled to the microprocessing unit, and composed of two banks B0 and 81. The lowest address on the address bus coupled to the memory and the microprocessing unit is "I Q I+," the row column address bank selector selects and sends the row column address to the bank B0, 81 by the "1 pass," the lowest address; The refresh address from the refresh address counter is transferred to the bank 8 by “0” Z11111.
1. Refresh address bank selector sent to BO,
When both the banks BO and 81 have been refreshed, the refresh address counter is counted up and a refresh request is made. The refresh request counter is reset and the row column address selector is turned off by the refresh request. A timing generating section including means for refreshing the banks B0 and 81 at the same time by setting both refresh address bank selectors to A, counting up the refresh address counter, and resetting the refresh request counter; The present invention is characterized by comprising a bank selector that selects one of the banks using the lowest address and the highest address on the address bus and sends a column address strobe signal to the bank.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an example of a device according to the present invention. In this figure, parts corresponding to those of the conventional device shown in FIG. 7 are designated by the same reference numerals. In the present invention, first, the DRAM 8 is divided into two large banks 80.
(82, 84...) and 81 (83, B5...), and normal access and DRAM refresh are performed alternately.

The address bus row column selector 6o decomposes the address on the address bus coupled to the MPU 1 into a row address and a column address, and sends these to the row address bank selector 61. This selector 61 selects and sends a row column address to the bank 80 side or the bank B1 side depending on the lowest address of IQIZI "1".

Further, the refresh address bank selector 62 inputs the refresh address from the refresh address counter 5, and the lowest address is IQPI,
11 i )) selects and sends the refresh address to the bank B1 side or the bank 80 side.

The timing generator 4 includes means for incrementing the refresh address counter 5 and resetting the refresh request counter 3 when both banks Bo and B1 are refreshed, and the output of the refresh request counter 3, ( refresh request), the selector 61 is turned off, and the selector 62 is turned off.
, refreshes bank B0 and bank B1 at the same time, counts up counter 5, and resets counter 3. The bank selector 7 receives the CAS signal and WE multiplication signal from the timing generator 4, and during normal access, it selects one bank using the lowest address and the highest address, and sends the CAS signal to the selected bank. .

FIG. 2 is a structural block diagram showing more details of the device according to the present invention. Here, a case where the device is applied to a system with a 16-bit data bus and a 512-byte memory bus (64 64K DRAMs) is exemplified.

The bus interface section 2 is coupled to the address bus from M P tJ 1, and is connected to the address bus from M P
□ Create memory select 1 to signal O8 from the address, and use this C8
The signal is sent to the timing generator 4. The refresh request counter 3 sends the refresh request signal RFRQ to the timing generator 4 once every 15 μs.

During normal memory access, this timing generator 4
8 signals and bus control signals to RAS signal, CAS signal, W
Create each E times signal and send each bank BO-8 of DRAM8
3° Send to bank selector 7. Also, Row Column Select
160 select signals R8, each address driver 618 forming the row column address bank selector 61
．． 61b, refresh address bank selector 62
A response signal ACK is generated for each address driver 62a, 62b constituting the gate signal Go~1 million, the clock RFACK for the refresh address counter 5, the reset signal RFCR for the refresh request counter 3, and the bus interface 2. Then, an address driver 62 configuring the refresh address bank selector 62 receives the refresh request signal RFRQ from the refresh request counter 3.
a, 62b is selected, and DRAM8 is selected by the RAS signal.
Refresh each bank.

Bank selector 7 receives lowest address signal and upper address signal A1 . A18 is input, one of banks BO-83 of DRAM8 is selected by these signals, and CASO-C is input to the selected bank.
Send AS3.

The operation of the apparatus configured as described above will now be described with reference to the time charts of FIGS. 3 and 4.

The operation can be divided into two types: when DRAMs are refreshed alternately, and when all DRAMs are forcibly refreshed at the same time.

First, the former operation will be explained. In the time chart of FIG. 3, an example is taken where DRAM is selected continuously. Also, in the address bus, banks B0, 131. B2. ... is selected, part 4
CAS0, CASl for each bank.

CAS2. ... is input. When bank 80 or B2 is selected and accessed, address driver 6
1b and 628 are enabled, selector 6, 'O
The date/column address RCAO-7, which is the output of counter 5, is input to banks BO and 82 by driver 61b, and the refresh address RFAO-6, which is the output of counter 5, is input to banks B1 and 83 by driver 62a.

The RAS signal is sent to all DRAMs when a DRAM is selected.
Therefore, D of bank BO or B2
When RΔ-share is accessed, banks B1 and 83 are refreshed at the same time. Similarly, D of bank B1 or B3
When R'AM is accessed, banks BO and 82 are refreshed at the same time. The refresh addresses are banks So, B2 and bank 81. When the B3 DRAM is refreshed alternately, it is updated by the refresh address counter clock RFΔCK. At the same time, refresh request counter 3 is reset.

Next, the operation time chart shown in FIG. 4 will be explained. This applies when no DRAM is selected, or when A1 remains "0" or "1" on the address bus. In either case, alternate refresh of [)RAM is not performed, After a certain period of time, the refresh request counter 3 outputs the 'request signal RFRQ, and a forced refresh cycle begins.Address drivers 61a and 61b are disabled, and address driver 6
2a and 62b become valid, and the addresses input to the DRAM become the refresh addresses RFAO-6, which are the outputs of the counter 5, for all banks 80-83. Therefore, all DRAMs are refreshed simultaneously by the RAS signal. Also, similar to the former, updating of the reflexico address counter 5 and refresh request counter 3
will be reset.

In the above embodiment, the DRAM is accessed and refreshed at the same time, but if there is no access to the DRAM, the refresh request counter 3 forcibly refreshes the DRAM. In order to reduce the frequency of this forced refresh, the following method may be used.

The system address bus is activated, the address on the bus is determined, and the IC outputs the RAS signal to the DRAM.

Therefore, one bank is refreshed by the lowest address lO17, 11111 even if the DRAM is not actually selected. At this point, the addresses on the bus are input to the other banks, but the CAS signal is not input, so the data output of the DRAM is at high impedance, and the contents of the DRAM will not be rewritten by mistake.

Therefore, unless the lowest address remains in the state of "O゛' or 1" for a certain period of time or more, DRAM refresh is performed alternately in bank units, which eliminates the time remaining due to competition with forced refresh. Access can be made faster.

The operational features of the device according to the present invention are summarized as follows.

(a) By dividing the DRAM into two banks, switching the address on the system address bus between row/column, and having a selector in each bank to switch the refresh address, one bank can have the system address and another. The point is that the fresh address is input to the other bank, and normal access and refresh are performed on different banks at the same time.

(b) As one means of dividing the bank, the lowest address of the system is lQI+.

By using a binary state of 1”, the above (a)
The operation of the term is often performed by changing banks,
As a result, normal access and refresh will be performed alternately.

(C) After alternately refreshing the two banks, the occurrence of refresh requests can be suppressed by resetting the refresh-L request counter.

(Effects of the Invention) As explained above, according to the present invention, the frequency of forced refresh is reduced, and there is no conflict with refresh when accessing DRAM, so that access is improved.
D The time between i is reduced and the system speed is increased.
A RAM control device can be realized.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing an example of a device according to the present invention, FIG. 2 is a configuration block diagram showing more details thereof, FIGS. 3 and 4 are time charts for explaining its operation, 5 and 6 are time charts showing basic operation modes of the DRAM, and FIG. 7 is a configuration block diagram showing an example of a conventional device. 1... M'PLI (? Microprocessing unit) 2... Bus interface section 3... Refresh request counter 4... Timing generation section 5... Refresh address counter 61... Row column address bank fin Lid 62...Refresh address Bank selector 7...Bank selector 8...DRAM (dynamic random access memory) B0, B1...Bank

Claims (1)

[Claims] a microprocessing unit, coupled to this microprocessing unit, two banks B0, B1
A dynamic random access memory consisting of a dynamic random access memory, the lowest address on the address bus coupled to the microprocessing unit is "0", and a row column address is selected and sent to the banks B0 and B1 by "1". The bank selector selects the refresh address from the refresh address counter from the banks B1 and B depending on whether the lowest address is "0" or "1".
a refresh address bank selector that sends a refresh address to bank 0; means for resetting a refresh request counter that counts up the refresh address counter and issues a refresh request when both banks B0 and B1 are refreshed; a timing generator and a normal timing generator including means for turning off a column address selector, turning on both of the refresh address bank selectors to refresh the banks B0 and B1 at the same time, counting up the refresh address counter, and resetting the refresh request counter; a bank selector that selects one of the banks using the lowest address and the highest address on the address bus when accessing the memory, and sends a column address strobe signal to the bank. Control device.