JPH03237681A - Dynamic memory device - Google Patents

Abstract

PURPOSE:To improve stability and reliability by setting a central processing unit to a wait state for prescribed time at the time of a refresh operation and time-divisionally refreshing a dynamic memory means in terms of memory capacity during that time. CONSTITUTION:A CPU control circuit 40 detecting that CPU 23 outputs a refresh signal and setting CPU 23 in the wait state for prescribed time is added. Consequently, a memory control circuit 44 can time-divisionally refresh-operates respective banks 211-21n of a memory 21. Thus, the dynamic memory device can suppress the occurrence of noise and can improve stability and reliability by hourly distributing the generation of a refresh current.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic memory device using dynamic random access memory elements.

[Prior Art] Conventionally, this type of dynamic memory device has a plurality of dynamic random access memory devices as shown in Fig. 3.
Memory (hereinafter abbreviated as DRAM).

) memory 21 including n (n is a positive integer) banks 211 to 21n configured with elements; and a memory control circuit 2.
2, a central processing unit (hereinafter abbreviated as CPU) 23, and a memory address multiplexer 24.

Each bank 211-21n of the memory 21 is connected to a signal line 251-21n.
It is connected to the memory control circuit 22 via 25n,
A row address strobe signal (hereinafter abbreviated as RAS signal) and a column address strobe signal (
Hereinafter, it will be abbreviated as CAS signal. ) and a write enable signal (hereinafter abbreviated as WE multiplication signal) are input.

Further, each bank 211 to 2in of the memory 21 is connected to the CPU 23 via an address bus 26 and a memory address multiplexer 24, and an address signal from the CPU 23 is inputted through the memory address multiplexer 24.

The memory address multiplexer 24 is connected to the memory control circuit 22, and a multiplexer timing signal 27 for time-divisionally switching the address from the CPU 23 into a row address and a column address is input from the memory control circuit 22. be done.

The memory control circuit 22 is connected to a CPU 23, and receives signals from the CPU 23 indicating its operation, that is, a refresh signal 28 indicating a memory refresh operation, a read signal 29 indicating a memory read operation, and a write signal indicating a memory write operation. 30 will be done manually.

In the dynamic memory device configured as described above, during the refresh operation, the CPU 23 operates as shown in FIG. 4(a).
As shown in FIG. 2, the refresh signal 28, which is always at a high level, is output at a low level for a certain period of time. While the refresh signal 28 is at a low level, the memory control circuit 22 sends R, which is always at a high level, to each bank 211 to 2in.
ASI to RASn signals (shown in Fig. 4(b) to (e))
to low level at the same time. By this, all DRAM
A device refresh operation is performed.

[Problems to be Solved by the Invention] However, the above dynamic memory device
It is not possible to change the output time of the 23 refresh signals, and during the refresh operation, the DRAM elements of each bank are refreshed all at once, which causes a large refresh current to flow, which generates noise and impairs the stability of the device. There are drawbacks that reduce performance and reliability. Furthermore, it is necessary to set a large power supply capacity in accordance with the maximum power consumption, and to add a bypass capacitor on the power supply side to remove noise, which increases the price of the device.

The present invention has been made to solve the above-mentioned problems, and during a refresh operation, the central processing unit is placed in a wait state for a predetermined period of time, and during that time, the dynamic memory means is time-divisionally refreshed in units of memory capacity. The object of the present invention is to suppress the generation of noise by temporally distributing the generation of refresh current, improve stability and reliability, and provide an inexpensive dynamic memory device.

[Means for Solving the Problems] In order to achieve this object, the dynamic memory device of the present invention includes a dynamic memory means in which a storage area is divided into a plurality of memory capacity units, and a data storage device for the dynamic memory means. a central processing unit that reads and writes data and outputs a refresh signal for a certain period of time;
a control circuit that detects that the central processing unit outputs a refresh signal and puts the central processing unit in a wait state for a predetermined time; and a control circuit that time-divides the dynamic memory means in units of memory capacity while the refresh signal is output. and a memory control circuit that performs a refresh operation.

[Function] The dynamic memory device of the present invention having the above configuration has the following features:
A central processing unit outputs a refresh signal. The control circuit that detects this puts the central processing unit in a wait state for a predetermined period of time. During this time, a refresh signal is continuously output from the central processing unit, and the memory control circuit performs a refresh operation on the dynamic memory means in a time-division manner in units of memory capacity.

[Example] Hereinafter, an example embodying the present invention will be described with reference to the first construction drawing to FIG. 2.

Note that the same members as those in the conventional dynamic memory device shown in FIG. 3 are given the same numbers, and detailed explanation thereof will be omitted.

The dynamic memory device according to the present invention includes a CPU 23
The terminal RE outputting the refresh signal 28 and the CPU 2
A CPU control circuit 40 connected between wait terminal WA of No. 3 is added to the conventional dynamic memory device. When this CPU control subcircuit 40 detects that the refresh signal 28 of the CPU 23 has changed to a low level, it outputs a wait signal 42 for a predetermined period of time. Furthermore, the CPU
The time period during which the control circuit 40 outputs the wait signal 42 is long enough to complete the refresh operation of each bank 211 to 2 inches of the memory 21.

Further, a memory control circuit 44 is provided, and this memory control circuit 44 is connected to the memory address multiplexer 24 to switch the address from the CPU 23 into a row address and a column address in a time-sharing manner. multiplexer timing signal 27 to memory address multiplexer 24. The memory control circuit 44 is also connected to the CPU 23.
3, signals indicating the operations, that is, a refresh signal 28 indicating a memory refresh operation, a read signal 29 indicating a memory read operation, and a write signal 30 indicating a memory write operation are input manually.

Further, the memory control circuit 44 is connected to each bank 211 to 21n of the memory 21 via signal lines 451 to 45n, and the CAS
Outputs the signal and the WE multiplied signal.

Then, when the refresh signal 28 is output from the CPU 23, the memory control circuit 44 connects the signal lines 451 to 45
The RAS signal is sent to each bank 211 to 211 of the memory 21 through n.
21n sequentially.

Note that the memory 21 allows the dynamic memory means to
The U control circuit 40 constitutes a control circuit.

The operation of the dynamic memory device configured as described above during memory refresh will be explained with reference to FIG.

Normally, the CPU 23 outputs the refresh signal 28 to the memory control circuit 44 and the memory control circuit 44 outputs the refresh signal 28 to each bank 211 to 211 of the memory 21 through the signal lines 451 to 45n.
The RASI signal to RASn signal outputted to 21n are at high level, and the wait signal 42 outputted from CPU control circuit 40 to CPU 23 is at low level.

During memory refresh operation, the CPU 23 operates as shown in FIG. 2(a).
The refresh signal 28 is output at low level as shown in FIG. When the CPU control circuit 40 detects that the refresh signal 28 has changed to a low level, it outputs a wait signal 42 at a high level for a predetermined period of time to the CPU 23, as shown in FIG. 2(b). As a result, the CPU 23 enters a wait state and continues to output the refresh signal 28 at a low level.

Furthermore, when the refresh signal 28 changes to low level, the memory control circuit 44 first changes only the RASI signal outputted to the bank 211 of the memory 21 through the signal line 451 to low level, as shown in FIG. 2(C). change. R.A.
By changing the SI signal to low level, only the DRAM elements in bank 211 are refreshed. Next, the memory control circuit 44 changes the RASI signal from low level to high level, and then connects the signal line 452 as shown in FIG. 2(d).
Only the RAS2 signal output to the bank 212 through the RAS2 signal is changed to low level. By changing the RAS2 signal to low level, only the DRAM elements in bank 212 are refreshed. Next, the memory control circuit 44 changes the RAS2 signal from low level to high level, and then changes the RAS2 signal from low level to high level, and then
), only the RAS3 signal output to the bank 213 through the signal line 453 is changed to low level, and only the DRAM elements of the bank 213 are refreshed. Thereafter, the memory control circuit 44 controls each RAS4 signal to RASn
The signal (shown in FIG. 2(f)) is sequentially and temporally changed to a low level to sequentially refresh the DRAM elements of each bank 214-21n.

As shown in FIG. 2(b), the CPU control circuit 40 holds the wait signal 42 at a high level until the refresh of each bank 211 to 21n is completed at 5, and the refresh operation of all banks 211 to 21n is completed. After the completion of the process, the wait signal 42 is changed to low level. When this wait signal 42 becomes low level, the wait state of the CPU 23 is released, and then the refresh signal 28 is changed to high level to complete the refresh operation.

In this way, the dynamic memory device has CPU2
3 outputs a refresh signal, and the CPU
23 in a wait state for a predetermined period of time.
By adding , the memory control circuit 44 can control the memory 2
Each of the banks 211 to 2in of 1 can be refreshed in a time-division manner. As a result, the dynamic memory device can suppress the generation of noise by temporally distributing the generation of the refresh current, thereby improving stability and reliability, and can also be made inexpensive.

[Effects of the Invention] As is clear from the detailed description above, the present invention puts the central processing unit in a wait state for a predetermined period of time during a refresh operation, and during that time, refreshes the dynamic memory means in units of memory capacity in a time-sharing manner. By dispersing the generation of refresh current over time, it is possible to suppress the generation of noise, improve stability and reliability, and provide an inexpensive dynamic memory device.

[Brief explanation of drawings]

1 to 2 show an embodiment embodying the present invention. FIG. 1 is a block diagram of this embodiment, and FIG. 2 is a timing chart during a refresh operation of this embodiment. 3 to 4 show an example of the prior art, in which FIG. 3 is a block diagram and FIG. 4 is a timing chart during a refresh operation. In the figure, 21 is a memory (dynamic memory means), 23
28 is a refresh signal, 40 is a CPU control circuit (control circuit), and 44 is a memory control circuit.

Claims (1)

[Claims] 1. Dynamic memory means in which a storage area is divided into a plurality of memory capacity units, and a central processing unit that reads and writes data to the dynamic memory means and outputs a refresh signal for a certain period of time. a control circuit that detects that the central processing unit outputs a refresh signal and puts the central processing unit in a wait state for a predetermined period of time; and a control circuit that controls the dynamic memory means in units of memory capacity while the refresh signal is output. A dynamic memory device comprising a memory control circuit that performs a time-divisional refresh operation.