JPH04364295A - Dynamic ram control circuit device - Google Patents

Abstract

PURPOSE:To hardly generate a malfunction of a memory by providing a delay means which the refresh signal is inputted and each refresh signal corresponding to each memory bank is delayed and it is supplied to each memory bank. CONSTITUTION:Refresh signals, RAS, CAS are generated with a refresh timing generator part 11 with a refresh request from a refresh timer. With each RAS selector 9 a column address.strobe signal and the RAS signal are outputted to RAS 0-RAS 7 with each RAS selector 9 and the RAS signal is outputted to each RAS output by keeping a space of a delayed time by an amount set with a circuit 12. Hence a time shift at a peak current of a power source current generating at each bank with the RAS signal is generated and a peak current of a power source current generating in the total system is distributed and the peak value becomes not high and then the ratio of a malfunction of the memory at a refresh time can be suppressed lower.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM control circuit device for controlling the operation of a DRAM when a DRAM is used.

0002

2. Description of the Related Art FIG. 4 is a block diagram showing the configuration of a DRAM controller (control circuit device) in a system configuration when a DRAM is used as a general memory element, and includes a microprocessor unit (hereinafter referred to as MPU) 6, The MPU 6 and the DRAM 8 are connected to each other via a data buffer 7 via a data bus. DRA
The M controller mainly consists of the following five blocks. That is, 1 is an address multiplex section, 2 is a refresh timer section, 3 is a refresh address counter section, 4 is an arbiter section, and 5 is a timing generator section. The roles of each of the above blocks will be explained below.

[0003] In the above configuration, the address multiplex unit 1 receives the input of the row address and column address in a time-sharing manner in the DRAM 8, so the address multiplex unit 1 switches the memory address from the MPU 6 into the row address and the column address.
Responsible for multiplex functions. Refresh timer 2 also performs a timer function to refresh the DRAM 8 at regular intervals, and refresh timer 2 is the most commonly used one at present.
In an M-bit DRAM, 512 addresses are refreshed in 8ms. Further, the refresh address counter 3 functions as a counter for providing a refresh address, and since 512 addresses are required for a 1M bit DRAM, the refresh address counter 3 has a 9-bit counter configuration. For example, /RAS-only refresh requires the refresh address to be supplied externally, so this counter function is necessary. However, DRAMs of 256K bits or more have this refresh address counter built-in, and can also be used. When using this built-in counter, perform /CAS before /RAS refresh. Naturally, when this refresh method is used, a refresh address counter is not required in the DRAM controller.

Furthermore, when a memory access request from the MPU 6 and a refresh request from the refresh timer 2 conflict, the arbiter 4 determines which request should be given priority. Also timing generator 5
functions to generate row address strobe signal /RAS, column address strobe signal /CAS, and write signal /W so as to satisfy the timing required by DRAM 8 at each time of memory access or refresh.

DRAM is static RAM (hereinafter referred to as S
Because it is cheaper than RAM (RAM), it is often used in systems that require a large memory capacity. For example, in an MPU with a data bus width of 16 bits, a 1M bit D
If you use a RAM ×1 configuration, 16 DRA
M is required, and the memory space is 2Mbytes.
(16Mbit). In order to access this 2 Mbyte memory, the address space is 2
20 (A0 to A19) are required. In contrast, general M
PU address space is even larger 223 (A0 to A22)
To some extent. If all of this address space is allocated to memory, the memory space corresponds to 16 Mbytes.

FIG. 5 is a block diagram showing the system configuration in this case, and one block of 16 DRAMs corresponds to 2 Mbytes. Since there are 8 blocks in total, the memory space is 16 Mbytes in total. One group of blocks is called a bank. In other words, in this example system, there are 8 banks from 0 to 8. The DRAM controller section in this system uses 1M x 1 DRAM, so A0
The addresses of ~A19 are multiplexed. Also,
RAS output is set individually for eight banks (/RAS0 to /RAS
7), and is set to address A20~ by RAS selector 9.
A22 One of the three addresses /RA
The S output will be selected and a particular bank of memory will be accessed. Further, during refresh which is periodically performed by the refresh timer 2, the RAS selector 9 outputs the row address strobe signal RAS signal to /RAS0 to /RAS7 at the same time, so that all memories are refreshed at the same time.

By the way, since a DRAM is composed of a transistor and a capacitor, the power supply current during operation is a steep transient current due to charging and discharging of the capacitor. FIG. 6 shows the waveform of the power supply current ICC during operation. As shown in this figure, especially when /RAS becomes "L", a transient current of about 100 mA flows. Considering the system shown in FIG. 5, 16 DRAMs are accessed simultaneously during normal read/write, so the transient current flowing through the entire system is even larger.

[0008] In addition to normal read/write, this transient current also flows during refreshing. In other words, when multiple banks are used to take up a large amount of memory space, as in the system example shown in the figure, all memories are refreshed at the same time during refresh, so as shown in Figure 7, even more transient current (ICC ( total)) will be lost.

[0009]

[Problem to be solved by the invention] Conventional dynamic R
The AM control circuit device is configured as described above, and according to FIG. 6, approximately 100 mA is generated in a rise time of approximately 50 ns during read/write and also during refresh.
A transient current is flowing, and this current peak causes a
0MHZ high frequency power supply noise is generated. The spike voltage on the power line caused by this power supply noise is

0
010]

[Math 1]

It is expressed as: This spike voltage causes the power supply voltage to fluctuate sharply, causing a problem in that the memory malfunctions. Particularly during refresh, the peak value of the transient current becomes very high, so this spike voltage value also becomes very large, which tends to cause malfunctions of the memory.

The present invention was made in order to solve the above-mentioned problems, and provides a dynamic RAM control circuit device that can reduce transient power supply current particularly during refreshing and is less likely to generate high frequency power supply noise. The purpose is to obtain.

[0013]

[Means for solving the problems] DRAM according to the present invention
The controller circuit device is provided with a delay means for delaying each refresh signal corresponding to each memory bank, or independently outputs a refresh request signal corresponding to each memory bank from a refresh timer, and refreshes the memory of each bank. This is a time difference.

[0014]

[Operation] In the present invention, a delay means is provided to delay each refresh signal corresponding to each memory bank, and the refresh signal is supplied to each memory bank, and a time difference is provided for refreshing the memory of each bank. Since the refresh request signals corresponding to the refresh request signals are outputted independently so as not to overlap in time, the transient current of the power supply current that occurs during refresh is dispersed and reduced, and the generation of high-frequency power supply noise is suppressed.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a partial configuration diagram of a DRAM controller circuit device according to an embodiment of the present invention, which corresponds to the timing generator 5 and RAS selector section 9 shown in FIG. In the figure, 10 is a memory access timing generator section, which is a memory access timing generator section during read/write.
RAS and /CAS signals are generated. /RA selected by the upper addresses (three from A20 to A22 in the example)
S output (in the example, one from /RAS0 to /RAS7)
/RAS signal is output.

Reference numeral 11 denotes a refresh timing generator section, which generates /RAS and /CAS signals for refresh (/RAS only refresh or /CAS
Before/RAS refresh) is generated and all/RAS
A signal is output to the S output and /CAS output to refresh all memories at the same time. Reference numeral 12 denotes a delay circuit provided at a portion for outputting the /RAS signal generated during refresh to each /RAS output. Further, 13 is an address decoder which receives the above-mentioned upper addresses (three addresses A20 to A22) as input.

Next, the operation will be explained. FIG. 2 shows the RAS output during refresh in this circuit and the waveform of the power supply current at that time. In response to a refresh request from the refresh timer 2, the refresh timing generator section 11 generates /RAS and /CAS signals for refresh, and each RAS selector 9 generates /RAS0 to /RAS.
The row address strobe signal RAS signal is output to S7, but the delay circuit 12 outputs /RAS to each RAS output.
Since the S signal is output with a delay time interval set by the delay circuit 12, there is a time lag in the peak current of the power supply current generated in each bank due to the RAS signal, and the power supply generated in the total system is The peak currents of the currents are not multiplied but dispersed, and the peak value does not become high. Therefore, the peak current at this time is approximately the same as when accessing one memory bank, the spike voltage of power supply noise that occurs during refreshing is the same as when accessing memory, and the rate of memory malfunction during refreshing is approximately the same as when accessing one memory bank. can be kept low.

As described above, according to this embodiment, the delay circuit 12 is provided for the refresh /RAS and /CAS signals generated by the refresh timing generator section 11, and the delay circuit 12 sets the refresh signals to each RAS output. Since the output is maintained at a delay time interval equal to the delay time, there is a time lag in the peak current of the power supply current generated in each bank due to the RAS signal, and the peak current of the power supply current generated in the total system is dispersed. Therefore, the generation of spike voltages due to power supply noise can be suppressed.

In the above embodiment, the transient currents of the power supply currents are prevented from overlapping by giving a time difference to the /RAS signals output to each memory bank when refreshing is performed simultaneously in response to a refresh request by the refresh timer 2. As shown in FIG. 3, the refresh timer 2 is provided with refresh requests 0 to 7 for each bank, and the refresh timer 14 configured to generate refresh requests 0 to 7 separately is used to refresh each bank separately. A similar effect can also be obtained by executing the command separately.

[0020]

As described above, according to the DRAM controller circuit device according to the present invention, delay means for delaying each refresh signal corresponding to each memory bank is provided, and the delay means is provided to delay each refresh signal corresponding to each memory bank. By setting a time difference between refreshes, or by outputting refresh request signals corresponding to each memory bank from the refresh timer independently so that they do not overlap in time, the transient current of the power supply that occurs during refresh is dispersed. This has the effect that it is possible to obtain a highly reliable DRAM controller circuit device in which high-frequency power supply noise is less likely to occur and memory malfunctions are less likely to occur.

[Brief explanation of the drawing]

FIG. 1 is a partial block diagram of a DRAM controller circuit device according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing the operation of a DRAM controller circuit device according to an embodiment of the present invention.

FIG. 3 is a partial block diagram of a DRAM controller circuit device according to another embodiment of the present invention.

FIG. 4 is a block configuration diagram including a general DRAM controller.

FIG. 5 is a system configuration diagram including a general DRAM controller.

FIG. 6 is a waveform diagram of a power supply current during a transient state in a system equipped with a conventional DRAM controller.

FIG. 7 is a timing diagram showing the operation of a system including a conventional DRAM controller circuit device.

[Explanation of symbols]

1 Address multiplexer 2, 14 Refresh timer 4 Arbiter 5 Timing generator 6 MPU 8 DRAM 10 Address decoder 11 Refresh timing generator 12
delay circuit

Claims (2)

[Claims] [Claim 1] Controlling the operation of a plurality of memory banks,
A dynamic RAM controller circuit that includes a refresh timer that outputs a refresh request signal, and a refresh signal generation circuit that generates a refresh signal in response to the refresh request signal, and that simultaneously refreshes the plurality of memory banks using the refresh signal. 1. A dynamic RAM control circuit device, characterized in that the device comprises a delay means which takes the refresh signal as input, delays each refresh signal corresponding to each memory bank, and supplies the delayed refresh signal to each memory bank. 2. Controlling the operation of a plurality of memory banks;
A dynamic RAM controller circuit that includes a refresh timer that outputs a refresh request signal, and a refresh signal generation circuit that generates a refresh signal in response to the refresh request signal, and that simultaneously refreshes the plurality of memory banks using the refresh signal. A dynamic RAM control circuit device, wherein the refresh timer independently outputs a refresh request signal corresponding to each of the memory banks.