JPH0476886A - Memory - Google Patents

Abstract

PURPOSE:To simplify an outside circuit for controlling a memory, to save a mounting space, and to reduce a cost by changing an interface with the outside of a refresh control. CONSTITUTION:A memory 8 incorporates a refresh(Rf) timer 4. When a time out signal 16 is generated from this in a constant cycle, an Rf requesting circuit 5 generates an Rf requesting signal 17 to the outside. When an Rf permitting signal 13 is inputted from the outside, an RAS.CAS generating circuit 1 supplies an Rf starting signal 14 to an Rf address counter 2, and activates the Rf. Then, the Rf of a memory cell 3 is executed by a memory cell controlling signal 15. The timer 4 and the circuit 5 are reset by the signal 13, and turned to be in a state waiting for the next Rf signal 16. And also, the signal lines of an RAS 11 and a CAS 12 and the signal lines of the signals 17 and 13 are separat ed, and set as different pins, so that an only bus controlling circuit 9 is enough for the outside circuit for controlling the Rf. Thus, a simple circuit constitution can be realized by both the circuit 9 and an RAS.CAS controlling circuit 7, and the cost can be reduced.

Description

TECHNICAL FIELD The present invention relates to memory, and in particular to DRAM (Dynamic RAM), which is a memory that requires a refresh operation.
) regarding.

Prior Art A conventional DRAM includes an address decoder, a buffer, a memory cell array, and a circuit for generating RAS, CAS, and WRITE clocks. Therefore, in order to perform refresh, it is necessary to create special timing for the RAS and CAS signals for refresh in an external circuit.

In other words, in the conventional DRAM, in addition to the memory cell 3 that stores and holds data as shown in FIG.
A S (Row Address 5 trove) and CA S (Column Address 5 tr)
The RAS-CAS generating circuit 1 sends out a refresh start signal 14 in response to the refresh start signal 14, and the memory cell control signal 15 is sent out to the memory cell 3 in response to the refresh start signal 14 to perform refresh or refresh. The counter 2 is configured to include a counter 2.

However, it is necessary to refresh at a constant cycle depending on the data retention capacity of the memory cell 3. Therefore, as shown in FIG. 4, it is possible to provide a refresh timer 4 that sends out a timeout signal 16 at regular intervals, and a refresh request circuit 5 that sends out a refresh request signal 17 every time the timeout signal 16 occurs. It's common.

Furthermore, upon receiving the refresh request signal 17, the CPU 6
A hash control circuit 9 sends a hash hold request 20 to the CPU 6, receives a pass hold permission 19 from the CPU 6, and sends out a refresh permission signal 13, and a hash control circuit 9 sends a refresh timing signal 22 in response to a signal 21 from the refresh request circuit 5. It is necessary to provide a refresh timing generation circuit 10 for sending the data, and a RAS-CAS control circuit 7 for sending the RAS II and CAS 12 to the memory 8 in response to the control signal 18 from the CPU 6 and the refresh timing signal 22 from the refresh timing generation circuit 10. There is.

Conventional DRAMs that require an external circuit with such a configuration are
The interface with an external circuit that performs refresh control was realized by the timing of RAS, CAS, and address signals. Therefore, even in small-scale devices, external circuits for DRAM include a refresh timer for measuring refresh intervals, a refresh request circuit, a refresh timing generation circuit, and an RAS.
- It was necessary to provide a CAS control circuit and a HAS control circuit. Therefore, there is a drawback that the mounting space increases and furthermore, the cost increases.

Purpose of the Invention The present invention has been made to solve the above-mentioned conventional drawbacks, and its purpose is to reduce the mounting space for an external circuit for refresh control and further reduce costs. It is to provide memory.

Structure of the Invention A memory according to the present invention includes a memory cell that stores and holds predetermined data, a refresh request means that sends a refresh request to a host device at predetermined intervals, and a refresh request unit that sends a refresh request from the host device based on the refresh request. The present invention is characterized in that a refresh means for refreshing the memory cells in response to refresh permission is enclosed within one chip.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the internal structure of an embodiment of a memory according to the present invention, and parts equivalent to those in FIGS. 3 and 4 are designated by the same reference numerals.

In the figure, a memory 8 according to an embodiment of the present invention has a built-in refresh timer 4, and when a timeout signal 16 is generated at regular intervals, a refresh request circuit 5 sends a refresh request signal (REFRE) to the outside.
SHRQ) 17 is generated.

External refresh enable signal (REFRESHAK)
13, the RAS-CAS generating circuit 1 supplies a refresh start signal 14 to the refresh address counter 2 to activate refresh, and refreshes the memory cell 3 using the memory cell control signal 15.

The refresh timer 4 and the refresh request circuit 5 are reset by the refresh permission signal 13 and enter a state of waiting for the next refresh timeout signal 16.

FIG. 2 is a block diagram of an external circuit using the memory 8 of this embodiment. RASll and CA as shown
By separating the S12 signal line from the refresh request signal 17 and refresh permission signal 13 signal lines and making them separate pins, the bus control circuit 9 is the only external circuit required for refresh control. . Therefore, a simple circuit configuration can be realized in combination with the RAS-CAS regulation circuit 7.

As described in detail, the present invention simplifies the external circuit for memory control by changing the refresh control interface with the outside, thereby reducing costs by saving mounting space and reducing the number of parts. It has the effect of being able to

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the internal configuration of a memory according to an embodiment of the present invention, FIG. 2 is a block diagram showing a connection state between the memory in FIG. 1 and an external circuit, and FIG. 3 is an internal configuration of a conventional memory. FIG. 4 is a block diagram showing the connection state between the memory in FIG. 3 and an external circuit. Explanation of symbols of main parts 1...RAS-CAS generation circuit 2...
Refresh address counter 3...Memory cell 4...Refresh timer 5...Refresh request circuit Applicant: NEC Corporation (1 other person)

Claims (1)

[Claims] (1) A memory cell that stores and holds predetermined data, a refresh request unit that sends a refresh request to a host device at predetermined intervals, and a refresh request unit that responds to a refresh permission sent from the host device based on the refresh request. A memory characterized in that a refresh means for refreshing the memory cells is enclosed within one chip.