JPH04337596A - Dynamic ram - Google Patents

Abstract

PURPOSE:To highten utilization efficiency by reducing the proportion of a refreshing time occupying all utilization time. CONSTITUTION:When a CBR refresh cycle is detected by a CBR detection circuit 5, a refresh address signal outputted from a refresh counter 7 and a refresh address signal outputted from an inverse circuit 8 are supplied to a word line decoder 2 in sequence and a refreshing is executed for two lines within one refreshing cycle.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a dynamic random access memory (RAM) in a semiconductor memory device.
accessmemory. (hereinafter referred to as DRAM).

Since DRAM uses a capacitor as a storage element, it requires refresh operations a certain number of times within a certain period of time in order to retain data. During this refresh operation, read and write operations, which are the original uses of the DRAM, cannot be performed. Therefore, from the point of view of usage efficiency, it is preferable that the ratio of the refresh time to the total usage time is small.

0003

2. Description of the Related Art Conventional DRAMs are configured to perform refresh operations in CBR (CAS-before-RAS) refresh cycles, RAS-only refresh cycles, and the like.

0004

[Problem to be solved by the invention] Such conventional DRAM
is configured and controlled so that one row can be refreshed during one refresh cycle. For this reason, the refresh time occupies a large proportion of the total usage time, posing a problem in terms of usage efficiency.

[0005] In view of this, the present invention provides a dynamic RA in which the ratio of refresh time to the total usage time can be reduced and the usage efficiency can be increased.
The purpose is to provide M.

[0006]

[Means for Solving the Problems] A DRAM according to the present invention includes a refresh cycle detecting means for detecting a refresh cycle from a certain signal supplied from the outside, and when the refresh cycle detecting means detects a refresh cycle. During one refresh cycle,
A row address signal generating means for outputting a row address signal so that a plurality of rows can be sequentially refreshed one by one is provided.

[0007]

According to the present invention, a plurality of rows can be refreshed during one refresh cycle, so that the ratio of refresh time to the total usage time can be reduced.

[0008]

[Embodiment] First, an embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention, and FIG. 2 is a time chart showing a refresh operation in an embodiment of the present invention. In FIG. 1, 1 is a memory cell array, and 2 is a memory cell array. The word line decoder 3 is a sense amplifier. The sense amplifier 3 is configured to output a sense operation completion signal S6 of H level as shown in FIG. 2h when the sense operation is completed.

Reference numeral 4 denotes a timing generation circuit which receives the RAS bar signal and outputs the basic signal S1. Specifically, in response to the RAS bar signal as shown in FIG.
It outputs a basic signal S1 as shown in c.

Further, 5 is a CBR detection circuit that detects a CBR refresh cycle from changes in the RAS bar signal and the CAS bar signal. Specifically, as shown in FIG. 2b, after the CAS bar signal becomes active, , Figure 2a
As shown in FIG. 2D, when the RAS bar signal becomes active, a CBR detection signal S2 as shown in FIG. 2D is output.

6 is also a timing generation circuit,
This timing generation circuit 6 generates a word line decoder activation signal S3 that activates the word line decoder 2, a sense amplifier activation signal S4 that activates the sense amplifier 3, and an address switching operation of an address switching circuit 9, which will be described later. It outputs an address switching signal S5 to be controlled. Specifically, upon receiving the basic signal S1 outputted from the timing generation circuit 4 and the CBR detection signal S2 outputted from the CBR detection circuit 5, the word line decoder is activated at the timing shown in FIG. 2e(x). A signal S3 and a sense amplifier activation signal S4 having timings as shown in FIG. 2f(x) are output. Further, as shown in FIG. 2h(x), when the first sense operation end signal S6 is supplied from the sense amplifier 3, the word line decoder 2 and the sense amplifier 3 are reset in sequence, and then the , outputs the address switching signal S5, and newly outputs the word line decoder activation signal S3 with the timing shown in FIG. 2e(y) and FIG. 2f(
A sense amplifier activation signal S4 having a timing as shown in y) is output. Then, as shown in Figure 2h(y),
When the second sense operation end signal S6 is output, the word line decoder 2, sense amplifier 3, and address switching circuit 9 are reset in this order.

Further, 7 is a refresh counter that outputs a row address signal indicating a row to be refreshed, that is, a refresh address signal; 8 is an inverting circuit that inverts the refresh address signal output from refresh counter 7; 9, 10; is an address switching circuit, and the address switching circuit 9 supplies the refresh address signal output from the refresh counter 7 to the address switching circuit 10 before the address switching signal S5 is supplied. If supplied, the refresh address signal output from the inverting circuit 8 is sent to the address switching circuit 1 instead of the refresh address signal output from the refresh counter 7.
0.

Further, before the CBR detection signal S2 is supplied from the CBR detection circuit 5, the address switching circuit 10 supplies the row address signal supplied from the outside to the word line decoder 2, and the CBR detection signal S2 is supplied to the word line decoder 2. In response to this, the refresh address signal supplied from the address switching circuit 9 is supplied to the word line decoder 2 instead of the row address signal supplied from the outside.

In this embodiment configured as described above, when the RAS bar signal and the CAS bar signal become active in the order of the CAS bar signal and the RAS bar signal, that is, the C
When it comes to the BR refresh cycle (see Figures 2a and b)
, the CBR detection circuit 5 detects this (see FIG. 2d). Then, the address switching circuit 10 supplies the refresh address signal output from the address switching circuit 9, that is, the refresh address signal output from the refresh counter 7, to the word line decoder 2 instead of the row address signal supplied from the outside. (see Figure 2i(x)).

Thereafter, the word line decoder 2 and sense amplifier 3 are activated in this order (see FIGS. 2e and 2f), and the refresh counter 7 is activated.
The row designated by the refresh address signal output from is refreshed. Then, when this refresh is completed (see FIG. 2h), the word line decoder 2 and sense amplifier 3 are
After being reset in this order, the address switching signal S5 is supplied to the address switching circuit 9 (see FIGS. 2e, f, and g), and instead of the refresh address signal output from the refresh counter 7, the refresh address signal S5 is output from the inverting circuit 8. The address signal is supplied to the word line decoder 2 (see FIG. 2i(y)), and then the word line decoder 2 and sense amplifier 3 are activated in this order (see FIG. 2e, f). ), the row specified by the refresh address signal output from the inverting circuit 8 is refreshed. Thereafter, the word line decoder 2, sense amplifier 3, and address switching circuit 9 are reset in sequence (see FIGS. 2e, 2f, and 2g).

[0017] In this way, in this embodiment, CBR
During the refresh cycle, unlike the conventional CBR refresh cycle, two rows can be refreshed during one refresh cycle.
It is possible to reduce the ratio of refresh time to the total usage time and improve its usage efficiency.

In the above embodiment, the second refresh is automatically performed based on the sense operation end signal S6 outputted from the sense amplifier 3, but instead of this, the second refresh is performed as shown in FIG. When a CBR refresh cycle is detected, the word line j is activated and the first refresh is performed, and then it is detected that the CAS bar signal becomes inactive while the RAS bar signal is active. Then activate word line k,
It may be configured to perform a second refresh operation. In the case of such a configuration, if the RAS bar signal is made inactive before the CAS bar signal, only one row will be refreshed during one refresh cycle as in the conventional CBR refresh.

Further, in the above embodiment, the refresh counter 7, the inverting circuit 8, and the address switching circuit 9
However, instead of this, a refresh counter having an addition or subtraction function may be provided. In this case, the refresh counter is supplied with an addition or subtraction clock from the timing generation circuit 6. Furthermore, in this case, it becomes possible to refresh three or more rows during one refresh cycle.

[0020]

According to the present invention, since a plurality of rows can be refreshed during one refresh cycle, the ratio of the refresh time to the total usage time can be reduced and the usage efficiency can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing main parts of an embodiment of the present invention.

FIG. 2 is a time chart showing a refresh operation in an embodiment of the present invention.

FIG. 3 is a time chart for explaining another embodiment of the present invention.

[Explanation of symbols]

1 Memory cell array 2 Word line decoder 3 Sense amplifier 4 Timing generation circuit 5 CBR detection circuit 6 Timing generation circuit 7 Refresh counter 8 Inversion circuit 9 Address switching circuit 10 Address switching circuit

Claims (1)

[Claims] 1. Refresh cycle detection means for detecting a refresh cycle from a constant signal supplied from the outside, and when the refresh cycle detection means detects a refresh cycle, a plurality of rows are detected during one refresh cycle. A dynamic RAM comprising: row address signal generating means for outputting a row address signal so that rows can be refreshed one by one.