JP2002133853A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the readout time of a semiconductor memory device which does not impose restrictions on sense amplifier order. SOLUTION: Serially inputted address signals are converted into parallel signals in an address buffer 21, a lower side address is supplied to a column decoder 33, and a higher side address is supplied to a low decoder 34. An LSB address is supplied to an LSB decoder 35. Signal lines CL and WL specified in a lower side address and a higher side address by the decoders 33 and 34 are activated before an LSB address A0 is supplied to the address buffer 21. Data when the LSB address A0 is '1' and '0' are outputted to a selection part 85 through a bit line transfer gate 41. In the selection part 85, any of data when the LSB address A0 is '1' and '0' are selected according to a selection signal LS0 or LS1 according to the LSB address A0 from the LSB decoder 35, and is outputted to a sense amplifier-cum-latch circuit 65.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device including a sense amplifier, and more particularly, to a semiconductor memory device which does not follow the sense amplifier rules and can shorten the read time.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device which does not have a sense amplifier discipline, for example,
There is a method described in JP-A-11-288594. That is, as shown in FIG. 5, an address signal is serially input in synchronization with a clock, an address signal excluding the least significant bit is output to a corresponding column decoder or row decoder, and an address excluding the least significant bit is output. After all the data of the memory cell specified by the signal is selected and the data is determined by the sense amplifier / latch circuits 61 and 62,
The selector 85 selects and outputs the result of determination in either the sense amplifier / latch circuit 61 or 62 in accordance with the value of the least significant bit, thereby reading out the data specified by the input address signal. I have.

[0003]

However, in the conventional semiconductor memory device described above, when the sense amplifier / latch circuits 61 and 62 operate, it is necessary to discharge the parasitic capacitance of the bit line. There is a problem that reading in the case of "0" is slower than reading in the case of "1".

In spite of the fact that one of the sense amplifier / latch circuits is actually selected and its output signal is output as a signal corresponding to a designated address signal,
There is a problem that a plurality of sense amplifier / latch circuits are required. SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional unsolved problem, and has as its object to provide a semiconductor memory device which does not conform to the sense amplifier rules and can shorten the read time. .

[0005]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell corresponding to an N-bit (N is a natural number) serially input address signal; A semiconductor memory device for outputting stored data, wherein M bits (M is 1 ≦ M ≦
A decoding unit for decoding an address signal of (N-1 natural number) and selecting all memory cells indicated by the address signal; and a memory unit indicated by an M-bit address signal selected by the decoding unit. Activating means for activating the activated bit line, and a bit line to be connected to a sense amplifier among the bit lines activated by the activating means based on an address signal other than the decoded M bits of the N-bit address signal. It is characterized by comprising a bit line selecting means for selecting, and a sense amplifier section for performing a data deciding operation on the bit line selected by the bit line selecting means and outputting a decided result.

Further, a semiconductor memory device according to claim 2 is
2. The semiconductor memory device according to claim 1, wherein said activating means activates said bit line prior to a selection operation by said bit line selecting means for a predetermined time. Further, in the semiconductor memory device according to the third aspect, in the semiconductor memory device according to the first aspect, the activating means may be configured so that the decoding unit includes the M.
After the input of the bit address signal is completed, and before the selection operation by the bit line selection means, at least before the processing time required for discharging the bit line accompanying the data determination operation of the sense amplifier, the bit line is activated. It is characterized by being made to let.

According to the first to third aspects of the present invention, N-bit address signals (A _{N-1 to} A _N ) which are natural numbers are used.
₀ ), M-bit (M is a natural number of 1 ≦ M ≦ N−1) address signals (A
_{N-1 to} A _NM ) and decodes this address signal (A
_{N-1 to} A _NM ) are all selected by the decoding unit. Then, the bit line connected to the memory cell designated by the selected M-bit address signal is activated, and activated based on the address signal excluding the decoded M bits of the N-bit address signals. Among the bit lines, the bit line of the address specified by the address signal other than the decoded M bits is selected as the bit line to be connected to the sense amplifier, and the data determination operation is performed in the sense amplifier unit for the selected bit line. Is performed, and the designated address signal (A _N−1 to
The data of A ₀ ) is read.

[0008] Here, the decoding unit operates in response to the address signal (A).
After active bit line by selecting all the memory cells specified by _N-1 ~A _NM), among the bit lines, the bit line specified by the address signal (A _NM ~A ₀₎ is selected The data is supplied to the sense amplifier unit, and the determining operation is performed. Therefore, even if a parasitic capacitance occurs on the bit line, the discharge of the bit line is started when the bit line is activated, so that the processing time required for the discharge can be reduced according to the activation timing. As a result, it is possible to realize a semiconductor memory device that does not follow the sense amplifier rules.

For example, if the bit line is activated by a predetermined time prior to the bit line selecting operation by the bit line selecting means, at least the bit line selecting operation by the bit line selecting means is already performed. Since the discharge has been started, it is possible to reduce the processing time required for the discharge in the determination operation in the sense amplifier unit.

In particular, after the input of the M-bit address signal in the decoding unit and before the start of the selection operation by the bit line selection means, at least before the processing time required for the discharge associated with the operation of the sense amplifier. By activating the bit lines, when the operation of determining the sense amplifier is performed, the discharge of the bit lines has been completed, so that the operation can be immediately shifted to the determination operation.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a semiconductor memory device according to the present invention. The address signal is
8 bits from A _{7 to} A ₀ , A ₇ is the most significant bit,
The A ₀ to the least significant bit, illustrating the A ₇ to A ₄ upper address, the A ₃ to A ₁ lower address, the A ₀ as the LSB address.

In this semiconductor memory device, a shift register 11 for serially inputting an address signal in synchronization with a clock signal, and a lower address (A _{3 to} A ₁ ) of the address signal from the shift register 11 are stored in a column. The address buffer 21 that outputs the higher-order address (A _{7 to} A ₄ ) to the row decoder 34, the LSB address (A ₀ or the inverted version of A ₀ ) to the LSB decoder 35, and the pre-sense signal A column decoder 33 for selecting the signal lines CL0 to CL7 corresponding to the lower address, a row decoder 34 for selecting the signal lines WL0 to WLm corresponding to the upper address according to a pre-sense signal, and a row decoder 34 according to the LSB address Signal line LS0 or L
An LSB decoder 35 for selecting any one of S1, a memory cell group 51 having a plurality of memory cells, a bit line transfer gate 41, and a bit line transfer gate according to the signal line LS0 or LS1 selected by the LSB decoder 35. Signal line BL corresponding to one word from gate 41
A set of 0 to BL7 and BL8 to BL corresponding to one word
A selector 85 for selecting any one of the 15 sets, and output signals SL0 to SL0 of the selector 85 according to the sense amplifier signal.
It has a sense amplifier / latch circuit 65 that performs a data determination operation on SL7, and an output buffer 71 that sequentially outputs output signals of the sense amplifier / latch circuit 65.

[0013] The LSB decoder 35, for example, consists of two AND circuits 35a and 35b, LSB address A ₀ from the address buffer 21 is inputted to one of the AND circuit, for example 35a, the inverted signal of the LSB address A ₀ and the other Is input to the AND circuit 35b. In addition, each A
The sense amplifier signal is input to the ND circuits 35a and 35b. When the sense amplifier signal and the LSB address A ₀ are both at the “H” level, the AND circuit 35a sets the LS1 signal, which is the output thereof, to the “H” level. select signal line LS1 outputs output, the aND circuit 35b, the LS0 signal which is the output signal when the inverted signal of the sense amplifier signal and the LSB address a ₀ are both "H" level as "H" level To select the signal line LS0.

The sense amplifier / latch circuit 65 comprises:
A sense amplifier corresponding to a word signal line, in this case 8
Each of the sense amplifiers amplifies each of the data with respect to the 8-bit output signal from the selection unit 85, and determines “1” or “0”. Latch the data. Then, the latched 8-bit parallel data is subjected to parallel / serial conversion and output to the output buffer 71.

The sense amplifier signal is a signal for activating the sense amplifier, and the sense amplifier / latch circuit 65 is activated when the sense amplifier signal is at "H" level. The pre-sense signal is a signal for bringing the memory cell into the same state as when reading out the stored data, although the sense amplifier is in an inactive state. Specifically, the pre-sense signal turns on the selection gate of the memory cell. State, a read voltage is applied to the gate of the memory cell, and the source of the memory cell is set to the GND level.

If the period of the semiconductor memory device is designed to operate at the falling edge of the clock signal and the cycle thereof is T, the pre-sense signal is the clock signal following the clock signal from which the LSB address was read. Becomes "H" level at most 3 / 2T period before the falling edge of LSB address, and the LSB address reading period T
Is set to the “L” level at the end of the operation. Further, the sense amplifier signal becomes “H” level at most T / 2 cycles before the falling of the clock signal following the clock signal from which the LSB address was read, and the LSB address reading cycle T ends. At this point, the level is set to the “L” level.

[0017] Therefore, as a trigger for the next rise of the example (the period of T clock signal) T / 2 from the falling edge of the clock signal supply the address signal A ₁ is started in the address buffer 21 delayed by a clock signal,
It is output as “H” level. Further, the rising of the clock signal one cycle (T) after the rising of the pre-sense signal triggers the sense amplifier signal to change to “H”.
The pre-sense signal and the sense amplifier signal are both reset to the “L” level at the next fall of the clock signal. The pre-sense signal and the sense amplifier signal are, for example, stored in the address buffer 21.
There Based on this generates a timing signal as a trigger for receiving the address signal A _1, is generated such as by generating a pre-sensing signal and the sense amplifier signals.

FIG. 2 shows a bit line transfer gate 41.
2 is a configuration diagram of a memory cell group 51. FIG. Now, assuming that any one of the signal lines WL0 to WLm is selected by the row decoder 34, and then any one of the signal lines CL0 to CL7 is selected by the column decoder 33, When the lower address A ₀ is “1”, the 8-bit data stored in the memory cell mat to be selected is selected by a multiplexer via, for example, the transfer gate B 3 constituting the corresponding bit line transfer gate 41. The 8-bit data stored in the memory cell mat to be selected when the lowest address A ₀ is “0” is transmitted to the selection unit 85 via, for example, the transfer gate B4. Has become.

Then, the selecting section 85 is provided with the LSB decoder 3
5 in accordance with the signal LS0 or LS1 from the LSB decoder 35, and selects one of a set of signals of one word consisting of 8 bits from the transfer gate B3 or B4 corresponding to the LS0 or LS1 selected by the LSB decoder 35; These are sequentially output to the sense amplifier / latch circuit 65. As shown in FIG. 1, the selector 85 connects the drain and the source of the P-type MOSFET 80 and the N-type MOSFET 81 to each other, and also connects the P-type MOSFET 82 and the N-type MOSFET
It is composed of two pairs of FETs 83 each having a drain and a source connected to each other. And these two FET pairs are
A plurality of sense amplifiers constituting the sense amplifier / latch circuit 65 are provided corresponding to the respective sense amplifiers.

As shown in the schematic diagram of FIG. 3, one of two FET pairs, for example, a P-type and an N-type MOS
The FET pair composed of the FETs 80 and 81 has an LSB address A when each signal line CL is selected among the transistors constituting the bit line transfer gate 41.
Each transistor corresponding to the same bit when ₀ is "0" is connected. That is, in FIG. 3, for example, when the signal line CL0 is selected by the column decoder 33, L when the signal line CL0 is selected by the column decoder 33 is set to L.
When the SB address A ₀ is “0”, for example, a signal corresponding to the first bit is output to the FET pair 81 and 82, and when the signal line CL 5 is selected by the column decoder 33, the signal line CL 5 is selected The signal corresponding to the first bit is output to the FET pair 81, 82.

Similarly, P-type and N-type MOSFETs 82,
The pair of FETs 83 includes each signal line C among the transistors forming the bit line transfer gate 41.
Each transistor corresponding to the same bit when the LSB address A ₀ when “L” is selected is “1” is connected. Then, the gate of the P-type MOSFET 80 and the N-type M
A signal LS0 from the AND circuit 35b is input to the gate of the OSFET 83, and a signal LS1 from the AND circuit 35a is input to the gate of the N-type MOSFET 81 and the gate of the P-type MOSFET 82. In operation, data from the signal line BL corresponding to the LSB address A ₀ is supplied to the sense amplifier / latch circuit 65.

Here, the address buffer 21, the column decoder 33, and the row decoder 34 correspond to a decoding unit, and the process of activating a memory cell in the column decoder 33 and the row decoder 34 according to a pre-sense signal corresponds to an activating means. The LSB decoder 35 and the selector 85 correspond to a bit line selector, and the sense amplifier / latch circuit 65 corresponds to a sense amplifier.

Next, the operation of the above embodiment will be described with reference to the timing chart of FIG. The upper address and the lower address of the 8-bit address signal are sequentially supplied as serial signals to the shift register 11 in synchronization with the clock signal, and when the address signals A _{7 to} A ₁ are supplied, the shift register 11 The serial address signal is converted into a parallel signal and sent to the address buffer 21.
LSB address A ₀ yet at this point has not been supplied.

The address buffer 21 outputs the lower addresses A _{3 to} A ₁ to the column decoder 33 and outputs the upper addresses A _{7 to} A ₄ to the row decoder 34.
The column decoder 33 and the row decoder 34 respectively decode the input addresses. At this point, since the pre-sense signal is at “L” level, the signal line CL
And WL are not selected, that is, the signal lines CL and W are not selected.
L maintains the “L” level.

When the address signal A ₁ is supplied from the shift register 11 to the address buffer 21 at the time point t ₁ , the pre-sense signal is output to the column decoder 33 and the row decoder 34 as an “H” level by using this as a trigger. . When the pre-sense signal goes to the “H” level, the column decoder 33 and the row decoder 34 select one of the signal lines CL0 to CL7 and WL0 to WLm corresponding to the decoded address signal and output this as the “H” level. Then, a read voltage is applied to the gate of the memory cell to control the source of the memory cell to the GND level.

Then, the memory cell group 5 corresponding to the signal line selected by the column decoder 33 and the row decoder 34
1 is output to the bit line. For example, when the storage data is zero, when the pre-sense signal becomes "H" level, the chip is precharged when the chip is enabled. Is performed, the bit line potential drops, and the discharge is performed.

On the other hand, when the LSB address A ₀ to the address buffer 21 is followed at time t ₂ to the address signal A ₁ is supplied, a sense amplifier signal as a trigger is "H"
Output as a level. The address buffer 21
Then, when the LSB address A ₀ is input from the shift register 11 following the address signal A ₁ ,
Output to the AND circuit 35a of the B decoder 35,
The inverted signal is output to the AND circuit 35b.

Therefore, in the LSB decoder 35, while the sense amplifier signal is at "H" level, the AND circuit 3
Either the signal LS0 or LS1 output from 5a or 35b is at the "H" level, and when the signal LS0 is at the "H" level, the selector 85 selects the bit lines BL0-B.
L7 is selected and its output is output to the sense amplifier / latch circuit 65. At this time, since the sense amplifier signal is at the "H" level, the data is determined and the result is output via the output buffer 71. Output.

On the other hand, when signal LS1 is at "H" level, bit lines BL8-BL15 are selected by selector 85 and their outputs are output to sense amplifier / latch circuit 65, and the sense amplifier signal is at "H" level. Then, the determination operation is performed in the sense amplifier / latch circuit 65, and the result is output via the output buffer 71. Here, as shown in the schematic diagram of FIG. 3, the parasitic capacitances CB1 and CB2 are generated in the bit line. However, before the sense amplifier signal becomes “H” level and the sense amplifier 65 operates, the selection unit 85 Also, the bit line on the memory cell group 51 side has already been discharged. Therefore, when the sense amplifier 65 operates, it is not necessary to discharge the bit line parasitic capacitances CB1 and CB2.

Therefore, even when data "0" is read from the memory cell group 51, since the discharge has already been performed when the sense amplifier operates, the change of the node immediately before the sense amplifier is fast, and the read operation is performed. Can be performed promptly. Therefore, the reading time can be shortened accordingly. In addition, by the selection unit 65,
LSB address A ₀ is "1" bit line BL8~BL15 corresponding to the time is, and the corresponding Bittto line when LSB address A ₀ is "0" BL0-BL7
Is selected and then processed by the sense amplifier / latch circuit 65. Therefore, it is not necessary to provide two sets of the sense amplifier / latch circuit 65 as in the related art.

Further, since the read time of the sense amplifier can be shortened by the output timing of the pre-sense signal, a semiconductor memory device that does not follow the sense amplifier rules can be realized. In the above-described embodiment, an 8-bit address signal is
The case where 8-bit data is read has been described. However, the present invention is not limited to this, and can be applied to an address signal having an arbitrary number of bits.

In the above embodiment, the LSB
The data when the address A ₀ is “0” and the data when the address A ₀ is “1” are read in advance, and the LSB address A
Selector 8 based on whether ₀ is “1” or “0”
The case where either one is selected in 5 has been described, but the present invention is not limited to this. That is, based on the number of remaining bits excluding an arbitrary number of bits from the first serially input address signal, if the number of remaining bits is Y, 2 ^Y-1 selection units 85 are provided,
An address signal of an arbitrary number of bits is supplied to the address buffer 21.
At the time when it is supplied to the memory, the pre-sense signal is set to "H" level to select all the memory cells specified by the address signal, and the memory data is selected for each combination of the bit values of the remaining bits of the address signal. 85, and when all the remaining bits of the address signal are supplied to the address buffer 21, the sense amplifier signal is set to the “H” level and the selection unit 85 specified by the bit values of the remaining bits. Data may be supplied to the sense amplifier / latch circuit 65.

By doing so, the time from the start of the bit line discharge to the start of the processing by the sense amplifier can be extended, so that it is effective to adjust it according to the parasitic capacitance of the bit line. It is.

[0034]

As described above, according to the first aspect of the present invention,
According to the semiconductor memory device of the present invention, among the _N- bit address signals (A _{N-1 to} A ₀ ), the M-bit address signal (A _N-1
~ A _NM ) to decode this address signal (A _N-1
.. A _NM ) to select and activate all the memory cells, and among them, select the bit line of the address specified by the remaining address signal so that the data determination operation is performed in the sense amplifier section. Therefore, it is possible to realize a semiconductor memory device that does not conform to the sense amplifier rules.

In particular, if the activation of the bit line is performed a predetermined time before the operation of selecting the bit line by the bit line selecting means, at least at the time of performing the operation of selecting the bit line by the bit line selecting means, Since the discharge is performed, the processing time required for the discharge in the determination operation in the sense amplifier unit can be reduced.

Further, after the input of the M-bit address signal is completed in the decoding unit, and at least before the processing time required for the discharge associated with the operation of the sense amplifier before the start of the selection operation by the bit line selection means. By activating the bit line, the operation can be promptly shifted to the definite operation.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of the circuit configuration of FIG.

FIG. 3 is a schematic diagram for explaining a connection portion between a selection unit 85 and a bit line transfer gate 41 in FIG. 1;

FIG. 4 is a timing chart for explaining the operation of the present invention.

FIG. 5 is a block diagram of a conventional semiconductor memory device.

[Explanation of symbols]

 Reference Signs List 11 shift register 21 address buffer 33 column decoder 34 row decoder 35 LSB decoder 41 bit line transfer gate 51 memory cell group 65 sense amplifier / latch circuit 71 output buffer 85 selector

Claims (3)

[Claims] 1. A semiconductor memory device for outputting data stored in a memory cell corresponding to an N-bit (N is a natural number) address signal input serially, wherein the address signal is serially input first. A decoding unit that decodes an M-bit (M is a natural number satisfying 1 ≦ M ≦ N−1) address signal and selects all the memory cells indicated by the address signal; Activating means for activating a bit line connected to a memory cell designated by a bit address signal; and bits activated by the activating means based on an address signal other than the decoded M bits of the N-bit address signal. Bit line selecting means for selecting a bit line to be connected to the sense amplifier among the lines, and a bit line selected by the bit line selecting means. For a semiconductor memory device characterized by comprising a sense amplifier section, a for outputting the determined result perform data confirm operation. 2. The semiconductor memory device according to claim 1, wherein said activating means activates said bit line prior to a selection operation by said bit line selecting means for a predetermined time. 3. The method according to claim 1, wherein the activating means is configured to perform a bit line operation after the end of the input of the M-bit address signal in the decoding unit and at least in accordance with a data deciding operation of the sense amplifier than a selecting operation by the bit line selecting means. 2. The semiconductor memory device according to claim 1, wherein the bit line is activated before a processing time required for discharging the data.