JP3154865B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a high-speed access mode.

[0002]

2. Description of the Related Art In recent years, with the speeding-up of microprocessors and the like, there has been an increasing demand for semiconductor memory devices that operate at high speed. Therefore, while increasing the speed of ordinary random access, the access method is somewhat limited, but a semiconductor memory device having a high-speed read mode enabling higher-speed read has been conventionally developed (for example, B.I. ASHMORE et al. "A 20ns 1Mb CMOS
Burst Mode EPROM "(1989 IEEE International Solid-Sta
te Circuit Conference)).

The configuration of a conventional semiconductor memory device having such a high-speed read mode is changed to a mask ROM [read only].
[memory] is shown in FIG. 12 as an example.

In the mask ROM, a number of bit lines BL are formed in the vertical direction in the figure, and a number of row selection lines WL are formed in the horizontal direction in the figure so as to cross the bit lines BL. A transistor Q forming a memory cell is connected to each intersection of the bit line BL and the row selection line WL. A large number of row selection lines WL are signal lines in which only one of the row selection lines WL is selected by decoding upper bits of an input address signal to be at a high level. In the figure, one row selection line WLj and n + 1 bit lines BLi0 to BLin, BL
(i + 1) 0 to BL (i + 1) n and n + 1 transistors Qij0 to Qijn, Q
Only (i + 1) j0 to Q (i + 1) jn are shown.

Each transistor Q forming a memory cell
Are composed of N-channel MOSFETs, the drain terminals are connected to the corresponding bit lines BL, and the source terminals are grounded. The gate terminal of each transistor Q is connected to a corresponding row selection line WL. Therefore, each transistor Qijk arranged in the same row j,
The gate terminals of Q (i + 1) jk are connected to the same row selection line WLj, and the drain terminals of the transistors Qijk arranged in the same column i are connected to the same bit line BLik. However, k = 0 to n.

Each transistor Q forming the memory cell is formed such that the threshold voltage becomes the same as that of a normal enhancement type when the memory cell stores a logical state "0" in a semiconductor manufacturing process. When the logic state "1" is stored, the threshold voltage is formed to be a high voltage. Therefore, when the row selection line WL goes high, only the transistor Q connected to the row selection line WL that stores the logical state “0” is turned on, and the bit line connected to the transistor Q is turned on. The potential of BL gradually decreases. Also, the transistor Q connected to the row selection line WL and storing the logical state “1” remains OFF (normally OFF), and the potential of the bit line BL connected to the transistor Q gradually increases. .

The above-mentioned n + 1 lines constitute one set of bit lines BLi0.
To BLin are n through transistors QCSi0 to QCin.
It is connected to one end of +1 data lines DL0 to DLn. Also, the other sets of bit lines BL (i + 1) 0 to BL
(i + 1) nB and the like are also connected to one end side of the same (n + 1) data lines DL0 to DLn via transistors QCS (i + 1) 0 to QCS (i + 1) n and the like, respectively. Each transistor QCS
Each of them is composed of an N-channel MOSFET, and the gate terminal is connected to the column selection line CS. When the column selection line CS becomes high level, it is turned on. In addition, each of these transistors QCS has the same column selection line CS as each of n + 1 transistors.
It is connected to the. Therefore, each of the n + 1 transistors QCSi0 to QCsin shown in the drawing has one column terminal for the column selection line C.
Si, and transistors QCS (i + 1) 0 to QCS (i + 1) n
For each of these, each gate terminal is connected to another column selection line CSi + 1.
It is connected to the. These column select lines CS are signal lines which are high-level by decoding only the least significant bits of the lower bits of the input address signal to select any one column select line CS. It is.

The other ends of the (n + 1) data lines DL0 to DLn are connected to inputs of sense amplifier circuits SA0 to SAn, respectively. The sense amplifier circuits SA0 to SAn use the data line DL0 to generate a small potential change appearing on each bit line BL according to the storage state of the transistor Q forming the memory cell.
... DLn and differentially amplifies the same to determine the logical amplitude and output. Outputs of these sense amplifier circuits SA0 to SAn are connected to one common output buffer circuit OB via transistors QP0 to QPn, respectively. Transistor QP0 ~
Each of QPn is composed of an N-channel MOSFET, and its gate terminal is connected to each of data selection lines P0 to Pn. By decoding the least significant bits of the input address signal or the count value of the address counter inside the semiconductor memory device, only one of the data selection lines P0 to Pn is selected to select a high level. Signal line. And the output buffer circuit OB
Is a buffer circuit for transmitting data amplified and determined by any of the sense amplifier circuits SA as read data D from the semiconductor memory device via the transistor QP whose data selection line P has become high level and turned on. .

The operation of the mask ROM having the above configuration will be described with reference to FIG.

When the input address signal is determined at time t10, the first address signal obtained by removing the least significant bits of the input address signal is also determined, and the upper bits of the first address signal are decoded. As a result, for example, the row selection line WLj goes high. Then, the transistor Qij0 connected to the row selection line WLj
To Qijn, Q (i + 1) j0 to Q (i + 1) jn, etc., only those that store the logical state “0” are turned on, and the bit line BL
Of i0 to BLin, BL (i + 1) 0 to BL (i + 1) n, etc., only the potential of the connected transistor Q which is turned on gradually decreases, and the potential of the other bit lines BL Gradually rises. At the same time, by decoding the lower bits of the first address signal, for example, the column selection line C
Si goes high. Then, n + 1 transistors QCSi0 to QCsin connected to the column selection line CSi are turned on.
N, and only n + 1 bit lines BLi0 to BLin are connected to the data line D via these transistors QCSi0 to QCin.
L0 to DLn. Accordingly, the bit lines BLi0 to BLiB corresponding to the storage states of the transistors Qij0 to Qijn
Small changes in the potential of Lin are input to the sense amplifier circuits SA0 to SAn via the data lines DL0 to DLn, respectively.

The outputs of the sense amplifier circuits SA0 to SAn are almost completely determined at time t11 after a predetermined time has elapsed from time t10. Here, assuming that the data selection line P0 is already at the high level at this time t11 by decoding the second address signal, the data output from the sense amplifier circuit SA0 is at this time t11. O
Since it is sent to the output buffer circuit OB via the transistor QP0 which has become N, it is determined as read data D at the subsequent time t12 and sent out.

In the case of random access, the second address signal is constituted by the least significant bits of the input address signal. Therefore, in this case, an arbitrary data selection line P can be set to a high level by an input address signal, and data is read from an arbitrary memory cell with an access time TR from time t10 to time t12. Can be.

At time t12, the output buffer circuit O
All outputs of the other sense amplifier circuits SA not sent to B have already been determined. Therefore, in the case of the high-speed read mode, the second address signal is generated by, for example, an address signal generated by an address counter in the semiconductor memory device, and the second address signal is changed by a count operation at time t13. When the data is decoded, the data selection line P1 goes high and only the transistor QP1 is turned on. Then, the output of the sense amplifier circuit SA1 that has already been determined is immediately sent to the output buffer circuit OB, and at time t14 after a short access time TF has elapsed, the read data D is determined and sent out. Thereafter, when the transistors QP2 to QPn are sequentially turned ON by the counting operation of the address counter, the outputs of the sense amplifier circuits SA2 to SAn are determined as read data D from the output buffer circuit OB after the same access time TF has elapsed. They will be sent out sequentially. The high-speed read mode can be realized by configuring the second address signal with the least significant bits of the input address signal and changing only the least significant bits of the input address signal from outside.

As a result, in the case of random access or the first reading of data in the high-speed read mode, the sense amplifier circuit is not used until the read data D of the output buffer circuit OB is determined after the input address signal is determined. Although SA0 to SAn require a relatively long access time TR to determine data, when reading data from the second to the (n + 1) th data in the high-speed read mode, the read data D is sequentially and continuously reduced with the short access time TF. Can be sent to

[0015]

However, in spite of the fact that one sense amplifier circuit is sufficient to output 1-bit read data D, the above-mentioned conventional mask ROM is provided with a high-speed read mode. So n
+1 sense amplifier circuits SA0 to SAn are required.
In addition, the basic configuration of the sense amplifier circuit may be a simple configuration using one differential amplifier circuit 1 as shown in FIG. 10, but in a recent semiconductor memory device, as shown in FIG.
First, the data on the data line DL is divided into two differential amplifier circuits 2,
In step 3, differential amplification is performed to generate complementary signals.
Next, the sense amplifier circuit has a complicated two-stage configuration such that the complementary signal is differentially amplified by another differential amplifier circuit 4 to determine the data, so that the random access or high-speed read mode can be performed. , The access time TR at the time of outputting the first data is shortened. In order to shorten the access time TR in the above-described conventional mask ROM, all the (n + 1) sense amplifier circuits SA0 to SAn must have a complicated circuit configuration as shown in FIG.

Therefore, in the conventional semiconductor memory device, as the amount of data that can be continuously read in the high-speed read mode increases, the area on the chip occupied by the sense amplifier circuit increases. There has been a problem that the power consumed by the amplifier circuit also increases.

The present invention has been made in view of the above circumstances, and an object of the present invention is to simplify the entire circuit configuration of a sense amplifier circuit, so that the sense amplifier circuit occupies a chip. While reducing the area,
An object of the present invention is to provide a semiconductor memory device which can reduce power consumption.

[0018]

According to the semiconductor memory device of the present invention, a plurality of memory cells are simultaneously selected from a large number of memory cells based on a first address signal and stored in the selected plurality of memory cells. A semiconductor memory device for reading the output data to a plurality of data lines, each of the plurality of data lines being connected to one of the plurality of data lines, and amplifying data on a corresponding one of the plurality of data lines. A plurality of first sense amplifier circuits to be output; and a plurality of data lines connected to the plurality of data lines, selectively selecting only data on any one of the plurality of data lines based on a second address signal. And a second sense unit for amplifying the data selectively output by the data selection unit at a speed higher than the amplification speed of the plurality of first sense amplifier circuits and outputting the amplified data. And amplifier circuit includes a, the object is achieved.

Also, a control signal generating means for generating an output control signal based on the first address signal and the second address signal, and a plurality of control signal generating means based on the output control signal generated by the control signal generating means. Output data control means for selecting only one of each output of the first sense amplifier circuit and the output of the second sense amplifier circuit and outputting it to the output buffer circuit may be provided.

Further, the control signal generating means receives a first address signal, and detects an address change detection circuit for detecting a change in the first address signal. When a change is detected,
A timing signal generation circuit for generating a timing signal for causing the output data control means to select the output of the second sense amplifier circuit for a predetermined period, wherein the control signal generation means outputs the timing signal to an output control signal. May occur.

The control signal generating means may further include a signal generating circuit for generating a series of signals in which the second address signal is sequentially changed, and the control signal generating means controls the output of the series of signals. It may be generated as a signal.

[0022]

[0023]

The data read operation of the semiconductor memory device according to the present invention will be described with reference to the block diagram shown in FIG. When a plurality of memory cells are selected based on the first address signal and data is read out to a plurality of data lines, these data are respectively amplified by the first sense amplifier circuit. At this time, the data selection circuit connects any one of the plurality of data lines to the second sense amplifier circuit based on the second address signal, so that the data is read out to the data line. Data
At the same time, the signal is amplified at high speed by the second sense amplifier circuit. Therefore, the data read from the plurality of memory cells at the same time is first sent to the second sense amplifier circuit, determined and output first, and thereafter, the data sent to the first sense amplifier circuit is almost output. It is determined and output at the same time.

Therefore, the output data control circuit allows the output of the second sense amplifier circuit to be initially selected by the output control signal generated by the control signal generating means based on the first address signal and the second address signal. In this case, the data determined first by the second sense amplifier circuit can be quickly output first. Thereafter, if the outputs of the plurality of first sense amplifier circuits are sequentially selected by the output data control circuit, the data determined by the first sense amplifier circuit while the first data is being output is sequentially output to the output buffer. Output to

For example, when random access is performed by an externally input address signal, some bits (first address signal) of the input address signal are decoded to select a plurality of memory cells, and the remaining memory cells are selected. (Second address signal) and the data line is selected by the data selection circuit. Then, in the random access mode, the output data control circuit selects only the output of the second sense amplifier circuit. Then, only the target bit data that has been randomly accessed is determined at a high speed by the second sense amplifier circuit and output to the output buffer via the output data control circuit.

For example, in the case where continuous data is read at a high speed by an externally input address signal,
A part or all of the bits of the input address signal (first address signal) are decoded to select a plurality of memory cells, and the remaining bits or the initial value of the internally generated count value (second address signal) ) Is decoded and the data line is selected by the data selection circuit. And
An address change detection circuit detects a change in an input address signal (a portion corresponding to the first address signal), and a timing signal generation circuit generates a timing signal according to the detected change. By generating this timing signal as an output control signal by the control signal generation circuit, the output data control circuit can select only the output of the second sense amplifier circuit when the input address signal changes. Then, first, only the first data designated by the externally input address signal is determined at a high speed by the second sense amplifier circuit, and is quickly output via the output data control circuit. Thereafter, only the remaining bits of the input address signal are sequentially changed, or the internally generated count value is sequentially changed, and this changed value is generated as an output control signal, thereby selecting the output data control circuit. The switching is sequentially performed, and the data already determined by the first sense amplifier circuit can be sequentially output at a high speed.

As a result, the first data at the time of random access or in the high-speed read mode can be quickly read with the same access time as the conventional one by using the second sense amplifier circuit which operates at high speed. The first sense amplifier circuit completes the determination of the other data on the bit line while the second sense amplifier circuit is outputting the first data, so that the other data is quickly read following the first data. be able to. The first sense amplifier circuit includes:
Since other data may be determined while the first data is being output, it is not necessary to perform a high-speed operation, and a simple and small occupied circuit configuration can be achieved.

When the first address signal changes and data is read from a plurality of memory cells, the output control signal generated by the control signal generation circuit causes the output data control circuit to operate as described above. The output of the second sense amplifier circuit can be selected for a certain period.

In another aspect of the present invention, when data is read out to a plurality of data lines based on a first address signal, these data are respectively amplified by a first sense amplifier circuit. . Further, the outputs of these first sense amplifier circuits are connected to the second sense amplifier circuit by selecting only one of the outputs based on the second address signal. Then, by sequentially switching the second address signal, the data amplified by the first sense amplifier circuit is sequentially selected and
The signals are determined by the sense amplifier circuit and are sequentially output.

When a sense amplifier circuit has a two-stage configuration in order to amplify and determine data on a data line at a high speed, conventionally, it is necessary to provide a complicated sense amplifier circuit having the two-stage configuration for each data line. However, as described above, according to the present invention, the first stage of the sense amplifier circuit is constituted by the first sense amplifier circuit, and the second stage is constituted by the second sense amplifier circuit. The occupied area on the chip can be reduced by sharing the second sense amplifier circuit. Also, in the present invention, 2 in the high-speed read mode
It takes time for the data to be determined in the second sense amplifier circuit when outputting the data after the first data. However, the data after the second data is already output during the output of the first data. Since the determination is sufficiently performed by the amplifier circuit, the determination can be performed in a very short time by the second sense amplifier circuit.

In any case of the present invention,
In the case of a semiconductor memory device that outputs a plurality of bits of data at the same time, the above configuration can be provided for each output bit.

Further, the data selection circuit and the output data control circuit in each of the above-mentioned inventions can be constituted by a multiplexer that selects only one of a plurality of input lines and connects it to an output line. If the second address signal and the output control signal are signals for the data selection circuit and the output data control circuit to perform selection,
For signals that need to be decoded or decoded signals,
Any type of signal may be used.

[0033]

The present invention will be described below with reference to examples.

2 and 3 show one embodiment of the present invention. FIG. 2 is a block diagram showing a circuit configuration of a data reading section of a mask ROM, and FIG. 3 is an operation of the data reading section of FIG. FIG. Components having the same functions as those of the conventional example shown in FIG. 12 are denoted by the same reference numerals.

In the present embodiment, a mask ROM having a high-speed read mode will be described. It should be noted that other semiconductor memory devices other than the mask ROM differ only in the configuration of the memory cells, and the present invention can be similarly implemented.

In the mask ROM of this embodiment, the first address signal is obtained by removing the least significant bits of the input address signal input from the outside. By decoding the upper bits of the first address signal, any one of
One of the row selection lines WLj is selected and set to a high level, and by decoding the lower bits of the first address signal, one of the column selection lines CSi is selected and set to a high level. The configuration in which data is read from the transistors Qij0 to Qijn forming the memory cell to the bit lines BLi0 to BLin and sent to the (n + 1) data lines DL0 to DLn through the transistors QCSi0 to QCSin is the same as the conventional example shown in FIG. Is the same. If the input address signal is composed of bits A0 to A3, for example, bits A3 to A3 excluding the three least significant bits A0 to A2 can be used as the first address signal. Data is sent out to the (n = 7) data line DL.

The n + 1 data lines DL0 to DLn are
Each is connected to the input of the first sense amplifier circuits 1SA0 to 1SAn. First sense amplifier circuits 1SA0-1
SAn is composed of one differential amplifier circuit 1 as shown in FIG. The differential amplifier circuit 1 is an amplifier circuit that compares the potential of the data line DL with a reference potential and sets the output potential to a high level or a low level of a logical amplitude depending on which potential is higher. By setting the reference potential to an intermediate value between minute potential changes of the data line DL, this potential change can be determined and output at a high level or a low level. However, since the first sense amplifier circuits 1SA0 to 1SAn are constituted by one differential amplifier circuit 1, it takes a relatively long time to amplify and determine a minute potential change.

The n + 1 data lines DL0 to DL0
Ln is 1 via transistors QPA0 to QPAn, respectively.
Are connected to the inputs of the second sense amplifier circuits 2SA. Each of the transistors QPA0 to QPAn is an N-channel MOSFET, and has a first terminal connected to the gate terminal.
The data selection lines PA0 to PAn are connected. Each of the first data selection lines PA0 to PAn is a signal line that is set to a high level by selecting only one of the data selection lines PA by decoding the second address signal. When any one of the data selection lines PA goes high, the corresponding one of the transistors QPA is turned off.
N. The second address signal is an address signal including the least significant bits of the input address signal. n = 7
FIG. 4 shows the second address signals (A0 to A2) and the signals on the first data selection lines (PA0 to PA7) as an example in the case of (1). However, in the case of the high-speed read mode, any one of the first data selection lines PA,
For example, the address signal may be such that only the first data selection line PA0 is at a high level.

The second sense amplifier circuit 2SA is the same as that shown in FIG.
1 has a two-stage configuration including three differential amplifier circuits 2 to 4. First two differential amplifier circuits 2, 3
Have the same configuration as the differential amplifier circuit 1 shown in FIG. 10, compare the potential of the data line DL with the reference potential, and change the output potential to the high level or the low level of the logic amplitude depending on which potential is higher. It is designed to be level.
However, these differential amplifier circuits 2 and 3 are connected to the data line DL
And the reference potential are input in opposite directions, so that the output potentials are complementary to each other. The second-stage differential amplifier circuit 4 is a circuit in which the polarities of the transistors of the differential amplifier circuit 1 shown in FIG. This is an amplifier circuit that compares different signals and sets the output potential to a high level or a low level of a logic amplitude depending on which potential is higher. Therefore, when a minute change in the potential of the data line DL is amplified by the first-stage differential amplifier circuits 2 and 3 and output as a complementary signal,
The second-stage differential amplifier circuit 4 compares the signals whose difference is increased by the complementation, and determines the logic amplitude of the output potential at high speed before the outputs of the first-stage differential amplifier circuits 2 and 3 are determined. can do. For this purpose, the second sense amplifier circuit 2SA is connected to the first sense amplifier circuits 1SA0 to 1S.
Compared with An, a minute potential change on the data line DL can be determined and output in a shorter time.

The respective outputs of the second sense amplifier circuit 2SA and the first sense amplifier circuits 1SA0 to 1SAn are connected to a common 1 through transistors QPB-1 and QPB0 to QPBn, respectively.
Are connected to the output buffer circuits OB. Each of the transistors QPB-1, QPB0 to QPBn is composed of an N-channel MOSFET, and the second data selection lines PB-1, PB0 to PBn are respectively connected to the gate terminals. Second
The data selection line PB is a signal line in which only one of the data selection lines PB is selected to be at a high level by decoding the output control signal. FIG. 5 shows a series of signals obtained by sequentially changing the second address signal and signals on the second data selection lines (PB-1, PB0 to PB7) in the case where n = 7. The output buffer circuit OB outputs the data that has been amplified and determined by any of the second sense amplifier circuit 2SA or the first sense amplifier circuits 1SA0 to 1SAn via the transistor QPB whose data selection line PB has become high level and turned on. This is a buffer circuit for transmitting read data D from the semiconductor memory device.

The output control signal is a signal generated by a control signal generation circuit in the semiconductor memory device. The control signal generating circuit detects the change of the input address signal and generates a detection signal (ATD signal), and selects the second data selection line PB-1 for a certain period based on the ATD signal. And a timing signal generating circuit for generating a timing signal therefor. Specific examples of these circuits are shown in FIGS. For example, A3 to An except for the least significant bits of the input address signal.
Is the first address signal. A
When at least one of Ak from 3 to An changes, the signal φAk changes to high level for a short period of time, and the ATD signal indicating the change of the input address signal changes to high level for a short period of time. Based on the ATD signal output from the address change detection circuit, a timing signal generation circuit as illustrated in FIG.
A timing signal for selecting the data selection line PB-1 can be generated. Thereafter, the control signal generation circuit outputs the least significant bits (for example, A0) of the input address signal.
A2) are sequentially generated as output control signals. Such an output control signal generating circuit can be constituted by a multiplexer that selects only one of a plurality of input lines and connects to the output line.

It should be noted that the control signal generating circuit can also generate an output control signal such that only the second data selection line PB-1 is always at the high level during random access.
In the case of the high-speed read mode, the second
After the data selection line PB-1 has been at a high level for a certain period,
An address signal in which the second data selection lines PB0 to PBn sequentially become high level can be generated as an output control signal by an address counter in the semiconductor memory device.

The operation of the mask ROM having the above configuration will be described with reference to FIG.

When the input address signal is determined at time t0, the first address signal obtained by removing the least significant bits of the input address signal is also determined, and the upper bits of the first address signal are decoded. As a result, one of the row selection lines WL is selected and set to the high level. Then, assuming that the row selection line WLj shown in the drawing becomes high level, the transistors Qij0 to Qijn and Q (i + 1) j0 to Q (i +) connected to the row selection line WLj.
1) Among jn and the like, only those that store the logical state “0” are turned ON. Then, the bit lines BLi0 to BLin, BL (i
+1) 0 to BL (i + 1) n etc.
, The potential of only the bit line BL to which is connected gradually decreases,
The potentials of the other bit lines BL gradually increase.

At the same time, the lower bits of the first address signal (excluding the least significant bits of the lower bits of the input address signal) are decoded, so that one of the column selection lines CS is selected and goes high. Then, the column selection line CSi shown in FIG.
Becomes high level, n + 1 transistors QCSi0 to QCsin connected to the column selection line CSi
N, and only n + 1 bit lines BLi0 to BLin are connected to the data line D via these transistors QCSi0 to QCin.
L0 to DLn.

Therefore, a small change in the potential of the bit lines BLi0 to BLin according to the storage state of the transistors Qij0 to Qijn is input to the first sense amplifier circuits 1SA0 to 1SAn via the data lines DL0 to DLn and amplified. Is done. That is, when the transistor Q forming the memory cell stores the logical state “0”, the potential of the bit line BL gradually decreases.
The sense amplifier circuit 1SA determines the amplification and outputs a low level of the logic amplitude. Further, when the transistor Q stores the logic state “1”, the potential of the bit line BL gradually rises, and the first sense amplifier circuit 1SA amplifies this minute potential rise to determine the logic state. Outputs high level of amplitude.

At this time, the second address signal is decoded, so that the first data selection line P
Assuming that A0 is already at the high level, the data line DL0 is also connected to the second sense amplifier circuit 2SA via the turned-on transistor QPA0. Therefore, the minute change in the potential of the data line DL0 is also amplified and determined by the second sense amplifier circuit 2SA, and a high or low logic amplitude is output.

However, the second sense amplifier circuit 2SA
Since the differential amplifier circuits 2 to 4 have a two-stage configuration for high-speed operation as described above, the output is determined first at time t1, but the first sense amplifier circuit 1SA
As described above, 0 to 1SAn are each composed of one differential amplifier circuit 1 and have relatively low operating speeds, so that their outputs are determined at time t3 after time t1.

Here, the second sense amplifier circuit 2SA
At the time t1 when the output of the second data selection line PB is decoded as shown in FIG.
-1 is high level. Accordingly, the data output from the second sense amplifier circuit 2SA is sent to the output buffer circuit OB via the transistor QPB-1 which has been turned on, so that it is determined as read data D at the subsequent time t2 and externally. Sent out. Further, at time t3 after time t2, the outputs of the first sense amplifier circuits 1SA0 to 1SAn are all determined as described above.

In the case of random access, since the second address signal is constituted by the least significant bits of the input address signal, not only the first data selection line PA0 shown in FIG. As a result, an arbitrary first data selection line PA can be set to a high level, and data can be read from an arbitrary memory cell with an access time TR from time t0 to time t2.

In the high-speed read mode, the output control signal changes at the subsequent time t4 to return the second data selection line PB-1 to the low level, and thereafter, the least significant bits of the input address signal Is switched to the address signal composed of Accordingly, at this time t4, the second data selection line PB0 goes high as shown in FIG.
Data output from sense amplifier circuit 1SA0 is ON
Is sent to the output buffer circuit OB via the transistor QPB0. However, in this case, the output of the second sense amplifier circuit 2SA and the first sense amplifier circuit 1SA0
Is the data determined on the same data line DL0, the data transmitted to the outside does not change.

However, at the subsequent time t5, only the least significant bits of the input address signal are changed, and the second data selection line PB0 is returned to the low level as shown, and the second data selection line PB1 is brought to the high level. Then, the data output from the first sense amplifier circuit 1SA1 is turned on and the output buffer circuit OB is turned on via the transistor QPB1 which is turned on.
At time t6 after a short access time TF has elapsed, it is determined as read data D and sent out. When the transistors QPB2 to QPBn are sequentially turned on by sequentially changing only the least significant bits of the input address signal, the outputs of the first sense amplifier circuits 1SA2 to 1SAn are output after the same access time TF has elapsed.
The data is determined as read data D from B and is sequentially transmitted. By generating the output control signal by an address counter in the semiconductor memory device,
After the second data selection line PB-1 is set to the high level for a certain period, the second data selection lines PB0 to PBn may be sequentially set to the high level.

As a result, in the case of random access or the first data read in the high-speed read mode, one second sense amplifier circuit 2S performing high-speed operation
Since A determines the data on the data lines DL0 to DLn,
The read data D can be determined in the same access time TR as in the related art. Also, a number of first sense amplifier circuits 1SA0 to 1SA0 to 1 provided for each of data lines DL0 to DLn are provided.
Since each output of 1SAn can be determined while transmitting the first data in the high-speed read mode, it is constituted by one differential amplifier circuit 1 having a low operation speed as shown in FIG. Will be able to

Therefore, according to the semiconductor memory device of the present embodiment, only one additional second sense amplifier circuit 2SA performing the same high-speed operation as the conventional one is provided, and each data line DL0 is provided for the high-speed read mode. To DLn, the circuit configuration of the other many first sense amplifier circuits 1SA0 to 1SAn can be simplified.

8 and 9 show another embodiment of the present invention. FIG. 8 is a block diagram showing a circuit configuration of a data reading section of a mask ROM, and FIG. 9 is a sense amplifier circuit section of FIG. FIG. 3 is a circuit diagram showing a specific configuration of FIG. Components having the same functions as those of the conventional example shown in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted.

In the present embodiment, a mask ROM having a high-speed read mode will be described. It should be noted that other semiconductor memory devices other than the mask ROM differ only in the configuration of the memory cells, and the present invention can be similarly implemented.

The mask ROM of this embodiment eliminates the transistors QP0 to QPn in the conventional example shown in FIG. 12 and divides the sense amplifier circuits SA0 to SAn, and connects the switch circuits SW0 to SWn therebetween. It has been inserted. That is, the (n + 1) data lines DL0 to DLn are connected to the first sense amplifier circuits 1SA0 to 1SAn, respectively. Further, these first sense amplifier circuits 1SA0
To 1SAn are connected to switch circuits SW0 to SW, respectively.
It is connected to one second sense amplifier circuit 2SA via Wn. Then, the second sense amplifier circuit 2S
The output of A is connected to the output buffer circuit OB.

Here, the conventional sense amplifier circuit SA0
To SAn are, as shown in FIG. 11, two differential amplifier circuits 2 and 3 in the first stage and one differential amplifier circuit 4 in the second stage.
Was composed by. As shown in FIG. 9, the first sense amplifier circuits 1SA0 to 1SAn of the present embodiment include two differential amplifier circuits 5 and 5 having the same configuration as the two differential amplifier circuits 2 and 3 in the first stage. 6 and the second sense amplifier circuit 2SA is configured by a differential amplifier circuit 7 having the same configuration as the one differential amplifier circuit 4 in the second stage.

Therefore, the first sense amplifier circuit 1SA
The two differential amplifier circuits 5 and 6 compare the potential of the data line DL with the reference potential and output complementary signals. This first sense amplifier circuit 1SA0
To 1SAn are output from the switch circuit SW0, respectively.
Through SWn, one second sense amplifier circuit 2SA
It is connected to the. Each of the switch circuits SW0 to SWn is constituted by transistors QSW0 and QSW1 each composed of two N-channel MOSFETs. Also,
Data selection lines P0 to Pn are connected to the switch circuits SW0 to SWn, respectively.
Are commonly connected to the gate terminals of the two transistors QSW0 and QSW1. Second sense amplifier circuit 2
The SA compares the complementary outputs of any one of the first sense amplifier circuits 1SA0 to 1SAn via the switch circuits SW0 to SWn, amplifies the output, and outputs the amplified result. Then, the data output from the second sense amplifier circuit 2SA is sent to the output buffer circuit OB and sent out as read data D from the semiconductor memory device.

The operation of the above-configured max ROM will be described below.

When the input address signal is determined, the first address signal which is obtained by removing the least significant bits of the input address signal is also determined, and the upper and lower bits of the first address signal are decoded. Thus, for example, the row selection line WLj and the column selection line CSi become high level. Then, the transistor Q constituting the memory cell
Bit lines BLi0 to BLin according to the storage state of ij0 to Qijn
Of the transistor QCS
The signals are input to the first sense amplifier circuits 1SA0 to 1SAn via i0 to QCSin and the data lines DL0 to DLn, respectively.

Here, assuming that the data selection line P0 is already at the high level due to the decoding of the second address signal, the first sense amplifier circuit 1
The complementary signal output from SA0 is sent to the second sense amplifier circuit 2SA via the switch circuit SW0 that has been turned ON. Then, the data on the data line DL0 is determined and output by the first sense amplifier circuit 1SA0 and the second sense amplifier circuit 2SA at the same speed as the conventional one, and is sent out of the output buffer circuit OB to the outside of the semiconductor memory device. You.

In the case of random access, the second address signal is constituted by the least significant bits of the input address signal. Therefore, in this case, an arbitrary data selection line P can be set to a high level by an input address signal, and data can be read from an arbitrary memory cell with the same access time as in the related art. In the case of the high-speed read mode, the second address signal is constituted by, for example, an address signal generated by an address counter inside the semiconductor memory device. Then, when the second address signal is changed by a count operation after reading the data on the data line DL0, the second address signal is decoded, whereby the data selection line P1 becomes high level and only the switch circuit SW1 is turned on. . Then
The complementary signal output from the first sense amplifier circuit 1SA1 is immediately sent to the second sense amplifier circuit 2SA, where the amplification is determined. Thereafter, when the switch circuits SW2 to SWn are sequentially turned on by the counting operation of the address counter, complementary signals output from the first sense amplifier circuits 1SA2 to 1SAn are sequentially sent to the second sense amplifier circuit 2SA to determine the amplification. Is done. Therefore, the output buffer circuit O
From B, data can be sequentially transmitted in a short access time.

In this embodiment, compared to the conventional example shown in FIG. 12, the access time in the high-speed read mode is second.
The time required for determining the amplification of the complementary signal by the sense amplifier circuit 2SA becomes longer. However, the complementary signals output by the first sense amplifier circuits 1SA0 to 1SAn are almost in a definite state while outputting the first data, and have a potential difference of a logic amplitude. This can be determined and output in a very short time. For this reason, also in the case of this embodiment, the access time is almost the same as the access time TF in the conventional example.
Data after the high-speed read mode can be continuously output.

Therefore, according to the semiconductor memory device of the present embodiment, the random access and the high-speed read mode are realized with almost the same access time as the conventional one, while the conventional arrangement is necessary for each of the sense amplifier circuits SA0 to SAn. The circuit configuration can be simplified by using only one differential amplifier circuit 7 of the second sense amplifier circuit 2SA for the differential amplifier circuit of the stage.

Also in the case of the present embodiment, the second address signal is constituted by the least significant bits of the input address signal, and only the least significant bits of the input address signal are changed externally. Thus, a high-speed read mode can be realized.

[0067]

As is apparent from the above description, according to the semiconductor memory device of the present invention, by providing one additional sense amplifier circuit for performing a high-speed operation, each data line is provided for the high-speed read mode. Since the circuit configuration of a plurality of other sense amplifier circuits connected to the sense amplifier circuits can be simplified, the chip area occupied by these sense amplifier circuits can be reduced as a whole, and the power consumption can be reduced. Become like

According to the semiconductor memory device of the present invention,
When a plurality of sense amplifier circuits connected to each data line have a two-stage configuration for the high-speed read mode, the first plurality of sense amplifier circuits share one second-stage sense amplifier circuit. Therefore, while reducing the overall circuit scale of these sense amplifier circuits, reducing the chip area,
Power consumption can also be reduced.

According to the semiconductor memory device of the present invention,
The amount of data that can be read continuously in the high-speed read mode can be increased without causing an increase in the chip area occupied by the sense amplifier circuit and an increase in power consumption consumed by the sense amplifier circuit.

[Brief description of the drawings]

FIG. 1, showing an embodiment of the present invention, is a block diagram illustrating a control signal for reading data and a flow of data.

FIG. 2, showing an embodiment of the present invention, is a block diagram illustrating a circuit configuration of a data reading unit of a mask ROM.

FIG. 3, showing an embodiment of the present invention, is a time chart illustrating an operation of the data reading unit of FIG. 2;

FIG. 4 shows one embodiment of the present invention, and is a table showing signals on a first data selection line based on a second address signal.

FIG. 5 is a table showing output control signals according to one embodiment of the present invention and showing signals on a second data selection line.

FIG. 6, showing an embodiment of the present invention, is a circuit diagram illustrating a specific configuration of an address change detection circuit.

FIG. 7, showing an embodiment of the present invention, is a circuit diagram illustrating a specific configuration of a timing signal generation circuit.

FIG. 8 shows another embodiment of the present invention, and is a block diagram illustrating a circuit configuration of a data reading unit of a mask ROM.

FIG. 9 shows another embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram showing a specific configuration of a sense amplifier circuit section.

FIG. 10 is a circuit diagram of a sense amplifier circuit including one differential amplifier circuit.

FIG. 11 is a circuit diagram of a sense amplifier circuit having a two-stage configuration including three differential amplifier circuits.

FIG. 12 shows a conventional example, and is a block diagram illustrating a circuit configuration of a data reading unit of a mask ROM.

13 shows a conventional example, and is a time chart showing the operation of the data reading section of FIG. 12. FIG.

[Explanation of symbols]

 DL0 to DLn Data line 1SA0 to 1SAn First sense amplifier circuit 2SA Second sense amplifier circuit PA0 to PAn First data selection line PB-1, PB0 to PBn Second data selection line QPA0 to QPAn Transistors QPB-1, QPB0 to QPBn Transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 16/00-16/34 G11C 11/34

Claims (4)

(57) [Claims] 1. A semiconductor for simultaneously selecting a plurality of memory cells from a large number of memory cells based on a first address signal, and reading data stored in the selected plurality of memory cells to a plurality of data lines, respectively. A plurality of first sense amplifier circuits connected to each of the plurality of data lines, each of which amplifies and outputs data on a corresponding data line among the plurality of data lines; A data selection unit connected to the plurality of data lines, for selectively outputting only data on any one of the plurality of data lines based on a second address signal; A second sense amplifier circuit for amplifying the data selectively output by the above at a higher speed than the amplification speed of the plurality of first sense amplifier circuits and outputting the amplified data. . 2. A control signal generating means for generating an output control signal based on the first address signal and the second address signal, and based on the output control signal generated by the control signal generating means. Output data control means for selecting only one of the outputs of the plurality of first sense amplifier circuits and the output of the second sense amplifier circuit and outputting the selected output to an output buffer circuit. The semiconductor memory device according to claim 1. 3. The control signal generating means receives the first address signal and detects a change in the first address signal. The address change detection circuit comprises: a first address signal; Is detected, the output data control means outputs the second
A timing signal generation circuit for generating a timing signal for selecting an output of the sense amplifier circuit for a predetermined period, wherein the control signal generation means generates the timing signal as the output control signal. 13. The semiconductor memory device according to claim 1. 4. The control signal generation means further includes a signal generation circuit for generating a series of signals obtained by sequentially changing the second address signal, and the control signal generation means generates the series of signals. 4. The signal output as the output control signal.
3. The semiconductor memory device according to claim 1.