JPH09204790A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase an access speed of a ROM of which power source voltage is made low. SOLUTION: In a mask ROM having a NOR type memory array (2) of sub-bit line structure, when a memory cell transistor selected by word lines (W1-W32) and a selecting transistor selected by selecting lines (DS1, SS1) are interposed in a current path from a selected bit line to a ground potential, a boosting circuit (5) is adopted as a power source circuit of drivers (DW11, WD101) utilized for selecting/driving word lines and selecting lines. And high speed access can be realized by increasing conductance of these selected transistors, increasing current variation caused there, and improving a detecting speed of a sense amplifier detecting the variation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a mask ROM (read only memory),
For example, the present invention relates to a technique effective when applied to a mask ROM having a NOR type memory cell arrangement and a sub bit line structure.

[0002]

2. Description of the Related Art In a mask ROM, data is written in a wafer process. This data writing method,
That is, the mask ROM programming method is a diffusion layer programming method in which a logical value "1" / "0" of data is defined depending on the presence / absence of a diffusion layer of a memory cell transistor (presence / absence of a memory transistor), and a memory cell by channel / ion implantation. There is an ion implantation programming method in which data is programmed by changing the threshold voltage of the transistor. Mask RO
Regarding the memory arrangement of M, there are NOR type and NAND type. The NOR type ROM is sometimes called a lateral ROM, and has a structure in which word lines and bit lines are arranged in the X and Y directions, and memory cells are arranged in a matrix at intersections of the word lines and the bit lines. The word line to be selected is set to the select level of the memory cell, and the word line to be deselected by the address signal is set to the non-select level of the memory cell, so that the select terminal is coupled to the word line. Storage information is read depending on whether or not a current flows through the bit line through the memory cell. NAND type ROM
Is also referred to as a vertical ROM. One end of a series connection circuit of a plurality of memory cells is coupled to a bit line, and a word line to be selected by an address signal is set to a non-selection level of the memory cell. Depending on whether or not a direct current path is formed in the series connection circuit by setting the word line to be deselected in step 1 to the selection level of the memory cell,
The stored information is read.

As an example of the document describing the mask ROM, "Ultra High Speed MOS Device", pages 316 to 3 issued by Baifukan Co., Ltd. on February 10, 1986.
There are 18 pages.

[0004]

DISCLOSURE OF THE INVENTION The inventor has found that the mask RO
The speedup of the access operation in M was examined. First, when the operating voltage of the semiconductor memory device is lowered,
The selective drive level of the word line cannot make the conductance of the memory cell transistor relatively large. In addition, in a memory array of a type in which a plurality of sub-bit lines are assigned to one bit line and the sub-bit line is selected together with the selection of the word line, the selection drive level of the sub-bit line as well as the word line is set to the conductance of the select transistor. It cannot be made relatively large. When the sense amplifier detects whether or not a current flows through the selected memory cell transistor or select transistor, if the conductance of these transistors becomes small, the change in the current that can be detected by the sense amplifier also becomes slow, and the semiconductor memory device It was clarified that it could delay the access operation of.

In order to deal with them, the boosting of the selection level of the word line or the like has been studied, but in that case, it must be done so as not to violate the demand for lower power consumption by lowering the operating voltage. .

Secondly, when the burst read configuration is adopted in which the output of the sense amplifier is selected by the page selection circuit in units of a plurality of bits so that the read data can be continuously output externally, it is included in the memory array. If replacement of repair data by a repair circuit for repairing a defective bit to be performed is performed in a subsequent stage of the page selection circuit, the page is also written to the repair circuit each time the page selection circuit switches the selected state during burst read. It has been clarified that the burst read operation speed is reduced because the operation must be performed by giving selection information.

Thirdly, a source line to which the source of the memory cell transistor is coupled and a bit line to which its drain is coupled are selected, the selected source line is set to the ground potential, and the selected bit line is set to the sense amplifier. NOR type in which sources and drains of memory cell transistors adjacent to each other are coupled to each other and arranged in series when the read data is determined by whether or not a current is drawn from the sense amplifier to the bit line. In the memory cell array having the above memory array, the unselected bit line or the unselected source line may be electrically connected to the selected bit line depending on the state of the threshold voltage of the memory cell transistor. Such undesired conduction causes erroneous detection by the sense amplifier or reduction in detection speed by the sense amplifier. It is necessary to eliminate this in order to realize the accuracy and speed of the read operation. In particular, in terms of speeding up the read operation, it is necessary to accurately match the precharge level of the selected bit line to the precharge level required by the sense amplifier. It was clarified that it is necessary to improve the credibility by making it difficult to receive.

An object of the present invention is to provide a semiconductor memory device in which the change in the current that can be detected by the sense amplifier is reduced as the operating voltage is lowered and the access speed is reduced.

It is another object of the present invention to use the boosted voltage to improve the reduction in access speed so as not to violate the demand for lower power consumption by lowering the operating voltage. is there.

Still another object of the present invention is to provide a semiconductor memory device capable of preventing a decrease in operating speed due to burst read when replacing a part of read data from a memory array with repair data. is there.

Another object of the present invention is to have a NOR type memory array structure, which is a disadvantage due to the conduction of the non-selected bit line or the non-selected source line to the selected bit line, that is, the sense amplifier. It is to eliminate the erroneous detection due to the error or the decrease in the detection speed due to the sense amplifier. Further, at this time, the precharge level of the selected bit line must be accurately adjusted to the precharge level required by the sense amplifier. Moreover, it is
It aims to make it less susceptible to process variations.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] First, a booster circuit (5) is adopted as a power source for selectively driving a memory cell transistor or a select transistor so as to increase a current change detectable by a sense amplifier.

In a semiconductor memory device having a NOR type memory array, a nonvolatile memory cell transistor (QM) is provided for each word line (W1 to W32) extending in the X direction, as illustrated in FIG. The selection terminals are coupled to the word lines and connected in series, and the series connection points of the memory cell transistors are sub-bit lines (SB1 to SB4) for each Y direction.
A plurality of select transistors (Qds1) for selecting which sub-bit line to form a current path to the bit line (BL1) assigned to each of the plurality of sub-bit lines. , Qds2, Q
ss1, Qss2) includes a memory array (2) provided for each of a plurality of sub-bit lines, and select lines (DS1, DS2, S) for selecting the select transistor.
S1 and SS2) and the word lines (W1 to W32) are driven to a selection level in accordance with the address signal, and a sense amplifier (18, 180) detects a current change caused by the selected memory cell transistor and the selection transistor.
It is configured to detect with. At this time, FIG. 1 and FIG.
, The word line driver (3, WD101) that drives the word line to the selection level and the select line driver (4, DW111) that drives the select line to the selection level A booster circuit (5) for generating is provided. In the semiconductor memory device including the NOR type memory array, the word line and select line designated by the address signal are selectively driven to the boosted potential (VCH) by the driver circuits (3, 4). As a result, the conductance of the selected memory cell transistor or select transistor is increased as compared with the case where the conductance is driven with the power supply voltage (Vdd) supplied from the outside as it is. Therefore, the change in current that occurs through the selected memory cell transistor and select transistor is increased, and the sense amplifier (18
The detection speed of 0) is improved, and high-speed access is realized.

In a semiconductor memory device having a NAND type memory array, a plurality of nonvolatile memory cell transistors (QMM) are connected in series in the Y direction to form a single memory cell column, as shown in FIG. The bit line (BL1) has a plurality of sets of circuits connected in a plurality of columns via select transistors (QDs1, Qds2) in the X direction, and word lines (W1 to W16) are provided to the select terminals of the memory cell transistors for each X direction. Of the select lines (DS1, DS
2) is provided with a coupled memory array and drives the select line together with the word line to a select level according to an address signal,
The sense amplifier (180) detects a change in current generated through the selected memory cell transistor and the select transistor. At this time, FIG.
3, a word line driver (WD101) that drives the word line to a selection level and a select line driver (DW that drives the select line to a selection level).
111) and a booster circuit (5) for generating respective operating power supplies. In a semiconductor memory device having a NAND type memory array, all the word lines except the word line designated by the address signal and the select line designated by the address signal are boosted by the driver circuit (VC).
H) is selectively driven. As a result, the conductance of the selected memory cell transistor and the select transistor is increased as compared with the case where the conductance is driven with the power supply voltage (Vdd) supplied from the outside as it is. Therefore, the change in current that occurs through the selected memory cell transistor and select transistor is increased, the detection speed of the sense amplifier (180) that detects the change is improved, and the access speed is increased.

It is sufficient that the booster circuit (5) can replenish the charge amount consumed by charging the word line and the select line.
As illustrated in FIG. 5, in order to guarantee the word line and select line potentials during the transition from the standby state to the selection operation of the word line and the select line, the minimum necessary boosting operation is performed in the standby state. A first oscillator circuit (44) and a first charge pump circuit (41) are provided. A second charge pump circuit (42) is provided which performs a boosting operation in synchronization with the address transition detection pulse (φATD) in order to compensate the charges consumed by charging the word line and the select line during memory access. Further, the second oscillating circuit (43) and the third charge pump circuit (40) can be employed to perform the boosting operation only when the boosted potential is insufficient. The second level sense circuit (45) is a circuit for detecting a shortage of the boosted potential (VCH) (a decrease in the boosted potential), and the second oscillator circuit in the range where the boosted voltage (VCH) is at a relatively low level. The oscillation operation of (43) is allowed. Since the rapid boosting operation is not required during standby, the oscillation frequency of the first oscillator circuit (44) is lower than that of the oscillator circuit (43). The first level sense circuit (46) is a circuit for detecting that the boosted voltage (VCH) has reached a necessary and sufficient potential.
The oscillation operation of the first oscillating circuit (44) is allowed within a range until H) is set to a necessary and sufficient level.

The booster circuit (5) increases the conductance of the memory cell transistor and the select transistor by making the control gate voltage of the memory cell transistor and the select transistor higher than the power supply voltage, and through them, to the bit line. Since an attempt is made to increase the flowing current, only the minimum boosting operation for securing a necessary memory cell current is performed to suppress an increase in power consumption due to useless boosting operation. That is, the boost level is prevented from becoming too high while guaranteeing the minimum boost potential. The control is mask R
Since the operation is performed according to the operating state of the semiconductor memory device such as OM, the control of the boosting operation can be simplified.

As described above, in order to guarantee the required boosted potential even in the transition from the standby state to the operating state, the first
The oscillator circuit (44) is almost operated. At this time, when adopting the power-down mode in which low power consumption is intended, in order to respond to the power-down mode, the first and second level sense circuits in the power-down mode oscillate the outputs of the oscillation circuits corresponding to the respective outputs. It may be configured to forcibly stop the operation.

[2] Secondly, the defective bit data is replaced with the repair data in the preceding stage of the page selection circuit for burst read. That is, as illustrated in FIG. 1, a memory array (2) in which a large number of non-volatile memory cell transistors are arranged, and a sense amplifier circuit for amplifying a plurality of bits of parallel data read from the memory array and selected. (18) and a page selection circuit (22) for selecting the output of the sense amplifier circuit in units of the number of output bits to the outside using a predetermined address signal,
In a semiconductor memory device in which data can be continuously output to the outside by switching the selection state of the page selection circuit, a relief position for relieving a defective bit included in the memory array and a relief in which relief data is programmed are relieved. Circuit (19) and when the access address to the memory array is the address to be repaired, the repair position information (2
07) to the bit specified by the repair data (210)
And a replacement circuit (20) for replacing the data with the above and outputting to the page selection circuit (22). in this way,
The relief circuit (19) is arranged in the preceding stage of the page selection circuit (22) so that it can be replaced with the relief data. Therefore, it is not necessary to change the operation state of the relief circuit (19) in the burst read performed by changing the specific address signal (A0 to A2). In other words, the operation time of the relief circuit does not affect the burst access time. As a result, the burst read operation speed is constant regardless of whether or not the read target data includes the bit to be relieved, which contributes to speeding up the burst read operation.

[3] Third, in terms of the precharge type of the bit lines and the source lines in the NOR type memory array, the detection operation by the sense amplifier can be speeded up.

First, as illustrated in FIG. 11, a semiconductor memory device is a NOR type including a large number of memory cell rows in which sources and drains of memory cell transistors adjacent to each other are connected and arranged in series. And a bit line (BL1) connected to the source of a non-volatile memory cell transistor (QM) connected to the source and a drain of the memory cell transistor.
Is selected, and the selected source line is set to the ground potential (Vss),
The selected bit line is connected to the sense amplifier (180), and read data is determined by whether or not current is drawn from the sense amplifier to the bit line. Here, the sense amplifier (180) includes a current control transistor (Q1) for negative feedback controlling the level of the input node (Nin).
The detection stage circuit (Q1) for detecting the current drawing from the input node to the bit line by the increase of the conductance of 7).
4, Q15, Q16, Q17). The voltage (340) constantly formed by the circuits (Q24, Q25, Q26, Q27) equivalent to this detection stage circuit is received, and it is unselected via the load transistor (QL2) that uses this as a control voltage. The bit line precharge circuit (30) for precharging the bit line and the voltage (330) constantly formed by the circuits (Q34, Q35, Q36, Q37) equivalent to the detection stage circuit, and receive the voltage (330). A source line precharge circuit (31) for precharging a non-selected source line is provided via a load transistor (QL1) used as a control voltage.

The precharge level of the non-selected bit line is
Since it is controlled by a circuit equivalent to the detection stage circuit of the sense amplifier (180), it is easy to accurately match the precharge level of the non-selected bit line and the non-selected source line with the precharge level required by the sense amplifier. Is. Therefore, the precharge level of the bit line changed from the non-selected state to the selected state is accurately adjusted to the precharge level required by the sense amplifier. As a result, the sense amplifier does not need to substantially precharge the selected bit line and can immediately shift to the detection operation, so that the operation of the sense amplifier can be speeded up. Moreover, it is possible to prevent a situation in which the sense amplifier erroneously detects or delays the detection operation due to an undesired current flowing from the selected bit line to the unselected bit line or the unselected source line.

According to another aspect of the bit line precharge, the semiconductor memory device has a word line (W1 to W1) extending in the X direction as illustrated in FIG.
Each non-volatile memory cell transistor (Q32)
M) is connected in series by connecting a selection terminal to the word line, and the series connection point of the memory cell transistors is Y.
It is connected to the sub-bit lines (SB1 to SB4) for each direction,
A plurality of select transistors are provided for selecting which sub-bit line is assigned to each of the plurality of sub-bit lines and which source line is connected to the sub-bit line adjacent to the sub-bit line. A select line provided for each sub-bit line and for selecting the select transistor is selected together with the selection of the word line, so that the bit line and the select line are connected to the adjacent sub-bit line via the selected select transistor. Memory array (2). A bit line selection circuit (12) for selecting the bit line; and a source line selection circuit (14) for connecting a source line paired with the bit line selected by the bit line selection circuit to a ground potential (14). A sense amplifier (180) for detecting a state where current flows into the bit line selected by the line selection circuit. Mainly having such a configuration, a bit line precharge circuit (30) for precharging a bit line that is not selected by the bit line selection circuit (12) and a non-selected bit line precharge circuit (14) by the source line selection circuit (14). Source line precharge circuit (31) for precharging the selected source line
And From this point of view, the non-selected bit line and the non-selected source line are directly precharged by the precharge circuit without passing through the sense amplifier.
0) does not need to positively precharge the bit line changed from the non-selected state to the selected state, and can immediately shift to the detection operation, so that the operation of the sense amplifier can be speeded up. it can.

Further, in the case of adding the viewpoint of precisely adjusting the precharge level to the precharge level required by the sense amplifier, the sense amplifier (180) controls the level of the input node (Nin) by negative feedback control. Detection stage circuit (Q14, Q15, Q1) for detecting current drawing from the input node to the bit line by increasing the conductance of the current controlling transistor (Q17)
6, Q17) and a dummy memory array (32) having an equivalent circuit configuration related to a pair of source lines and bit lines of the memory array, and a circuit (Q
34, Q35, Q36, Q37), so that the dummy source line (DS) included in the dummy memory array is
And a dummy source line precharge circuit (33) for precharging L) and a circuit (Q24,
And a dummy bit line precharge circuit (3) for precharging the dummy bit line (DBL) included in the dummy memory array.
4) and are provided. The source line precharge circuit (31) includes a dummy source line precharge circuit (3
Control voltage (330) of the current controlling transistor (Q37) included in the circuit equivalent to the detection stage circuit included in 3).
Of the load transistor (QL1) as a bias voltage for determining the precharge level. The bit line precharge circuit (30) includes a current control transistor (Q2) included in a circuit equivalent to the detection stage circuit included in the dummy bit line precharge circuit (34).
The load transistor (QL2) receives the control voltage (340) of 7) as a bias voltage for determining the precharge level. According to this, the dummy precharge circuit (33, 34) having a precharge characteristic substantially the same as the detection stage circuit (Q14 to Q17) of the sense amplifier (180) and the basic circuit configuration of the memory array are equivalent. A dummy memory array (32) and a voltage (330, 340) obtained when the dummy bit line (DBL) and the dummy source line (DSL) are constantly precharged by the dummy precharge circuits (33, 34). )Using,
Since a precharge level equivalent to the precharge level obtained by the dummy precharge is formed in the non-selected source line and the non-selected bit line, the pre-charge level of the non-selected bit line and the non-selected source line is the sense amplifier. (1
80) is accurately matched with the required precharge level. In other words, when the non-selected bit line is selected, the level of the selected bit line is also set to the precharge level required by the sense amplifier (180). Can be matched with high precision. As a result, the sense amplifier (180)
It is possible to guarantee the high-speed operation and to prevent the erroneous detection of read data by the sense amplifier with high accuracy. In addition, a bias signal (33
0, 340) are equivalent circuits (32, 33,
Since it is formed through 34), it is unlikely to be affected by process variations.

The dummy precharge circuits (33, 34) are controlled by the control voltage (330, 34) regardless of whether they are in the standby state or the operating state.
It is desirable to form 0) in terms of reliability of the precharge operation. At this time, when adopting the power down mode in which low power consumption is intended, in order to respond to the power down mode, in the power down mode, the dummy precharge circuit (33, 34) is connected to a DC circuit equivalent to the detection stage circuit. Transistors that cut off the current path (Q28, Q
38) and transistors (Q29, Q39) for controlling cutoff of the load transistors (QL1, QL2) included in the bit line precharge circuit (30) and the source line precharge circuit (31).

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION

<< Outline of Mask ROM >> FIG. 1 shows an overall block diagram of a mask ROM according to an embodiment of the present invention. First, the mask ROM of this embodiment will be outlined. Although not particularly limited, the mask ROM of this embodiment is formed on a single semiconductor substrate such as a single crystal silicon substrate by a known MOS semiconductor integrated circuit manufacturing technique. In the drawings referred to in this specification, the circuit symbol of the p-channel type MOS transistor is distinguished from the n-channel type MOS transistor by adding an arrow to its source.

The mask ROM of this embodiment is a NOR type mask ROM and has a flat cell type memory array 2. Although not particularly limited, the memory array 2 has eight memory mats MMAT, and each memory mat MMA
T has 64 memory blocks MBLK. FIG. 2 illustrates the configuration of one memory block MBLK, and FIG. 3 illustrates the overall configuration of one memory mat MMAT.

First, the basic structure of the memory block MBLK will be described with reference to FIG. Although not particularly limited, the memory block MBLK has 256 bit lines (B
L1 to BL256) and 257 source lines (SL1 to S
L257) and 32 word lines (W1 to W32). In FIG. 2, bit lines BL1 and BL2, source lines SL1, SL2 and SL3, and word lines W1, W2 and W3 are typically shown.
1, W32 are shown. According to this example, a series circuit of 1024 memory cell transistors QM is arranged along each word line, each gate is arranged in the corresponding word line, and the drain / source are arranged in parallel in the bit line direction. Of memory cell transistors QM are coupled to sub-bit lines SB1 to SB4. For example, focusing on the source line SL1 and the bit line BL1, the sub bit line SB1 is connected to the source line S via the select MOS transistor Qss1.
Sub bit line SB3 is connected to source line SL1 via select MOS transistor Qss2, sub bit line SB2 is connected to bit line BL1 via select MOS transistor Qds2, and sub bit line SB4 is connected to select MO.
It is coupled to bit line BL1 through S transistor Qds2. As for the other bit lines and source lines, the coupling relation with the four sub bit lines SB1 to SB4 is repeated in the same manner as above. Each select MOS transistor Qss1 is switch-controlled by the select line SS1, each select MOS transistor Qss2 is switch-controlled by the select line SS2, each select MOS transistor Qds1 is switch-controlled by the select line DS1, and each select MOS transistor Qs1. Qds2 is switch-controlled by the select line DS2.

Although not particularly limited, the sub-bit line S
B1 to SB4 are formed by diffusion layers of the memory cell transistor QM, the bit lines BL1 to BL265 and the source lines SL1 to SL257 are formed by aluminum wiring, and the word lines W1 to W32 and the select line DS are formed.
1, DS2, SS1 and SS2 are composed of silicide.

The memory cell transistor QM stores information by a so-called ion implantation programming method, and has a threshold voltage that can be turned on by receiving a word line selection level such as a high level at the gate, or a high level. Even if the gate receives the word line selection level as described above, it is in any one of the states having a relatively high threshold voltage which maintains the off state.

In reading data from the memory cell transistor QM in the memory block MBLK, one sub-bit line connected to one bit line is selected by the selecting operation of the select MOS transistors Qds1 and Qds2, and the sub-bit to be selected is selected. Another adjacent
Select sub-bit line to select MOS transistor Qss
The operation of connecting to one source line by the operation of selecting 1, Qss2 and the operation of selecting one word line are performed. For example, in the case of paying attention to the bit line BL1, in the data reading of the memory cell transistor QM arranged between the sub bit lines SB1 and SB2, the select MOS transistors Qds1 and Qss1 are selected (turned on) and the bit line BL1 and the source are selected. This is performed depending on whether or not a current path is formed between the line SL1 and the line SL1. Sub bit line SB2
And a memory cell transistor QM arranged between SB3 and SB3
The data read of the select MOS transistor Qd
Select s1 and Qss2 to select bit line BL1 and source line S
This is performed depending on whether or not a current path is formed between L1 and L1. Similarly, the data read of the memory cell transistor QM arranged between the sub-bit lines SB3 and SB4 is
The selection MOS transistors Qds2 and Qss2 are selected depending on whether or not a current path is formed between the bit line BL1 and the source line SL1. Sub bit line SB
Memory cell transistor Q arranged between 4 and SB1
The data read of M is performed by the select MOS transistor Q.
This is performed depending on whether ds2 or Qss1 is selected and whether a current path is formed between the bit line BL1 and the source line SL2.

In this embodiment, as shown in FIG.
The memory mat MMAT has 64 memory blocks M.
Includes BLK. The bit line and the source line of each memory block MBLK are shared or commonly connected among the 64 memory blocks MBLK.

The one designated by 3 in FIGS. 1 and 3 is the word lines W1 to W3 of the memory block MBLK.
2 is a word driver for driving 2, and 4 is select lines DS1, DS2, SS1, of the memory block MBLK.
A select line driver for driving SS2. The selection levels of the signals output by the word driver 3 and the select line driver 4 are supplied from the booster circuit 5. Although details of the booster circuit 5 will be described later, an address transition detection pulse φATD or the like output from the address transition detection circuit 7 is used for the boosting operation. The address change detection circuit 7 changes the address change detection pulse φATD once in a pulse shape every time a change in the address signals A0 to A19 is detected. Address change detection pulse φATD
Is also used to generate a timing signal for dynamically operating the inside of the mask ROM.

The word driver 3 receives the decode signal output from the word line X decoder 6 and drives the word line corresponding to the decode signal of the select level to the select level. Although not particularly limited, according to the present embodiment, as shown in FIG. 1, the word line X decoder 6 receives an internal complementary address signal corresponding to 8-bit address signals A12 to A19 from the address buffer 8. This is decoded and the 64 memory blocks MBLK shown in FIG.
(Eight memory blocks in (# 1) to (# 64) are selected, and the word line W1 in each selected memory block is selected.
A decode signal for selecting any one of W32 to W32 is formed. That is, the address signals A12 to A14
Is a unit of eight memory blocks MBLK (# 1) to MBLK (# 8), ..., MB of the 64 memory blocks MBLK of FIG.
It is regarded as a signal for selecting any one unit (8 memory blocks MBLK) from LK (# 57) to MBLK (# 64). The address signals A15 to A19 are word lines W1 to W in one memory block MBLK.
It is regarded as a signal for selecting any one of 32.
Therefore, the decoded signal by that is used as the units MBLK (# 1) to MBL of eight memory blocks MBLK.
K (# 8), ..., MBLK (# 57) to MBLK (# 6
4) The number is 32 for each. As shown in FIG. 3, the word driver 3 that receives a total of 32 × 8 decoded signals output from the word line X decoder 6 includes 32 driver WDs provided for every 8 memory blocks MBLK.
, WD801 to WD832. That is, one driver is used to drive eight word lines. For example, the driver WD101 uses the word line W1 included in each of the eight memory blocks MBLK.
It is used to drive. Therefore, in the word line selection operation, eight memory blocks MB among the 64 memory blocks MBLK included in one memory mat MMAT.
One word line is driven to the selection level in each of LK.

As shown in FIG. 1, the select line driver 4 receives the decode signal output from the select line X decoder 10. Select line X decoder 10 is 1
One memory block MBLK out of 64 memory blocks MBLK included in each memory mat MMAT
Is selected, and one of the four selectable states of the sub-bit line in the designated memory block MBLK is selected, and the bit line and the source line are selected from the memory cell transistors QM selected by the word line. The memory cell transistor QM to be connected to is selected. Although not particularly limited, according to the present embodiment, as shown in FIG.
The select line X decoder 10 receives an internal complementary address signal corresponding to the 8-bit address signals A7 to A14 from the address buffer 8, decodes it, and decodes four decode signals unique to each memory block MBLK ( A total of 256 decoded signals) are formed. As shown in FIG. 3, the select line driver 4 includes 256 drivers DW112, DW111,
SW112, SW111 to driver DW882, DW8
81, SW882, SW881. A total of 256 decoded signals are 8-bit address signals A7 to A1.
4, the select line DS1 or D of one memory block MBLK among the 64 memory blocks MBLK
It is changed to select a total of two lines S2 and select lines SS1 or SS2.

By the operation of selecting the word line and the select line, one memory block MBLK is designated from the 64 memory blocks MBLK included in one memory mat, and the sub-bit is designated in the designated memory block MBLK. One of the four selectable states of the line is selected, and the memory cell transistor QM to be connected to the bit line and the source line is selected from the memory cell transistors QM selected by the word line. As a result, a current path to the source line may or may not be formed in the bit lines BL1 to BL256 depending on the programmed state of the selected memory cell transistor.

According to this embodiment, the memory mat MM is
AT, word driver 3 and select line driver 4 are 8
A set of 8 parallel memory mats MMA
At T, the selection operation of the word line and the select line is performed. The bit line selection circuit 12 is a switch circuit that selects 16 bit lines from 256 bit lines in each of the eight memory mats MMAT. The bit line Y decoder 13 receives an internal complementary address signal corresponding to the 4-bit address signals A3 to A6 from the address buffer 8 and decodes it to control the bit line selection operation by the bit line selection circuit 12. The source line selection circuit 14 is a switch circuit that selects 16 source lines from 257 source lines in each of the eight memory mats MMAT. Source line Y decoder 15 receives an internal complementary address signal corresponding to 4-bit address signals A3 to A6 from address buffer 8 and decodes it to control the source line selecting operation by source line selecting circuit 14. The decode logic of the source line Y decoder 15 is not the same as the decode logic of the bit line Y decoder 13, but a source line connectable to the selected bit line must be selected. As described above, depending on the selected state of the select MOS transistor, the source line on the right side may have to be selected, so there is no particular limitation in order to consider the selected state by the select line X decoder 10. Specific 2 bits (select line S
An internal complementary address signal corresponding to 2 bits (which is considered to indicate which one of D1 and SD is selected and which one of the select lines SS1 and SS is selected) is also supplied to the source line Y decoder 15. ing. FIG.
In the figure, the supply state of the 2 bits to the source line Y decoder 15 is not shown.

The bit line selection circuit 12 selects a total of 128 bit lines for the eight memory mats MMAT, and the source line selection circuit 14 corresponds to the 128 bit lines.
The source line of the book is selected from the eight memory mats MMAT. A bit line precharge circuit 30 is provided on the bit line of each memory mat, and precharges the bit line that is not selected by the bit line selection circuit 12. Similarly, the source line of each of the memory mats is provided with a source line precharge circuit 31 to precharge the source line that is not selected by the source line selection circuit 14. The details will be described later together with the precharge circuits 30 and 31, but
A dummy memory array 32 and dummy precharge circuits 33 and 34 are provided to determine the precharge level by the bit line precharge circuit 30 and the source line precharge circuit 31.

The bit lines selected by the bit line selection circuit 12 are individually connected to the common data lines CD1 to CD128. The common data lines CD1 to CD128 are connected to the sense amplifier circuit 18. The sense amplifier circuit 18 has a current detection type sense amplifier unique to each of the common data lines CD1 to CD128. The sense amplifier will be described later, but when a current flows from the bit line to the source line, the change in the current is detected. The detection result of the presence or absence of current change by the sense amplifier is output to the subsequent stage as the data read result from the memory cell. The output of the sense amplifier circuit 18 is given to the page selection circuit 22 via the multiplexer 20. When there is data to be rescued by the rescue circuit 19 described later, the multiplexer 20 replaces a part of the output data of the sense amplifier circuit 18 with the rescue data 210 output from the rescue circuit 19 and then selects the page selection circuit. Give to 22. The page selection circuit 22 is
It is a circuit that selects 16 bits from the 128-bit data output from the multiplexer 20. The page decoder 23 receives an internal complementary address signal corresponding to the 3-bit address signals A0 to A2 from the address buffer 8 and decodes it to control the selection operation of output data by the page selection circuit 22. In this way, data reading from the memory array 2 is performed in 128-bit units, and 16 bits of the data are selected by the lower addresses A0 to A2. The next data can be immediately output from the page selection circuit 22 in synchronization with the change of the addresses A0 to A2. That is, burst read can be performed via the page selection circuit 22, and data can be read from continuous addresses at high speed.

The 16-bit data selected by the page selection circuit 22 is passed through the data buffer 24 to the data terminal D.
0 to D15.

In FIG. 1, reference numeral 25 is a timing controller. The timing controller 25 is not particularly limited, but a chip selection signal / CE (symbol / means that the signal with the symbol / is a low enable signal), an output enable signal / OE, a power down signal /
PWD is input from the outside, and internal control signals φOE, φCE, φPWD corresponding to the levels of these signals are output in synchronization with the address transition detection pulse φATD. Internal control signals φOE, φCE, φPWD are used as activation control signals. The control signal φOE is a signal for enabling the output operation of the data buffer 24, and is set to the output enable state (output enable signal / OE = low level) in the chip selection state (chip selection signal / CE = low level). As a result, the data buffer 24 is set to the high level, which enables the data output operation. Data buffer 24 is otherwise placed in a high output impedance state. The control signal φCE is not particularly limited, but in response to the chip selection state, the address buffer 8,
This is a control signal for activating the decoders 6, 10, 13, 15, 23. In the chip non-selected state (chip selection signal / CE = high level) when the operating power is turned on, the address buffer 8, decoders 6, 10, 1
3, 15, and 23 are inactivated, and this state is called a standby state or a standby mode. Control signal φP
WD is a signal which controls activation / inactivation of the booster circuit 5 and the dummy precharge circuits 33 and 34, although not particularly limited. This signal φPWD deactivates the booster circuit 5 and the dummy precharge circuits 33 and 34 when the power down signal / PWD is in the chip non-selected state (chip selection signal / CE = high level) and is set to the low level. . This state is called a complete standby state or power down mode. In other states, the booster circuit 5
The dummy precharge circuits 33 and 34 are activated. In other words, the booster circuit 5 and the dummy precharge circuits 33 and 34 are made operable in the standby state, and the desired state can be internally maintained for the next memory access operation. The power down mode is an operation mode set when low power consumption is given the highest priority.

<< Boosting of Word Line and Select Line >> In order to sufficiently increase the conductance of the memory cell transistor to be turned on, boosting the word select level is convenient for speeding up the read operation. At this time, in the mask ROM, as described with reference to FIG. 2, one sub-bit line is selected from the sub-bit lines SB1 to SB4 by selecting MOS transistors Qds1 and Qds.
2, Qss1 and Qss2 are selected and connected to the source line and the bit line. For example, in FIG. 2, the sub bit line SB1
Is connected to the bit line BL1 and the source line SL1, the select MOS transistors Qds1 and Qss1 are selected to be in the ON state, whereby the drain is connected to the bit line BL1.
One of 32 memory cell transistors QM in one column whose source is connected to the source line SL1 is selected by the word line. Therefore, the current path from the bit line to the source line includes the memory cell transistor selected by the word line and the two select MOS transistors selected by the select line. These three transistors have substantially the same size in terms of the memory array configuration. That is, select MO
S transistors Qds1, Qds2, Qss1, Qss
Reference numeral 2 is a transistor having substantially the same size as the memory cell transistor QM. This is for improving the integration degree or memory density of the transistors. Therefore, even if only the selection level of the word line that selects the memory cell transistor QM is boosted, it is not possible to increase the change in current that can be detected by the sense amplifier (the read operation cannot be speeded up). It is necessary to boost three signals together with the selection signal of the selection MOS transistor. In consideration of this, in the present embodiment, the word lines W1 to W3 are
Select lines DS1, DS2, SS with selection level 2
The selection levels of 1 and SS2 are also boosted levels (VCH) boosted by the booster circuit 5. By raising the select line select level as well as the word line select level to the power supply voltage (Vdd) or more, the current flowing through the bit line during data read becomes large, in other words, the current change through the bit line becomes faster, which results in The sense amplifier can immediately detect a change in current and can increase the data read speed. In particular, the effect is that the operating power supply voltage is 3.3.
This is remarkable in a mask ROM having a relatively low power supply voltage such as V.

As described above, in the read operation, one of the 64 memory blocks MBLK sharing the source line and the bit line with each other in each memory mat MMAT.
Memory blocks MBLK are designated and designated 1
Sub-bit lines S included in each memory block MBLK
In each of 256 pairs of B1 to SB4, one sub-bit line is connected to the bit line and the other sub-bit line is connected to the source line. Therefore, the word lines W1 ...
Since W32 needs to drive only one word line for each memory block MBLK, the word line selection operation may be performed in a plurality of memory blocks. From the viewpoint of reducing the number of drivers of the word driver 3 and thereby reducing the chip occupation area, increasing the number of word lines to be driven by one driver, that is, the word lines to be simultaneously selected. It is desirable to increase the number of. For example, the drivers WD101 to WD132 in FIG.
It is also possible to adopt a configuration in which the word line of LK is commonly used. However, in order to reduce the operating current of the word driver, it is effective to reduce the number of word lines that are simultaneously brought to the selection level. Further, in order to reduce the load on the booster circuit 5, it is necessary not to increase the number of word lines simultaneously operating unnecessarily.

In the present embodiment, in order to satisfy both of the above viewpoints to some extent, as shown in FIG. 3, each driver WD101, ... Is provided. In FIG. 4, eight memory blocks MBLK (# 1)
~ Driver DW111 corresponding to MBLK (# 8),
SW112 and WD101 are representatively shown. In the figure, the decode logics of the word line X decoder 6 and the select line X decoder 10 are shown as a single unit. The decode logic shown therein is just an example.

As typically shown in FIG. 4, the word line driver and the select line driver have the same circuit configuration. For example, the driver WD101 has two p-channel type MOS transistors Q1 and Q2 whose sources receive the boosted voltage VCH, and the drain of one transistor is coupled to the gate of the other transistor.
The drain of the MOS transistor Q1 is coupled to the drain of an n-channel type MOS transistor Q3 whose source is connected to the ground potential Vss.
The corresponding output signal line SW1 of the decoder is coupled to the gate of the. The drain of the MOS transistor Q2 is
The output signal line SW1 is supplied through an n-channel MOS transistor Q4 whose gate is biased by the power supply voltage Vdd.
Is combined with The output terminal of the driver WD101 is a MOS
It is used as the drain of the transistor Q1.

According to FIG. 4, the outputs of the decoders 6 and 10 are set at the low level as the selection level. Driver WD1
In 01, when the output signal line SW1 is at the non-selection level (high level), the transistor Q3 is turned on, and the word line W1 is set to the ground potential Vss which is the non-selection level. When the output signal line SW1 is at the selection level (low level), the transistors Q2 and Q3 are cut off, and the boosted potential VCH as the selection level is supplied to the word line W1.

<< Boosting Circuit >> FIG. 5 shows a block diagram of the boosting circuit 5. The booster circuit 5 includes three charge pump circuits 40 to 42 and two oscillator circuits 43, 44, and 2.
It has individual level sense circuits 45 and 46 and a relatively large storage capacitance 47. The storage capacitor 47 has a capacitance value that is large enough to store the charges necessary to charge the word line and the select line. Therefore, the booster circuit 5 only needs to be able to replenish the charge amount consumed by charging the word line and the select line, but guarantees the potential of the word line and the select line at the transition from the standby state to the operation of selecting the word line and the select line. Therefore, the oscillation circuit 44 and the charge pump circuit 41 are provided so as to perform the necessary minimum boosting operation in the standby state. A charge pump circuit 42 that performs a boosting operation in synchronization with the address transition detection pulse φATD is provided in order to supplement the charge consumed by charging the word line and the select line during memory access. Further, the oscillation circuit 43 and the charge pump circuit 40 are provided to perform the boosting operation only when the boosted potential VCH is insufficient. Level sense circuit 45 has boosted potential VCH
Is a circuit for detecting a deficiency of voltage (decrease in boosted potential), and allows the oscillation operation of the oscillation circuit 43 in a range where the boosted voltage VCH is at a relatively low level. Although not particularly limited, the level sense circuit 45 has the level detection signal φl in the range where the boosted voltage VCH is at a relatively low level.
Set ow to high level. The oscillation frequency of the oscillation circuit 44 is set lower than that of the oscillation circuit 43 because a rapid boosting operation is not required in the standby state. Level sense circuit 4
Reference numeral 6 is a circuit for detecting that the boosted voltage VCH has reached a necessary and sufficient potential, and allows the oscillation operation of the oscillation circuit 44 within a range until the boosted voltage VCH is set to a necessary and sufficient level. The level sense circuit 46 is not particularly limited.
Raises the level detection signal φhigh to the high level within a range until the boosted voltage VCH is set to a necessary and sufficient level. In the mask ROM, the boosted potential above the required level only increases the power consumption. The output of the level sense circuit 46 is further supplied to all charge pump circuits 4
It is used for stop control of the boost operation by 0 to 42. When the level sense circuit 46 detects that the boosted voltage has reached a necessary and sufficient potential, the detection output (low level output) stops the oscillation operation of the oscillation circuit 44, and the level sense circuit 45 is turned off. When the AND gate 4 is activated, the oscillation operation of the oscillation circuit 43 is stopped.
The change of the address change detection pulse φATD is blocked by 8 and the operation of the charge pump circuit 42 is stopped.

Next, a specific example of each circuit included in the booster circuit 5 will be described. FIG. 6 shows an example of the charge pump circuit 40. Reference numeral 400 denotes an n-channel transfer gate MOS transistor, the source of which is connected to the storage capacitor 47, and the drain of which is coupled to the three-stage inverters 402, 403 and 404 in series via the capacitor 401. Capacity 401
Are provided for boosting the potential of the drain of the transfer gate MOS transistor 400. The gate of the MOS transistor 400 is an n-channel switch MO.
It is coupled to the power supply voltage Vdd via the S-transistor 405 and is connected to the inverter circuit 407 via the capacitor 406.
Combined with the output of. The capacitor 406 is a transfer gate MO
It is provided to boost the gate potential of the S transistor 400. The inputs of inverters 404 and 407 are coupled to the output of NAND gate 408. The switch MO
The gate of S-transistor 405 is coupled to the output of NOR gate 410 via capacitor 409. Reference numeral 411 denotes an n-channel type M of diode connection type in which the direction from the power supply voltage Vdd to the gate of the MOS transistor 405 is the forward direction.
OS transistor (commutator transistor), 412 is M
This is a diode-connected n-channel MOS transistor (rectifier transistor) whose forward direction is from the gate of the OS transistor 405 to the power supply voltage Vdd. As a result, the gate of the MOS transistor 405 is set to the MOS transistor 412 with respect to the power supply voltage Vdd.
Attempts to keep the level higher by the threshold voltage of. 413
Is an n-channel type MOS transistor which receives the gate potential of the MOS transistor 405 and tries to maintain the drain of the MOS transistor 400 at least at the power supply voltage. Similarly, 414 receives the gate potential of the MOS transistor 405 and receives the MOS transistor 4
00 is an n-channel MOS transistor that tries to maintain at least the power supply voltage at its gate.

The pulse signal output from the oscillation circuit 43 is supplied to one input of the NOR gate 410 via the serial two-stage inverter circuits 416 and 417, and the other input terminal is connected to the inverter circuits 418 and 419 and the capacitor. 420
The output of the inverter circuit 417 is supplied through a delay circuit consisting of The output of the NOR gate 410 is immediately inverted to the low level in response to the rising change of the pulse signal, but its output is changed to the high level after waiting the delay time by the delay circuit for the falling change of the pulse signal. Be changed. The same signal as that of the NOR gate 410 is input to the NAND gate 408 as well. NAND Gate 4
The output of 08 is changed to a low level with respect to the rising change of the pulse signal after waiting the delay time by the delay circuit, and its output is immediately inverted to the low level with respect to the falling change of the pulse signal. .

Charge pump circuit 4 having the above configuration
When 0, when the input pulse signal is changed to the high level, the gate of the MOS transistor 400 is boosted via the capacitor 406 and the drain side of the MOS transistor 400 is boosted via the capacitor 401, thereby accumulating charges. It is transmitted to the capacity 47. When the input pulse signal is changed to the low level, the power supply voltage Vdd is supplied via the MOS transistors 413 and 414 to the drain and the gate of the MOS transistor 400 which is about to be lowered in level, and the next boosting operation is performed. You will be prepared. By repeating such an operation, a boosted potential is formed in the storage capacitor 47. Another booster circuit 41,
42 is similarly configured.

FIG. 7 shows an example of the oscillator circuit 43. The oscillator circuit 43 is composed of a ring oscillator mainly including a feedback circuit in which an inverter 430 and a NAND gate 431 are connected in series in an odd number of stages. The oscillation frequency is determined by the time constant of the resistor 432 and the capacitor 433. The level sense signal φlow is supplied to the NAND gate 431, and when the level sense signal φlow is set to the high level, the oscillation circuit 43 is enabled to oscillate. Although not particularly shown, the oscillator circuit 44 has a basic circuit configuration similar to that of FIG. 7. However, the time constant due to resistance and capacitance is
The oscillation frequency is relatively low.

FIG. 8 shows an example of the level detection circuit 46, and FIG. 9 shows an example of the level detection circuit 45. In the present embodiment, although not particularly limited, the expected value voltage (target voltage) of the boosted potential VCH is set to a level 1.5 times the power supply voltage Vdd, and at this time, the level detection circuit 45.
The level detected by is a voltage obtained by adding a certain voltage to the lowest level of the operation guarantee voltage related to the power supply voltage Vdd. For example, when Vdd = 3.3V, the detection level of the level detection circuit 45 is 4.3V. The level detected by the level detection circuit 46 is, for example, the upper limit voltage level of the burn-in voltage.

In FIG. 8, p-channel type MOS transistors 460 and 464 having a gate and a drain coupled to each other.
A resistor voltage divider circuit in which a resistor and a resistor 462, 463 are connected in series is a circuit that forms a voltage of Vdd / 2 as a reference potential, and includes a p-channel type power switch MOS transistor 460 and an n-channel type power switch MOS transistor 465. The current flowing through the resistance voltage divider circuit can be cut off by. p-channel type MO
The CMOS inverter circuit including the S transistor 467 and the n-channel MOS transistor 468, the series circuit of the p-channel MOS transistor 466 with the gate and drain coupled to each other, and the n-channel power switch MOS transistor 469 are connected to the boosted potential VCH. It is arranged between the ground potential Vss and a detection stage circuit. This detection stage circuit has the number of MOS transistors 466 in series so that the level of the boosted potential VCH when the output of the CMOS inverter that receives Vdd / 2 at its input is inverted from low level to high level is the level to be detected. Has been decided. According to this detection stage circuit, when the boosted voltage VCH obtained by the booster circuit 5 reaches a necessary and sufficient level, the CMOS inverter circuits (467, 46).
The output of 8) is inverted to high level. The output of the CMOS inverter circuit (467, 468) is transmitted to the subsequent stage as a level detection signal φhigh via a latch circuit constituted by a NAND gate and the like. Level detection signal φ
High is inverted to low level when the boosted voltage VCH reaches a necessary and sufficient level.

Power switch MOS transistor 4
60, 465, 469 are controlled by the power down signal φPWD, and in the power down mode in which it is brought to a high level, the power switch MOS transistors 460, 465, 469 are cut off.
This cuts off the through current path from the power supply voltage Vdd and the boosted potential VCH to the ground potential Vss. In the power-down mode, the p-channel pull-up MOS transistor 470 has a CMOS inverter circuit (467,
468) forcing the output of 468) to a high level, and by this setting the level detection signal φhigh to a low level, the oscillation operation of the oscillation circuit circuit 44 is stopped in the power-down mode, and the charge pump circuit 41 The boosting operation is also blocked, and the operation of the oscillation circuit 43 is also stopped via the level sense circuit 45 as described later.

The level sense circuit 45 shown in FIG.
Although the basic circuit configuration is the same as that of the level detection circuit 46, a MOS transistor 466 forming a detection stage circuit is used.
The number of serial stages of the power switch MOS transistors 460, 465, 46 is smaller than that of the configuration of FIG.
7 and the pull-up MOS transistor 470 are supplied with the level detection signal φhigh as a switch control signal, which is different from the level detection circuit 46. The detection stage circuit including the MOS transistors 467 and 468 is a level for detecting the level of the boosted potential VCH when the output of the CMOS inverter circuit (467, 468) receiving Vdd / 2 at its input is inverted from low level to high level. So that the MOS transistor 46
The number of 6 serial stages is determined. According to this detection stage circuit, when the boosted voltage VCH obtained by the booster circuit 5 reaches the minimum required level, the output of the CMOS inverter circuit (467, 468) is inverted to the high level. The output of the CMOS inverter circuit (467, 468) is transmitted to the subsequent stage as a level detection signal φlow via a latch circuit formed by a NAND gate and the like.
The level detection signal φlow is inverted to the low level when the boosted voltage VCH reaches the minimum required level.
When the boosted voltage VCH obtained by the booster circuit 5 becomes too low due to the charging operation for the word line and the like, and the level detection signal φlow is set to the high level, the oscillation circuit 43 is oscillated thereby, and the charge pump circuit 4
0 starts the boosting operation for immediately supplementing the insufficient potential. This operation is performed until the required minimum level of the boosted voltage VCH is obtained, and the boosting operation thereafter is entrusted to the charge pump circuit 41.

When the level detection signal φhigh is set to the low level, the power switch MOS is operated as described above.
The transistors 460, 465, 469 are cut off, which causes the power supply voltage Vdd and the boosted potential VC.
The through current path from H to the ground potential Vss is cut off.
Further, the level detection signal φlow is set to the low level by the action of the pull-up MOS transistor 470, so that the oscillation operation of the oscillation circuit 43 is stopped.

As described above, the charge pump circuit 5 receives level detection signals φhigh and φlo when the power is turned on.
As a result of w being both set to the high level, the boosting operation by the charge pump circuits 40 and 41 is started. Boost voltage VC
When H reaches the minimum required level, the level detection signal φlow is changed to the low level, and the oscillation operation 43 of the oscillation circuit 43 is stopped. After that, the oscillating operation of the oscillation circuit 44 is controlled so that the boosted voltage VCH does not exceed the upper limit level detected by the level sense circuit 46.
Controlled by 6. The boosted potential lowered by the word line / select line selection operation during memory access is
This is uniquely supplemented by the boosting operation of the charge pump circuit 42 synchronized with the address transition detection pulse φATD. When the level sense circuit 45 detects a decrease in the boosted level that cannot be compensated even by this boosting operation, in addition to this, the oscillation circuit 43 is oscillated by the high level level detection signal φlow, and the charge pump circuit 40. The rapid boosting operation is started. The operation is boosted voltage VCH
Until the minimum required level is reached.

As described above, the booster circuit 5 in the mask ROM includes the memory cell transistor QM and the select MO.
By increasing the gate voltage of the S-transistor, an attempt is made to increase the current flowing through the memory cell transistor QM to the bit line (hereinafter also simply referred to as the memory cell current). Therefore, in order to secure the necessary memory cell current. Only the lowest boosting operation is performed to suppress an increase in power consumption due to useless boosting operation. That is,
The minimum boosted potential is guaranteed and the boosted level is prevented from becoming too high. The control is a mask ROM
The control of the boosting operation can be simplified because it is performed according to the operating state of.

<< Relief Circuit >> The relief circuit 1 is shown in FIG.
An example of 9 is shown. The relief circuit 19 includes address comparison memory arrays 190A and 190B, a memory array 191 that stores data indicating a relief position of 128-bit data output from the sense amplifier circuit 10, and a memory that stores relief bit data. It has an array 192. Each memory array is UV erasable EPRO
Memory cell transistors such as FAMOS for M configuration are arranged in a matrix. The memory cell transistors in each memory array are not particularly limited, but their control gates are coupled to word lines, drains to bit lines, and sources to ground potential. Has been done.

Memory array 190 for address comparison
Each of A and 190B is not particularly limited, but it includes 12 word lines 193A and 193B and 8 bit lines 194.
A, 194B. Bit lines 193A and 193B are coupled on one side to the output terminal of write circuit 195,
On the other hand, it is coupled to the input terminal of the sense amplifier circuit 196. Reference numeral 197 is a word driver. The word driver 197 is supplied with 12-bit address signals A3 to A14. The word driver 197 uses the address signal A3
In a one-to-one correspondence with A14, the word line 193A is driven according to its logical value, and the word line 193B is driven according to its inverted logical value. Word driver 197
The operating power supply of is during the write operation (when programming the relief information)
Is a high voltage Vpp for writing, and a power supply voltage (Vdd) during a read operation (during a read operation for the memory array 2).
It is said. The write data is serially supplied from the data terminal D15. The input mode of the terminal D15 is instructed by the low level of the write control signal / WE, and the serial input of write data is performed in synchronization with the change of / WE. In the program of one address to be relieved,
Write data is applied to one bit line of memory array 193A and one bit line paired with it in memory array 193B. In other words, each memory array 193A, 193B is included in the program of one relief address.
Therefore, one bit line is used for each. For example, addresses to be relieved are A3, A19 = 1, A4 to A13 = 0.
Then, in the memory array 190A, the word line 19
Of the 3A, the memory cells whose control gates are coupled to the word lines corresponding to A3 and A19 are set to the write state (relatively high threshold voltage), and the memory array 190
In B, the memory cells whose control gates are coupled to the word lines corresponding to A4 to A18 among the word lines 193B are set to the write state (relatively high threshold voltage).
In the read operation, when the same address as the programmed address is supplied, the two bit line pairs in the two-sided memory arrays 190A and 190B do not cause a current change because the address does not change. It is a pair of two programmed bit lines. The sense amplifier circuit 196 sets the corresponding output bit to the high level when the two bit line pairs are aligned and no current change occurs. Although details of the sense amplifier circuit 196 are not illustrated, a sense amplifier is provided for each bit line, and a value obtained by taking a logical product of outputs of a pair of sense amplifiers corresponding to the bit line pair is obtained. It should be understood that it is output as the corresponding bit of the sense amplifier circuit 196. The output 205 of the sense amplifier circuit 196 is 8 bits. Reference numeral 198 is an OR gate, which forms a signal 199 obtained by ORing the 8-bit output 205 of the sense amplifier circuit 196.

The memory array 191 has eight word lines 200 and seven bit lines 201. Bit line 20
One is coupled to the output terminal of the write circuit 202 on the one hand and to the input terminal of the sense amplifier circuit 203 on the other hand. Reference numeral 204 is a word driver. The 8-bit signal 205 output from the sense amplifier circuit 196 is supplied to the word driver 204. The word driver 204 drives the word line corresponding to the signal having the logical value "1" among the 8-bit signals supplied thereto to the selection level. In other words, the 8-bit signal 205 can be regarded as the selection signal of the word line 200 for the memory array 191. Word driver 204
The operating power supply of is during the write operation (when programming the relief information)
Is a high voltage Vpp for writing, and a power supply voltage Vdd during a read operation (during a read operation for the memory array 2). The write data is serially supplied from the data terminal D15. The input mode of the terminal D15 is instructed by the low level of the write control signal / WE, and the serial input of write data is performed in synchronization with the change of / WE.
The write circuit 202 serially inputs 7-bit data in advance. Then, data writing is performed in parallel for 7 bits for one word line. This write data is
This is information for specifying the bit position for the 128-bit output of the sense amplifier circuit 18 with 7-bit data. The sense amplifier circuit 203 is the memory array 19
The read data from 1 is detected and amplified. A decoder 206 decodes the 7-bit output of the sense amplifier circuit 203. The decoder 206 outputs the signal 199.
Is set to a logical value "1", in other words, when the access address for the memory array 2 matches the address to be rescued programmed in the memory arrays 190A and 190B. The decode output 207 of the decoder 206 is set to the non-selection level when it is in the inactive state, and one of the 128 decode outputs 207 is set to the select level in the active state. The 128 decoded signals 207 are supplied to the multiplexer 20. The 128 decoded signals 207 are in one-to-one correspondence with the 128-bit data from the sense amplifier circuit 18, and the multiplexer 20 replaces the 1-bit data corresponding to the selected-level decode signal with the rescue data 210. It is supplied to the page selection circuit 22.

The memory array 192 has eight word lines 211 and 32 bit lines 212. Bit line 2
12 is coupled to the output terminal of write circuit 213 on the one hand and to bit line selection circuit 214 on the other hand. Reference numeral 215 is a word driver. The word driver 215 is supplied with the 8-bit signal 205 output from the sense amplifier circuit 196. Word driver 2
15 is the logical value of the 8-bit signal supplied to it.
The word line corresponding to the signal set to "1" is driven to the selection level. In other words, the 8-bit signal 205 is driven.
Can be regarded as a selection signal of the word line 211 for the memory array 192. The operating power supply of the word driver 215 is a high voltage Vpp for writing during a writing operation (when programming relief information), and during a reading operation (memory array 2).
To the power supply voltage Vdd.
The write data is serially supplied from the data terminal D15. The input mode of the terminal D15 is the write control signal /
Instructed by the low level of WE, the serial input of write data is performed in synchronization with the change of / WE. The write circuit 213 serially inputs 32-bit data in advance. Then, data writing is performed in parallel for 32 bits for one word line. This write data is used as relief bit data. The 32-bit data read from the memory array 192 is the bit line selection circuit 21.
Any one bit is selected by 4. The selection operation in the bit line selection circuit 214 is controlled by 32 decode signals supplied from the decoder 216. The decoder 216 corresponds to the address signals A15 to A19.
The bit address information is decoded to form a decode signal. The 1-bit data selected by the bit line selection circuit 214 is amplified by the sense amplifier 217, and its output is supplied to the multiplexer 20 as repair data 210. According to the relief circuit 19, W1 to W32
Defective bits can be repaired in units of two word lines, and a maximum of 8 × 32 = 256 defective bits can be repaired.

As shown in FIG. 1, the relief circuit 19 of the present embodiment is arranged in the preceding stage of the page selection circuit 22 so that it can be replaced with the relief data. Therefore, it is not necessary to change the operation state of the relief circuit 19 in the burst read performed by changing the address signals A0 to A2. Therefore, the burst read operation speed can be kept constant regardless of whether or not the read target data includes a bit to be relieved, which contributes to speeding up of the burst read operation. If the defective bit is replaced on the output side of the page selection circuit 22, the relief circuit must be newly operated every time the address signals A0 to A2 are changed during the burst read, and the burst read operation is performed. I'll be late.

<< Direct Precharge >> FIG. 11 shows a circuit configuration for precharging the bit lines and the source lines of the memory array, centering on the memory array 2 and the dummy memory array 32. Dummy memory array 32
Is configured by the same circuit configuration as the circuit configuration related to the pair of bit lines and source lines in the memory array 2, and includes dummy bit line DBL, dummy source line DSL, dummy sub-bit lines DSB1 to DSB4, dummy memory cell transistor DQM, and dummy. Select MOS transistor DQds
1, DQds2, DQss1, DQss2. Word lines W1 to W3 of each memory block MBLK
2, the select lines DS1, DS2, SS1, SS2 are shared with the dummy memory array 2. Although not particularly limited, the dummy memory cell transistor DQM has a threshold value having a relatively high threshold voltage and always turned off.

The source line selection circuit 14 uses the source line SL.
N-channel type selection MOS transistor QS1 for selectively bringing 1, SL2, SL3, ... To the ground potential Vss.
Are provided in one-to-one correspondence with the source lines SL1, SL2, SL3, ..., These are decoded signals (source line selection signals) YS1, output from the source line Y decoder 15.
Switch control is performed by YS2, YS3, .... One of the source line selection signals YS1, YS2, YS3, ... Is set to the selection level according to the address signals A3 to A6. As is clear from the number of bits of the address signals A3 to A6, the source line selection circuit 14 is configured to include a plurality of sets of the same circuits for every 16 source lines.

The source line precharge circuit 31 is a circuit for precharging the source lines that are not selected by the source line selection signals YS1, YS2, YS3, ... n-channel MOS
The transistor QL1 and the p-channel type MOS transistor QP1 are arranged in series, and each MOS transistor Q
P1 is switch-controlled by source line selection signals YS1, YS2, YS3, .... MOS transistor Q
L1 functions as a resistor for determining the precharge level of an unselected source line, and its gate bias voltage is formed by a dummy source line precharge circuit 33 whose details will be described later.

The bit line selection circuit 12 uses the bit line BL
1, BL2, BL3, ... Selectively sense amplifier circuit 1
The n-channel selection MOS transistor QS2 that is turned on is connected to the bit lines BL1, BL2, BL3, ...
The bit line Y decoder 1 is provided correspondingly.
Decode signal (bit line selection signal) Y output from 3
Switch control is performed by D1, YD2, YD3, .... The bit line selection signals YD1, YD2, YD3, ...
Any one of them is set to the selection level according to the address signals A3 to A6. As is clear from the number of bits of the address signals A3 to A6, the bit line selection circuit 12 also includes a plurality of sets of the same circuits for every 16 bit lines.

The bit line precharge circuit 30 is a circuit for precharging bit lines which are not selected by the bit line selection signals YD1, YD2, YD3, ... n-channel MOS
The transistor QL2 and the p-channel type MOS transistor QP2 are arranged in series, and each MOS transistor Q
P2 is switch-controlled by bit line selection signals YD1, YD2, YD3, .... MOS transistor Q
L2 functions as a resistor for determining the precharge level of the non-selected bit line, and its gate bias voltage is formed by the dummy bit line precharge circuit 34 described later in detail.

The sense amplifier circuit 18 includes 128 sense amplifiers, one for every 16 bit lines. In FIG. 11, one sense amplifier 180 is representatively shown. The sense amplifier 180 has its input node N
MOS transistor Q1 for precharging in
1 to Q13, and transistors Q14 to Q17 forming a detection stage circuit for detecting a current change of the input node Nin.
And MOS transistors Q18 and Q19 for CMOS inverter configuration for outputting the detection result.
Although the power switch MOS transistor for cutting off the current through path between the power supply voltage Vdd and the ground potential Vss is not shown, it is actually controlled to be in the cutoff state in the power down mode.
Further, a power switch MOS transistor for activating the sense amplifier at an activation timing synchronized with the address transition detection pulse φATD is provided.

The n-channel type MOS transistor Q
The conductance of 12 is determined by the level of the input node Nin, and the divided voltage obtained at the coupling node of the MOS transistor Q12 and the p-channel MOS transistor Q11 is the n-channel MOS transistor Q13.
Is received by the gate, which causes the MOS transistor Q1
The conductance of 3 is negatively feedback controlled by the level of the input node Nin to precharge the input node Nin. The conductance of the n-channel type MOS transistor Q15 in the detection stage is determined by the level of the input node Nin,
The divided voltage obtained at the connection node with the channel MOS transistor Q14 is transferred to the n-channel MOS transistor Q.
17 receives at the gate. This MOS transistor Q17
Are arranged in series with the p-channel MOS transistor Q16 between the input node Nin and the power supply voltage Vdd. The conductance of the MOS transistor Q17 is negatively feedback controlled according to the level of the input node Nin to precharge the input node Nin.

In the state where the precharged charge of the input node Nin is held, the MOS transistor Q1
The conductance of 7 is made small, and the output Sout of the sense amplifier is made low level. On the other hand, when the precharged charges of the input node Nin flow to the ground potential via the bit line and the source line, the conductance of the MOS transistor Q17 which is negatively feedback controlled by the level change is increased, and the output So of the sense amplifier is increased.
ut is inverted to high level.

The detection stage circuits Q14 to Q17 also have a function of precharging the input node Nin, but in order to accelerate the precharge speed for the input node Nin, a precharge circuit composed of the MOS transistors Q11 to Q13 is used. It is provided. Therefore, in order to prevent the circuit including the MOS transistors Q11 to Q13 from adversely affecting the detection operation, the MOS transistor Q11
The threshold voltage of the MOS transistor Q13 is set relatively high, and when a certain precharge level is obtained, the MOS transistor Q13
Is to be cut off.

The reason why the source line precharge circuit 31 and the bit line precharge circuit 30 precharge the unselected source lines and the unselected bit lines is as follows. That is, the sense amplifier 180 inverts the output Sout when the charge of the input node Nin is extracted to the ground potential Vss. Therefore, it is necessary to prevent an undesired current from flowing from the selected bit line to the unselected bit line or the unselected source line adjacent thereto. For example, assuming that the bit line BL2, the select lines DS1 and SS1, and the word line W1 are selected, the bit line BL2 and the non-selected bit line BL3 adjacent to the bit line BL2 have four memory cell transistors QM.
When the threshold voltage of (a, b, c, d) is low, it is conducted. Similarly, the bit line BL2 and the non-selected source line SL3 adjacent thereto are rendered conductive when the threshold voltages of the three memory cell transistors QM (a, b, c) are low. The memory array 2 is brought into conduction.
It is difficult to avoid because it is determined by the memory information of. When a current flows from the selected bit line when the selected bit line is electrically connected to the unselected source line or the unselected bit line, the sense amplifier 180 erroneously detects the read data, or it takes time to determine the output. . To avoid this, precharge the unselected source line and the unselected bit line so that even if the selected bit line and the unselected source line or the unselected bit line become conductive, the current does not flow from the selected bit line. I have to.

Particularly, in this embodiment, the precharge level of the non-selected bit line and the non-selected source line is adjusted to the precharge level of the selected bit line, and the precharge level is set to the precharge level required by the sense amplifier 180. It has adopted a device that enables highly accurate adjustment. That is, the dummy precharge circuits 33 and 34
Is a detection stage circuit of the sense amplifier 180 (Q14 to Q17)
It has the same precharge performance as. This is because the precharge level required by the sense amplifier for the detection operation is determined by the detection stage circuit (Q14 to Q17).

As a concrete example, in the dummy precharge circuit 34, the MOS transistors Q24 to Q27 are
It has the same circuit coupling as the MOS transistors Q14 to Q17 of the sense amplifier and has a transistor size substantially equal to that of the corresponding transistor. The conductance of the n-channel MOS transistor Q25 is determined by the level of the dummy bit line DBL, and the divided voltage obtained at the node between the MOS transistor Q25 and the p-channel MOS transistor Q24 is n.
Channel type MOS transistor Q27 receives at the gate. This MOS transistor Q27 is a p-channel MO
It is arranged in series between the dummy bit line DBL and the power supply voltage Vdd together with the S transistor Q26. The MOS
The voltage obtained at the drain of the transistor Q25 is used as the gate bias voltage 340 of the MOS transistor QL2 of the bit line precharge circuit 30. The MOS transistors Q29 and Q28 are transistors for deactivating the dummy precharge circuit 34 in the power down mode, and are transistors that do not substantially participate in the determination of the gate bias voltage. After the power is turned on, the dummy bit line DBL is used unless the power down mode is set.
Keeps the precharge level steady.

The non-selected bit line is precharged through the MOS transistor QL2 receiving the gate bias voltage 340 and the MOS transistor QP2 connected in series to the MOS transistor QL2. As is clear from the coupling relation between the MOS transistors Q26 and Q27 of the dummy precharge circuit 34 and the dummy bit line DBL, and the coupling relation between the MOS transistors QP2 and QL2 of the bit line precharge circuit 30 and the bit line, both circuits are shown. If the transistors in 34 and 30 have the same size, and the dummy bit line and the non-selected bit line have substantially the same load condition,
The precharge level of the non-selected bit line is substantially the same as the precharge level of the dummy bit line DBL, in other words, the precharge level required by the sense amplifier (which is also the precharge level of the selected bit line). Are the same. By design, when the load conditions of the dummy bit line DBL and the non-selected bit line do not match, the MOS transistor Q26 of the dummy precharge circuit 34,
For Q27, the MO of the bit line precharge circuit 30
The precharge level of the non-selected bit line can be matched with the precharge level required by the sense amplifier 180 by simply determining the transistor sizes of the S transistors QP2 and QL2 appropriately.

Dummy precharge circuit 33 on the source line side
Is exactly the same for the MOS transistor Q34
To Q37 are MOS transistors Q14 of the sense amplifier
~ Q17 with the same circuit coupling and configured with a transistor size substantially equal to the corresponding transistor. The conductance of the n-channel type MOS transistor Q35 is determined by the level of the dummy source line DSL, and the divided voltage obtained at the node between the MOS transistor Q35 and the p-channel type MOS transistor Q34 is supplied to the n-channel type MOS transistor Q37. Get to the gate. This MOS transistor Q37 is arranged in series between the dummy source line DSL and the power supply voltage Vdd together with the p-channel MOS transistor Q36.
The voltage obtained at the drain of the MOS transistor Q35 is used as the gate bias voltage 330 of the MOS transistor QL1 of the source line precharge circuit 31. MOS
The transistors Q39 and Q38 are transistors for deactivating the dummy precharge circuit 33 in the power down mode, and are transistors that do not substantially participate in the determination of the gate bias voltage. After the power is turned on, the dummy source line DSL constantly maintains the precharge level unless the power down mode is set.

The non-selected source line is precharged via the MOS transistor QL1 receiving the gate bias voltage 330 and the MOS transistor QP1 connected in series to it. As is clear from the coupling relation between the MOS transistors Q36 and Q37 of the dummy precharge circuit 33 and the dummy source line DSL, and the coupling relation between the MOS transistors QP1 and QL1 of the source line precharge circuit 31 and the bit line, both circuits are If the transistors 33 and 31 have the same size and the load conditions of the dummy source line and the non-selected source line are substantially the same,
The precharge level of the non-selected source line is substantially the same as the precharge level of the dummy source line DSL, in other words, the precharge level required by the sense amplifier 180 (also the precharge level of the selected bit line). Substantially the same. By design, dummy source line DSL
If the load conditions of the non-selected source line do not match,
MOS transistor Q3 of the dummy precharge circuit 33
6 and Q37, the transistor size of the MOS transistors QP1 and QL1 of the source line precharge circuit 31 is appropriately determined to match the precharge level of the non-selected source line with the precharge level required by the sense amplifier 180. Can be made.

As described above, the dummy precharge circuits 33 and 34 having precharge characteristics substantially equal to those of the detection stage circuits (Q14 to Q17) of the sense amplifier 180, and the dummy equivalent to the basic circuit configuration of the memory array. The memory array 32 is provided, and the dummy bit lines DBL and the dummy source lines DSL can be obtained by the dummy precharge using the voltages 330 and 340 obtained when the dummy precharge circuits 33 and 34 are constantly precharged. Since a precharge level equivalent to the precharge level is formed in the non-selected source line and the non-selected bit line, the precharge level of the non-selected bit line and the non-selected source line is the precharge required by the sense amplifier 180. It can be adjusted to the level accurately. Therefore, it is possible to prevent the sense amplifier 180 from erroneously detecting read data due to an undesired current flowing from the selected bit line to the unselected bit line or the unselected source line. Furthermore, when the unselected bit line is changed to the selected state, the level of the selected bit line is already
Since it is accurately adjusted to the level required by the sense amplifier 180, the sense amplifier 180 does not substantially need to positively precharge the selected bit line, and high-speed operation of the sense amplifier can be guaranteed. The prevention of erroneous detection can be realized with high accuracy. In addition, since the bias signals 330 and 340 for precharging are formed via the circuits 32, 33 and 34 which are equivalent to the actual circuits, the above effect can be obtained without being affected by the process variations.

<< NAND Type Mask ROM >> FIG. 12 shows a basic circuit configuration of one memory block in the NAND type mask ROM. N illustrated in FIG.
The AND-type mask ROM is provided with two series connection circuits (memory cell columns) ML1 and ML2 of a plurality of memory cells QMM with respect to one bit line BL1.
One ends of L1 and ML2 are connected to the ground potential Vss, and the series circuit ML is connected.
The other end of 1 is connected to the bit line BL1 via the select MOS transistor Qds1, and the other end of the series circuit ML2 is connected to the bit line BL1 via the select MOS transistor Qds2. Such a memory cell arrangement is actually repeated many times in the lateral direction of the paper surface of FIG. 12 to form one memory block. Select MOS transistor Qd
s1 is switch-controlled by the select line DS1, and the select MOS transistor Qds2 is selected by the select line DS2.
Switch controlled by. The gate of memory cell transistor QMM is coupled to word lines W1 to W16 arranged corresponding to each row.

The memory cell transistor QMM stores information according to whether it is a depletion type or an enhancement type. The word line to be selected by the address signal is driven to the non-selection level of the memory cell, and the word line to be unselected by the address signal is driven to the selection level of the memory cell, so that the memory cell column (ML1, The stored information is read depending on whether or not a direct current path is formed in ML2). At this time, either one of the memory cell columns ML1 or ML2 is selected by the select lines DS1 and DS2.

The memory mat is constructed by arranging a plurality of memory blocks MBLK of FIG. 12 in the vertical direction of the paper surface. For example, as shown in FIG. 13, one memory mat is composed of eight memory blocks MBLK (# 1 to # 8).

In order to sufficiently increase the conductance of the memory cell transistor QMM to be turned on, boosting the word selection level is convenient for speeding up the read operation. At this time, the NAND-type mask ROM selects one of the two memory cell columns ML1 and ML2 by the select MOS transistors Qds1 and Qds2 and connects it to the bit line. Therefore, the select MOS transistor selected by the select line is also interposed in the current path from the bit line to the ground potential Vss. The select MOS transistors Qds1 and Qds2 have substantially the same size as the memory cell transistor QMM due to the configuration of the memory array. Therefore, even if only the selection level of the word line that selects the memory cell transistor QMM is boosted, the change in current that can be detected by the sense amplifier 180 cannot be increased (the read operation cannot be speeded up). Considering this, the word line W
Select lines DS1 and DS with selection levels 1 to W16
The selection level 2 of 2 is also set to the boost level VCH boosted by the boost circuit 5. By boosting the select line selection level together with the word line selection level above the power supply voltage, the current flowing through the bit line during data read increases,
In other words, the change in current through the bit line becomes faster, which allows the sense amplifier 180 to immediately detect the change in current and increase the data read speed.
This situation is the same as in the case of the NOR type mask ROM.

According to the example of FIG. 13, in the read operation,
Eight memory blocks MBL sharing bit lines with each other
The select line is selected in one memory block MBLK from K, and the selecting operation of the word lines W1 to W16 is commonly performed in eight memory blocks MBLK. As a result, it is possible to reduce the number of word drivers and thereby reduce the chip occupation area. In FIG. 13, eight memory blocks MBL are shown.
Driver D corresponding to K (# 1) to MBLK (# 8)
W111 and WD101 are representatively shown. In the figure, the decoder 500 includes the decode logics of the word line and the select line all in one. The decode logic shown therein is just an example. The drivers DW111 and WD101 typically shown in FIG. 13 are the same as those described based on FIG. 4, and the boosted voltage V supplied to them is the same.
CH is also supplied from the same circuit as the booster circuit 5. FIG.
3, the output of the decoder 500 has a low level as a selection level. In the driver WD101, when the output signal line SW1 is at the non-selection level (high level), the transistor Q3 is turned on, whereby the word line W1 is at the non-selection level ground potential Vss.
To be. When the output signal line SW1 is at the selection level (low level), the transistors Q2Q3 are cut off, whereby the boosted potential VCH as the selection level is supplied to the word line W1.

In such a NAND type mask ROM, memory cells are driven by driving all the select signal lines to be selected and the non-selected word lines except the word lines to be selected by the address signal with the boosted voltage VCH. The current value flowing in the sense amplifier 18 can be increased.
The detection of the current change due to 0 becomes faster, and the access can be speeded up.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

For example, the booster circuit may be composed mainly of a circuit which constitutes a self-boost circuit by pulse driving by an ATD circuit and supplements charges consumed by a word line by one charge pump. In this case, timing control is required to prevent loss of charge, but the energy required is minimal. Further, in the NOR type memory array, the number of sub bit lines for one bit line is 4
It is possible to change to a configuration other than a book. Similarly, in the NAND type memory array, it is also possible to have two or more memory cell columns for one bit line. The storage capacity of the memory array, the number of memory mats, and the like can be appropriately changed. The number of word lines driven by one driver is not limited to that in the above embodiment, and can be changed appropriately. As for the booster circuit, the level sense circuit 45 and the oscillator circuit 4
3, the charge pump circuit 40 can be omitted.

In the above description, the case of applying the invention made by the present inventor mainly to the mask ROM which is the field of use which is the background of the invention has been described.
It can also be applied to M, EEPROM, flash memory and the like. Further, the semiconductor memory device according to the present invention is not limited to a single memory LSI, but can be applied to a semiconductor memory device on-chip in a logic LSI such as a microcomputer.

[0090]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

[1] Since the booster circuit is adopted as the power source for selectively driving the memory cell transistor and the select transistor, the current change generated through the selected memory cell transistor and the select transistor is increased,
The detection speed of the sense amplifier that detects the change is improved, and the access speed can be increased.

[2] The booster circuit increases the conductance of the memory cell transistor and the select transistor by making the control gate voltage of the memory cell transistor and the select transistor higher than the power supply voltage, and through the bit line to the bit line. Since an attempt is made to increase the amount of current flowing, it is possible to suppress an increase in power consumption due to useless boosting operation by performing only the minimum boosting operation for securing a necessary memory cell current. Control of the boosting operation can be simplified by performing the control for ensuring the minimum boosted potential and preventing the boosted potential from becoming too high according to the operating state of the semiconductor memory device. ..

[3] The operation state of the relief circuit is changed in the burst read performed by changing the specific address signal by replacing the defective bit data with the relief data in the preceding stage of the page selection circuit for the burst read. It doesn't need to. In other words, the operation time of the relief circuit does not affect the burst access time. As a result, the burst read operation speed is constant regardless of whether or not the read target data includes the bit to be relieved, which contributes to speeding up the burst read operation.

[4] In the NOR type memory array, by providing a circuit for directly precharging the unselected bit lines and the unselected source lines, the sense amplifier does not need to substantially precharge the selected bit lines. At this point, the detection operation of the sense amplifier can be accelerated.

[5] By controlling the precharge level of the unselected bit lines by the dummy precharge circuit equivalent to the detection stage circuit of the sense amplifier, the precharge levels of the unselected bit lines and the unselected source lines are changed. It is easy to accurately adjust to the precharge level required by the sense amplifier. Therefore, the precharge level of the bit line changed from the non-selected state to the selected state is accurately adjusted to the precharge level required by the sense amplifier. As a result, the sense amplifier does not need to substantially precharge the selected bit line and can immediately shift to the detection operation, so that the operation of the sense amplifier can be speeded up. Moreover, it is possible to prevent a situation in which the sense amplifier erroneously detects or delays the detection operation due to an undesired current flowing from the selected bit line to the unselected bit line or the unselected source line. In particular, by using the voltage obtained when the dummy bit line and the dummy source line of the dummy memory array equivalent to the basic circuit configuration of the memory array are constantly precharged by the dummy precharge circuit, By forming the precharge level of the non-selected bit line, the precharge level of the non-selected bit line and the non-selected source line and the non-selected to the selected state are substantially not affected by the process variation. The bit line level can be controlled with high precision to the precharge level required by the sense amplifier.

[Brief description of drawings]

FIG. 1 is a NOR type mask ROM according to an embodiment of the present invention.
2 is an overall block diagram of FIG.

FIG. 2 is a circuit diagram showing a basic configuration of one memory block MBLK in the mask ROM of FIG.

FIG. 3 is a block diagram showing an overall configuration of one memory mat MMAT.

FIG. 4 is an explanatory diagram showing an example of word line and select line drivers and word line drive formats.

FIG. 5 is a block diagram of an example of a booster circuit that forms a drive voltage for a word line and a select line.

FIG. 6 is a circuit diagram of an example of a charge pump circuit included in the booster circuit.

FIG. 7 is a circuit diagram of an example of an oscillator circuit included in a booster circuit.

FIG. 8 is a circuit diagram of an example of a level detection circuit that detects an upper limit level of a boosted voltage.

FIG. 9 is a circuit diagram of an example of a level detection circuit that detects a minimum level required as a boosted voltage.

FIG. 10 is a block diagram of an example of a relief circuit included in a mask ROM.

FIG. 11 is a circuit diagram showing an example of a precharge circuit for precharging bit lines and source lines of a memory array, a dummy memory array, and a dummy precharge circuit.

FIG. 12 is a circuit diagram showing a basic example circuit configuration of one memory block in a NAND mask ROM.

FIG. 13 is an explanatory diagram showing a word line drive format and a driver for word lines and select lines in a NAND mask ROM.

[Explanation of symbols]

2 memory array MMAT memory mat MBLK memory block BL1 to BL256 bit line W1 to W32 word line SL1 to SL257 source line QM memory cell transistor SB1 to SB4 sub bit line DS1, DS2, SS1, SS2 select line Qds1, Qds2, Qss1, Qss2 select Transistor 3 Word driver WD101 to DW832 Word line driver 4 Select line driver DW111 to DW882 Select line driver 5 Booster circuit 40, 41, 42 Charge pump circuit 43, 44 Oscillator circuit 45, 46 Level sense circuit VCH Boosted potential 6 Word line X decoder φATD Address change detection pulse 7 Address change detection circuit 10 Select line X decoder 14 Source line selection circuit 15 Source line Y data 18 Sense amplifier circuit 180 Sense amplifier Q14 to Q17 Detection stage circuit Q24 to Q27 Circuit equivalent to detection stage Q34 to Q37 Circuit equivalent to detection stage 19 Relief circuit 207 Relief position information 210 Relief data 20 Multiplexer 22 Page selection Circuit 23 Page Decoder 30 Bit Line Precharge Circuit 31 Source Line Precharge Circuit 32 Dummy Memory Array 33 Dummy Source Line Precharge Circuit 34 Dummy Bit Line Precharge Circuit 330, 340 Control Voltage Signal

Front page continuation (72) Inventor Teruhisa Takashi 5-201-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitate Cho-LS Engineering Co., Ltd. (72) Inventor Fumio Kojima, Kodaira-shi, Tokyo 5-20-1 Mizumotocho Hitsuru Cho-LS Engineering Co., Ltd. (72) Inventor Yasuhiro Yoshii 5-2-1 Kamisuihoncho, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division ( 72) Inventor Noriyuki Yabushi, 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo, Ltd. Semiconductor Company, Hitachi Ltd. (72) Inventor Toshifumi Takeda 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division (72) Inventor Kikuo Sakai 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitate Cho-LS Engineering Co., Ltd. (72) Inventor Takeshi Wada Kodaira, Tokyo 5-20-1 Joumizuhonmachi, Ichi, Ltd. Hitachi, Ltd. half Conductor Division (72) Inventor Hiroshi Kawamoto 5-201-1, Josuihonmachi, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division

Claims (10)

[Claims] 1. A non-volatile memory cell transistor is connected in series for each word line extending in the X direction by connecting a selection terminal to the word line, and the series connection point of the memory cell transistor is connected in each Y direction. Coupled to the sub-bit line,
A plurality of select transistors for selecting which sub-bit line to form a current path to the bit line with respect to the bit line assigned to each of the plurality of sub-bit lines is provided for each of the plurality of sub-bit lines. A selected memory cell transistor and a select transistor, the word line is driven to a selected level according to an address signal, and a change in current generated through the selected memory cell transistor and the select transistor is sensed. A semiconductor memory device detected by an amplifier is provided with a booster circuit that generates operating power for each of a word line driver that drives the word line to a selection level and a select line driver that drives the select line to a selection level. A semiconductor memory device characterized by being a thing. 2. A plurality of sets of circuits in the X direction in which a plurality of non-volatile memory cell transistors connected in series in the Y direction are connected to a single bit line in a plurality of columns via select transistors. , A memory array in which a word line is coupled to the select terminal of the memory cell transistor for each X direction and a select line is coupled to the select terminal of the select transistor for each X direction is provided. A semiconductor memory device in which a sense amplifier detects a current change generated through a memory cell transistor and a select transistor selected by driving the word line driver to drive the word line to a select level, Each of the operating power supplies for the select line driver that drives the line to the selected level The semiconductor memory device, characterized in that those comprising providing a booster circuit for forming. 3. The booster circuit comprises: a first oscillator circuit; a first charge pump circuit which receives the oscillation output of the booster circuit and boosts a power supply voltage; A first level sense circuit that enables the first oscillation circuit to oscillate in a range defined by the above range; 3. The semiconductor memory device according to claim 1, further comprising: a storage capacitor having a storage electrode commonly connected to output terminals of the first and second charge pump circuits. 4. The booster circuit further receives a second oscillator circuit having an oscillation frequency higher than that of the first oscillator circuit and receives an oscillation output from the second oscillator circuit to perform a boosting operation of a power supply voltage and the output thereof is the storage capacitor. A third charge pump circuit coupled to the second charge pump circuit, and a second level sense circuit that enables the second oscillator circuit to oscillate within a range in which the generated boosted voltage is equal to or lower than the second voltage, 4. The semiconductor memory device according to claim 3, wherein the second voltage has a level lower than that of the first voltage. 5. An external signal input terminal for designating a power-down mode is provided, and in the power-down mode, the first and second level sense circuits respectively correspond to oscillation operations of oscillation circuits. 5. The method according to claim 4, characterized in that
The semiconductor memory device described. 6. A memory array in which a large number of non-volatile memory cell transistors are arranged, a sense amplifier circuit for amplifying parallel data of a plurality of bits read from the memory array and selected, and a predetermined address signal. A semiconductor memory device comprising: a page selection circuit that selects the output of the sense amplifier circuit in units of the number of output bits to the outside, and data can be continuously output to the outside by switching the selection state of the page selection circuit. A relief circuit in which a relief position and relief data for relieving a defective bit included in the memory array are programmed; Replace the bit specified by the relief position information held by The semiconductor memory device, characterized in that those comprising providing a circuit replacing outputting the page selection circuit. 7. A non-volatile memory cell transistor having a NOR type memory array including a large number of memory cell rows arranged in series, in which sources and drains of memory cell transistors adjacent to each other are connected to each other. Select the source line connected to the source and the bit line connected to the drain of the memory cell transistor, connect the selected source line to the ground potential, connect the selected bit line to the sense amplifier, and connect the sense amplifier to the bit line. Is a semiconductor memory device that determines read data depending on whether or not a current is drawn into the sense amplifier, wherein the sense amplifier is configured to increase the conductance of a current control transistor that controls the level of the input node in a negative feedback from the input node to the bit line. Has a detection stage circuit for detecting the current pull-in, and a circuit equivalent to the detection stage circuit A constant voltage is formed by a bit line precharge circuit that receives a voltage that is constantly generated and that precharges a non-selected bit line via a load transistor that uses this voltage as a control voltage, and a circuit that is equivalent to the detection stage circuit. And a source line precharge circuit for precharging a non-selected source line via a load transistor having the control voltage as a control voltage. Semiconductor memory device. 8. A non-volatile memory cell transistor is connected in series for each word line extending in the X direction by connecting a selection terminal to the word line, and the series connection point of the memory cell transistors is arranged in each Y direction. Coupled to the sub-bit line,
A plurality of select transistors are provided for selecting which sub-bit line is assigned to each of the plurality of sub-bit lines and which source line is connected to the sub-bit line adjacent to the sub-bit line. A memory that is provided for each sub-bit line, and a select line for selecting the select transistor is selected together with the word line, so that the bit line and the select line are connected to an adjacent sub-bit line via the selected select transistor. An array; a bit line selection circuit for selecting the bit line; a source line selection circuit for connecting a source line paired with the bit line selected by the bit line selection circuit to a ground potential; and a selection for the bit line selection circuit. In a semiconductor memory device that includes a sense amplifier that detects a state in which a current flows into the generated bit line. A bit line precharge circuit that precharges the bit line that is not selected by the bit line selection circuit, and a source line precharge circuit that precharges the source line that is not selected by the source line selection circuit. A semiconductor memory device characterized by being provided. 9. The memory amplifier includes a detection stage circuit that detects current drawing from an input node to a bit line by increasing conductance of a current control transistor that negatively feedback-controls a level of an input node. A dummy memory array having an equivalent circuit configuration relating to a pair of source lines and bit lines, and a circuit equivalent to the detection stage circuit, whereby a dummy source line included in the dummy memory array is precharged. A source line precharge circuit is provided, and a dummy bit line precharge circuit that has a circuit equivalent to the detection stage circuit and that precharges a dummy bit line included in a dummy memory array is provided. The circuit is equivalent to the detection stage circuit included in the dummy source line precharge circuit. A load transistor that receives a control voltage of a current control transistor included in the path as a bias voltage for determining a precharge level, and the bit line precharge circuit includes the detection circuit included in the dummy bit line precharge circuit. 9. The load circuit according to claim 8, further comprising a load transistor that receives a control voltage of a current control transistor included in a circuit equivalent to the stage circuit as a bias voltage for determining a precharge level. Semiconductor memory device. 10. An input terminal for an external signal for instructing a power down mode, wherein in the power down mode, the dummy source line precharge circuit and the dummy bit line precharge circuit are the detection stage circuits. And a transistor that cuts off a DC current path of a circuit equivalent to the above circuit, and a transistor that cuts off a load transistor included in the bit line precharge circuit and the source line precharge circuit. The semiconductor memory device according to claim 9.