JP4808838B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device including a sense amplifier, and more particularly to a semiconductor memory device that does not become sense amplifier discipline and can shorten the read time.
[0002]
[Prior art]
Conventionally, as a semiconductor memory device that does not become sense amplifier discipline, for example, there is a method described in Japanese Patent Laid-Open No. 11-288594 previously proposed by the present applicant.
That is, as shown in FIG. 5, the address signal is serially input in synchronization with the clock, the address signal excluding the least significant bit is output to the corresponding column decoder or row decoder, and the address excluding the least significant bit is output. After all the data of the memory cell specified by the signal is selected and the data determination operation is performed by the sense amplifier / latch circuits 61 and 62, the selection unit 85 selects the sense amplifier / latch circuit 61 or 62 according to the value of the least significant bit. Data determined by the input address signal is read out by selectively outputting the final result.
[0003]
[Problems to be solved by the invention]
However, in the above conventional semiconductor memory device, when the sense amplifier / latch circuits 61 and 62 operate, it is necessary to discharge the parasitic capacitance of the bit line. There is a problem that it is slower than reading in the case of 1 ″.
[0004]
In practice, a plurality of sense amplifier / latch circuits are required even though any one sense amplifier / latch circuit is selected and its output signal is output as a signal corresponding to the designated address signal. There is a problem.
Accordingly, the present invention has been made paying attention to the above-mentioned conventional unsolved problems, and an object of the present invention is to provide a semiconductor memory device that does not become a sense amplifier discipline that can shorten the read time. .
[0005]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor memory device according to claim 1 of the present invention outputs data stored in a memory cell corresponding to an N-bit (N is a natural number) address signal inputted serially. A device that serially inputs the N-bit address signal and decodes the M-bit address signal (M is a natural number 1 ≦ M ≦ N−1) from the first serially input address signal. A decoder for selecting all the memory cells indicated by the address signal, and an activating means for activating a bit line connected to the memory cell indicated by the M-bit address signal selected by the decoder; based on the address signal and the sense amplifier signals except for M bits of decoding of the N bit address signal, which is activated by said active means bicycloaryl A bit line selection means for selecting a bit line to be connected to the sense amplifier of the bets line, the sense amplifier signal data determination operation was carried out definite results for the bit line selected by it and said bit line selection means and activated by And a sense amplifier signal that is output as a trigger when all the N-bit address signals are input to the decode unit, and the activation means is the bit line selection means The bit line is activated prior to the timing at which the selection operation is performed for a predetermined time set based on the timing at which the bit line selection operation is performed.
[0006]
According to a second aspect of the present invention, there is provided a semiconductor memory device for outputting data stored in a memory cell corresponding to an N-bit (N is a natural number) address signal input serially . A memory in which an address signal is serially input and an M-bit address signal (M is a natural number of 1 ≦ M ≦ N−1) is decoded from the first address signal of the address signal, and the address signal indicates A decoding unit for selecting all cells;
Activating means for activating a bit line connected to a memory cell indicated by the M-bit address signal selected by the decoding unit; an address signal and a sense amplifier excluding the decoded M-bit from the N-bit address signal; based on the signal, and the bit line selecting means for selecting a bit line to be connected to the sense amplifier of the active bit line at the active unit, wherein the active state by the sense amplifier signal is selected and by the bit line selection means A sense amplifier unit that performs a data determination operation on the bit line and outputs a determination result, and the sense amplifier signal is triggered when all the N-bit address signals are input to the decode unit. is, the active means, after the end of input address signals of the M bit in the decoding section In addition, the bit line is activated at least prior to the processing time required for the discharge of the bit line associated with the data determination operation of the sense amplifier section before the selection operation by the bit line selection means. It is a feature.
[0007]
In the invention according to claim 1 or claim 2, among the _N- bit address signals (A _{N-1 to} A ₀ ) that are natural numbers, the first serially input M bits (M is 1 ≦ M ≦). (N-1 natural number) address signals (A _{N-1 to} A _N-M ) are decoded, and all the memory cells indicated by the address signals (A _{N-1 to} A _N-M ) are decoded by the decoding unit. Selected. Then, the selected bit line connected to the memory cell indicated by the address signal of M bits are active, the address signal and the N-bit address signals except the decoded M bits of the N bits of the address signal The bit line of the address specified by the address signal excluding the decoded M bits out of the activated bit lines based on the sense amplifier signal that is output when triggered by the input to the decoding unit Is selected as a bit line to be connected to the sense amplifier, and the data determination operation is performed in the sense amplifier unit for the selected bit line, and the data of the designated address signal (A _{N-1 to} A ₀ ) is stored. Reading is performed.
[0008]
Here, after the decoding unit selects all the memory cells designated by the address signals (A _{N-1 to} A _NM ) and activates the bit lines, among these bit lines, the address signals (A _{NM to} A ₀ ) are selected. The bit line specified in (1) is selected and supplied to the sense amplifier unit, and the determination operation is performed.
Therefore, even if a parasitic capacitance is generated in the bit line, the discharge of the bit line is started when the bit line is activated. Therefore, the processing time required for the discharge can be shortened according to the activation timing. Thus, it becomes possible to realize a semiconductor memory device that does not become sense amplifier discipline.
[0009]
For example, if the bit line is activated for a predetermined time before the bit line selection operation by the bit line selection means, the discharge has already started at least when the bit line selection operation is performed by the bit line selection means. Therefore, it is possible to reduce the processing time required for the discharge during the definite operation in the sense amplifier unit.
[0010]
In particular, after the input of the M-bit address signal in the decoding unit, and before the processing time required for the discharge accompanying the operation of the sense amplifier at least before the start time of the selection operation in the bit line selection means, the bit line When the activation of the sense amplifier is performed, when the operation of determining the sense amplifier is performed, since the discharge of the bit line has been completed, the operation can be promptly shifted to the operation of determination.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram of a semiconductor memory device according to the present invention.
The address signals, A ₇ and 8-bit up to A _0, the A ₇ and the most significant bits, the A ₀ and the least significant bits, the upper address _{A 7 ~A 4, A 3 ~A} 1 the lower side The address A ₀ is described as an LSB address.
[0012]
This semiconductor memory device includes a shift register 11 that serially inputs an address signal in synchronization with a clock signal, and a lower address (A _{3 to} A ₁ ) among the address signals from the shift register 11 to the column decoder 33. The address buffer 21 that outputs the upper address (A _{7 to} A ₄ ) to the row decoder 34 and the LSB address (inverted A ₀ or A ₀ ) to the LSB decoder 35, and the lower address according to the pre-sense signal A column decoder 33 for selecting the signal lines CL0 to CL7 corresponding to the address, a row decoder 34 for selecting the signal lines WL0 to WLm corresponding to the higher address according to the pre-sense signal, and a signal line LS0 according to the LSB address Or an LSB decoder 35 for selecting either LS1 and a memory cell group 5 having a plurality of memory cells 1, a bit line transfer gate 41, a set of signal lines BL 0 to BL 7 corresponding to one word from the bit line transfer gate 41 according to the signal line LS 0 or LS 1 selected by the LSB decoder 35, and one word And a sense amplifier / latch circuit that performs a data determination operation on the output signals SL0-SL7 of the selection unit 85 in accordance with the sense amplifier signal. 65, and an output buffer 71 that sequentially outputs the output signals of the sense amplifier / latch circuit 65.
[0013]
The LSB decoder 35 includes, for example, two AND circuits 35a and 35b, and the LSB address A ₀ from the address buffer 21 is input to one AND circuit, for example 35a, and the inverted signal of the LSB address A ₀ is the other AND circuit. 35b. Further, a sense amplifier signal is input to each of the AND circuits 35a and 35b. In the AND circuit 35a, when both the sense amplifier signal and the LSB address A ₀ are at “H” level, the output LS1 signal is set to “H”. "output as the level select signal line LS1, in the aND circuit 35b, an inverted signal of the sense amplifier signal and the LSB address a ₀ are""a LS0 signal which is the output signal when a level" H H " As a level, the signal line LS0 is selected.
[0014]
The sense amplifier / latch circuit 65 includes a sense amplifier corresponding to a signal line for one word, in this case, eight sense amplifiers. Each of the data is amplified by the sense amplifier to determine “1” or “0”, and the determined data is latched. The latched 8-bit parallel data is parallel / serial converted and output to the output buffer 71.
[0015]
The sense amplifier signal is a signal for activating the sense amplifier, and the sense amplifier / latch circuit 65 is activated when the sense amplifier signal is at "H" level. The pre-sense signal is a signal for bringing the memory cell into the same state as when reading stored data, although the sense amplifier is in an inactive state. Specifically, the selection gate of the memory cell is turned on. This is a signal for setting a state, applying a read voltage to the gate of the memory cell, and setting the source of the memory cell to the GND level.
[0016]
When the semiconductor memory device is a circuit that operates at the falling edge of the clock signal and its period is T, the pre-sense signal is the falling edge of the clock signal next to the clock signal from which the LSB address has been read. It is set to be “H” level at the time before 3 / 2T period at most, and to “L” level when the LSB address reading period T ends. Further, the sense amplifier signal becomes “H” level at least T / 2 cycles before the falling edge of the clock signal next to the clock signal from which the LSB address has been read, and the LSB address read cycle T ends. At this time, it is set to become “L” level.
[0017]
Therefore, for example, “H” is triggered by the next rising edge of the clock signal delayed by T / 2 (T is the period of the clock signal) from the falling edge of the clock signal at which the supply of the address signal A ₁ to the address buffer 21 is started. Output as a level. In addition, the sense amplifier signal is output as an “H” level triggered by the rise of the clock signal one cycle (T) after the rise of the pre-sense signal, and the pre-sense signal and the sense amplifier signal are output at the next fall of the clock signal. Both are reset to "L" level. The pre-sense signal and the sense amplifier signal are generated by, for example, generating a timing signal triggered by the address buffer 21 receiving the address signal A ₁ and generating the pre-sense signal and the sense amplifier signal based on the timing signal. Generated.
[0018]
FIG. 2 is a configuration diagram of the bit line transfer gate 41 and the memory cell group 51. Assuming that any one of the signal lines WL0 to WLm is selected by the row decoder 34, if any one of the signal lines CL0 to CL7 is next selected by the column decoder 33, the most recent address signal is output. Selection of 8-bit data stored in the memory cell mat to be selected when the lower address A ₀ is “1” is constituted by a multiplexer via the bit line transfer gate 41 corresponding thereto, for example, the transfer gate B3 The 8-bit data stored in the memory cell mat to be selected when the lowest address A ₀ is “0” is sent to the selection unit 85 via the transfer gate B4, for example. It has become.
[0019]
Then, the selection unit 85, in response to the signal LS0 or LS1 from the LSB decoder 35, the signal of one word consisting of 8 bits from the transfer gate B3 or B4 corresponding to LS0 or LS1 selected by the LSB decoder 35. One of the sets is selected, and these are sequentially output to the sense amplifier / latch circuit 65.
As shown in FIG. 1, the selector 85 connects the drains and sources of the P-type MOSFET 80 and the N-type MOSFET 81, and two pairs of FET pairs in which the drains and sources of the P-type MOSFET 82 and the N-type MOSFET 83 are connected. It is composed of The two sets of FET pairs are provided corresponding to the plurality of sense amplifiers constituting the sense amplifier / latch circuit 65, respectively.
[0020]
As shown in the schematic diagram of FIG. 3, one of the two pairs of FETs, for example, a pair of FETs composed of P-type and N-type MOSFETs 80 and 81 includes a transistor constituting the bit line transfer gate 41. Of these, the transistors corresponding to the same bit when the LSB address A ₀ when each signal line CL is selected is “0” are connected. That is, in FIG. 3, when for example the signal line CL0 a column decoder 33 is selected, corresponds to 1 bit for example when the LSB address A ₀ is "0" when the signal line CL0 is selected by the column decoder 33 When the signal line CL5 is selected by the column decoder 33, a signal corresponding to the first bit when the signal line CL5 is selected is output to the FET pair 81, 82. It has come to be.
[0021]
Similarly, in the FET pair constituted by the P-type and N-type MOSFETs 82 and 83, the LSB address A ₀ when each signal line CL is selected among the transistors constituting the bit line transfer gate 41 is “1”. Each transistor corresponding to the same bit is connected.
The signal LS0 from the AND circuit 35b is input to the gate of the P-type MOSFET 80 and the gate of the N-type MOSFET 83, and the signal LS1 from the AND circuit 35a is input to the gate of the N-type MOSFET 81 and the gate of the P-type MOSFET 82. and each MOSFET80~83 is activated in response to LS1, the data from the signal line BL corresponding to the LSB address a ₀ is adapted to be supplied to the sense amplifier and latch circuit 65.
[0022]
Here, the address buffer 21, the column decoder 33, and the row decoder 34 correspond to a decoding unit. In the column decoder 33 and the row decoder 34, a process for activating a memory cell in response to a pre-sense signal corresponds to an activation unit, and an LSB decoder 35. The selection unit 85 corresponds to the bit line selection means, and the sense amplifier / latch circuit 65 corresponds to the sense amplifier unit.
[0023]
Next, the operation of the above embodiment will be described based on the timing chart of FIG.
The upper address and lower address of the 8-bit address signal are sequentially supplied to the shift register 11 as serial signals in synchronization with the clock signal, and when the address signals A _{7 to} A ₁ are supplied, the shift register 11 The serial address signal is converted into a parallel signal and sent to the address buffer 21. At this time, the LSB address A ₀ has not been supplied yet.
[0024]
The address buffer 21 outputs lower addresses A _{3 to} A ₁ to the column decoder 33 and outputs upper addresses A _{7 to} A ₄ to the row decoder 34.
The column decoder 33 and the row decoder 34 decode the input addresses, respectively, but since the pre-sense signal is at the “L” level at this time, the signal lines CL and WL are not selected, that is, the signal lines CL and WL maintains the “L” level.
[0025]
When the address signal A ₁ is supplied from the shift register 11 to the address buffer 21 at time t ₁ , the pre-sense signal is output to the column decoder 33 and the row decoder 34 as “H” level using this as a trigger.
In the column decoder 33 and the row decoder 34, when the pre-sense signal becomes “H” level, one of the signal lines CL0 to CL7 and WL0 to WLm corresponding to the decoded address signal is selected and output as “H” level. Then, a read voltage is applied to the gate of the memory cell to control the source of the memory cell to the GND level.
[0026]
Then, the data stored in the memory cell mat of the memory cell group 51 corresponding to the signal line selected by the column decoder 33 and the row decoder 34 is output to the bit line. For example, when the stored data is zero, When the pre-sense signal becomes “H” level, the bit line potential that has been precharged when the chip is enabled is lowered and discharged.
[0027]
On the other hand, when the LSB address A ₀ is supplied to the address buffer 21 following the address signal A ₁ at time t ₂ , the sense amplifier signal is output as the “H” level using this as a trigger.
In addition, when the LSB address A ₀ is input from the shift register 11 following the address signal A ₁ , the address buffer 21 outputs this to the AND circuit 35a of the LSB decoder 35, and also outputs the inverted signal thereof to the AND circuit 35b. Output to.
[0028]
Therefore, in the LSB decoder 35, while the sense amplifier signal is at the “H” level, either the signal LS0 or LS1 that is the output of the AND circuit 35a or 35b is at the “H” level, and the signal LS0 is at the “H” level. the output bit lines BL 8 to BL 15 in the selection unit 85 is selected is output to the sense amplifier and latch circuit 65 when the, from the sense amplifier signal at this time is at "H" level, where the data of the deterministic operation And the result is output via the output buffer 71.
[0029]
On the other hand, when the signal LS1 is at “H” level, the selection unit 85 selects the bit lines BL 0 to BL 7 and outputs the output to the sense amplifier / latch circuit 65, and the sense amplifier signal is at “H” level. A definite operation is performed in the sense amplifier / latch circuit 65 and the result is output via the output buffer 71. Here, as shown in the schematic diagram of FIG. 3, parasitic capacitances CB1 and CB2 are generated in the bit line, but before the sense amplifier 65 is activated by the sense amplifier signal becoming “H” level, the selection unit 85 The bit line on the memory cell group 51 side is already discharged. Therefore, when the sense amplifier 65 operates, it is not necessary to discharge the parasitic capacitances CB1 and CB2 of the bit line.
[0030]
Therefore, even when data “0” is read from the memory cell group 51, since the discharge has already been performed when the sense amplifier operates, the change of the node immediately before the sense amplifier is fast, and the read is quickly performed. It can be carried out. Therefore, the reading time can be shortened accordingly.
Further, the selector 8 5, LSB address _{A 0} is "1" bit lines BL 0 to BL 7 corresponding to the time is, and LSB address _{A 0} is "0" the bit line BL 8 corresponding to the time is ~ Since any one of BL 15 is selected and processed by the sense amplifier / latch circuit 65, it is not necessary to provide two sets of sense amplifier / latch circuits 65 as in the prior art.
[0031]
Further, since the read time of the sense amplifier can be shortened by the output timing of the pre-sense signal in this way, a semiconductor memory device that does not become sense amplifier discipline can be realized.
In the above-described embodiment, the case where 8-bit data is read from an 8-bit address signal has been described. However, the present invention is not limited to this, and the present invention can be applied to an address signal having an arbitrary number of bits. Can do.
[0032]
In the above embodiment, the data when the LSB address A ₀ is “0” and the data when the LSB address A ₀ is “1” are read, and whether the LSB address A ₀ is “1” or “0”. In the above description, the selection unit 85 selects one of them based on whether or not, but the present invention is not limited to this. That is, based on the remaining number of bits obtained by removing an arbitrary number of bits from the first serially input address signal, assuming that the remaining number of bits is Y, 2 ^Y-1 selection units 85 are provided, When an address signal having an arbitrary number of bits is supplied to the address buffer 21, the pre-sense signal is set to "H" level to select all the memory cells specified by the address signal, and the bit values of the remaining bits of the address signal For each combination, the memory data is output to the selection unit 85, and when all the remaining bits of the address signal are supplied to the address buffer 21, the sense amplifier signal is set to "H" level and the remaining bits Data from the selection unit 85 specified by the bit value may be supplied to the sense amplifier / latch circuit 65.
[0033]
By doing so, the time from the start of the bit line discharge to the start of the processing in the sense amplifier can be extended. Therefore, it is effective to adjust according to the parasitic capacitance of the bit line.
[0034]
【The invention's effect】
As described above, according to the semiconductor memory device of the first or second aspect of the present invention, the N-bit address signals (A _{N-1 to} A ₀ ) are first serially input. The M-bit address signal (A _{N-1 to} A _N-M ) is decoded, and all the memory cells indicated by the address signal (A _{N-1 to} A _N-M ) are selected and activated. Of these, the bit line of the address specified by the remaining address signal is selected, and the data determination operation is performed in the sense amplifier unit, so that a semiconductor memory device that does not become sense amplifier discipline can be realized.
[0035]
In particular, if the bit line is activated for a predetermined time prior to the bit line selection operation by the bit line selection means, the discharge is already performed at least when the bit line selection operation is performed by the bit line selection means. As a result, the processing time required for the discharge during the definite operation in the sense amplifier unit can be shortened.
[0036]
In addition, after the input of the M-bit address signal in the decoding unit, and before the processing time required for the discharge accompanying the operation of the sense amplifier, at least before the start time of the selection operation in the bit line selection means, the bit line It is possible to promptly shift to a deterministic operation by performing the activation of.
[Brief description of the drawings]
FIG. 1 is a block configuration diagram of a semiconductor memory device according to an embodiment of the present invention.
2 is a circuit diagram showing an example of the circuit configuration of FIG. 1. FIG.
3 is a schematic diagram for explaining a connection portion between a selection unit 85 and a bit line transfer gate 41 in FIG. 1;
FIG. 4 is a timing chart for explaining the operation of the present invention.
FIG. 5 is a block diagram of a conventional semiconductor memory device.
[Explanation of symbols]
11 shift register 21 address buffer 33 column decoder 34 row decoder 35 LSB decoder 41 bit line transfer gate 51 memory cell group 65 sense amplifier / latch circuit 71 output buffer 85 selector

Claims (2)

A semiconductor memory device for outputting data stored in a memory cell corresponding to an N-bit (N is a natural number) address signal input serially,
The N-bit address signal is serially input, and an M-bit address signal (M is a natural number 1 ≦ M ≦ N−1) is decoded from the first serially input address signal. A decoding unit for selecting all the designated memory cells;
Activating means for activating a bit line connected to a memory cell indicated by an M-bit address signal selected by the decoding unit;
Based on the address signal and the sense amplifier signals except for M bits obtained by decoding of the address signal of the N bit, the bit line selection means for selecting a bit line to be connected to the sense amplifier of the active bit line at said active means When,
A sense amplifier section that is activated by the sense amplifier signal and performs a data confirmation operation on the bit line selected by the bit line selection means and outputs a confirmation result;
The sense amplifier signal is output as a trigger when all the N-bit address signals are input to the decoding unit,
The activation means activates the bit line prior to the timing at which the selection operation is performed for a predetermined time set based on the timing at which the bit line selection operation is performed by the bit line selection means. Semiconductor memory device. A semiconductor memory device for outputting data stored in a memory cell corresponding to an N-bit (N is a natural number) address signal input serially,
The N-bit address signal is serially input, and an M-bit address signal (M is a natural number 1 ≦ M ≦ N−1) is decoded from the first serially input address signal. A decoding unit for selecting all the designated memory cells;
Activating means for activating a bit line connected to a memory cell indicated by an M-bit address signal selected by the decoding unit;
Based on the address signal and the sense amplifier signals except for M bits obtained by decoding of the address signal of the N bit, the bit line selection means for selecting a bit line to be connected to the sense amplifier of the active bit line at said active means When,
A sense amplifier section that is activated by the sense amplifier signal and performs a data confirmation operation on the bit line selected by the bit line selection means and outputs a confirmation result;
The sense amplifier signal is output as a trigger when all the N-bit address signals are input to the decoding unit,
The activating means is required for discharging the bit line after the input operation of the M-bit address signal in the decoding unit and at least accompanying the data determining operation of the sense amplifier unit rather than the selecting operation in the bit line selecting unit. A semiconductor memory device, wherein the bit line is activated before a processing time.

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