JP3580266B2 - Semiconductor storage device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a semiconductor memory device such as a mask ROM (Mask Read Only Memory: MROM) in which data recording is programmed by a mask used in a chip manufacturing process.
[0002]
[Prior art]
Conventionally, a mask ROM whose main part is shown in FIG. 8 is known. In the figure, 58 is a chip body, 59 to 62 are 1024 × 1024 × 2 bit memory cell arrays, and 63 is an address buffer to which row address signals A0 to A9 and column address signals A10 to A19 are input.
[0003]
A row decoder 64 decodes the row address signals A0 to A9 output from the address buffer 63 and selects a word line of the memory cell arrays 59 and 60.
[0004]
A row decoder 65 decodes the row address signals A0 to A9 output from the address buffer 63 and selects a word line of the memory cell arrays 61 and 62.
[0005]
Reference numerals 66 to 69 denote column decoders for decoding column address signals A10 to A19 output from the address buffer 63 and outputting column selection signals for selecting columns of the memory cell arrays 59 to 62, respectively.
[0006]
Reference numerals 70 to 73 denote sense amplifiers for detecting data read from the memory cell arrays 59 to 62, respectively, and reference numeral 74 denotes an output buffer for outputting the data detected by the sense amplifiers 70 to 73 to the outside.
[0007]
The column gates for selecting the columns of the memory cell arrays 59 to 62 based on the column selection signals output from the column decoders 66 to 69 are not shown.
[0008]
Reference numeral 75 also receives a chip enable signal / CE and an output enable signal / OE from outside, and outputs a control signal for controlling the operation of the address buffer 63, the sense amplifiers 70 to 73, the output buffer 74, etc. / OE logic circuit.
[0009]
Each of the sense amplifiers 70 to 73 is configured as shown in FIG. In the figure, 75 is a VCC power supply line for supplying a power supply voltage VCC, 76 is a resistor forming a load, 77 is an nMOS transistor, 78 is an inverter, and 79 is a bit line selected by a column gate.
[0010]
The output buffer 74 is configured so that its 1-bit portion is shown in FIG. In the figure, reference numeral 80 denotes a VCC power supply line, and reference numeral 81 denotes an internal output enable signal input terminal to which an internal output enable signal OE having an inversion relationship with the output enable signal / OE is input.
[0011]
Reference numeral 82 denotes an internal output enable signal input terminal to which an internal output enable signal OEB having the same phase as the output enable signal / OE is input.
[0012]
83 is a sense amplifier output / input terminal to which the sense amplifier output SOUT is input, 84 is a NAND circuit, 85 is a NOR circuit, 86 is a pMOS transistor, 87 is an nMOS transistor, and 88 is a data output terminal.
[0013]
In the output buffer 74, at the time of reading, the internal output enable signal OE is set to "H" and the internal output enable signal OEB is set to "L".
[0014]
As a result, when the sense amplifier output SOUT = “H”, the output of the NAND circuit 84 = “L”, the pMOS transistor 86 = ON, the output of the NOR circuit 85 = “L”, and the nMOS transistor 87 = It is turned OFF, and "H" is output as the output data DOUT.
[0015]
On the other hand, when the sense amplifier output SOUT = “L”, the output of the NAND circuit 84 = “H”, the pMOS transistor 86 = OFF, the output of the NOR circuit 85 = “H”, and the nMOS transistor 87 = ON, and “L” is output as the output data DOUT.
[0016]
FIG. 11 is a waveform diagram showing a read operation of the conventional mask ROM shown in FIG. 8, FIG. 11 (A) shows address signals A0 to A19, FIG. 11 (B) shows output SOUT of sense amplifiers 70 to 73, FIG. (C) shows a change in data D0 to D7 output from the output buffer 74. Note that TCY is a cycle time, and TAC is an address access time.
[0017]
[Problems to be solved by the invention]
In the conventional mask ROM shown in FIG. 8, the cycle time TCY is longer than the address access time TAC (see FIG. 11), and a time longer than the address access time TAC elapses from the determination of the address. Until then, no change in address was recognized, which hindered the speeding up of the read operation.
[0018]
In view of the above, an object of the present invention is to provide a semiconductor memory device in which the cycle time TCY is shorter than the address access time TAC so that the speed can be increased.
[0019]
[Means for Solving the Problems]
A semiconductor memory device according to the present invention includes: an address buffer for inputting at least a part of an address signal composed of a plurality of bits; and a timing according to a predetermined bit and an inverted bit of the address signal composed of the plurality of bits. First and second address storage circuits for alternately storing the output address signals; and first and second address storage circuits provided corresponding to the first and second address storage circuits, respectively. The first and second memory areas from which data is read by decoding the output address signal are read from the first and second memory areas in accordance with the timing according to the predetermined bit and its inverted bit. And an output switching circuit for alternately switching the output data and outputting the data .
[0020]
[Action]
According to the present invention, the storage timing of the address signal in the first and second address storage circuits and the output data switching timing in the output switching circuit are generated from a predetermined bit of the address signal and its inverted bit. Therefore, even if the address access time TAC is the same as the conventional case , the cycle time TCY can be reduced to １ ／ by a simple circuit configuration .
[0021]
【Example】
Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 7 by taking a case where the present invention is applied to a mask ROM as an example.
[0022]
FIG. 1 is a block diagram showing a main part of an embodiment of the present invention. In the drawing, 234 is a chip body, and 237 to 240 are 1024 × 512 × 4 bit memory cell arrays.
[0023]
A0 to A19 are address signals, A0 is an address signal used as a control signal for selecting a memory cell array and the like, A1 to A10 are row address signals for selecting a word line of the memory cell array, and A11 to A19 are columns. This is a column address signal for selection.
[0024]
Reference numeral 241 denotes an address buffer for fetching externally supplied address signals A1 to A19, and reference numerals 242 and 243 denote address storage circuits for alternately storing address signals A1 to A19 sequentially output from the address buffer 241.
[0025]
Reference numeral 244 denotes a row decoder that decodes the row address signals A1 to A10 among the address signals A1 to A19 stored in the address storage circuit 242 and selects a word line of the memory cell arrays 237 and 238.
[0026]
A row decoder 245 decodes the row address signals A1 to A10 among the address signals A1 to A19 stored in the address storage circuit 242 and selects a word line of the memory cell arrays 239 and 240.
[0027]
Further, reference numerals 246 to 249 denote column selections necessary for decoding the column address signals A11 to A19 of the address signals A1 to A19 stored in the address storage circuits 242 and 243 and selecting columns of the memory cell arrays 237 to 240, respectively. This is a column decoder that outputs a signal.
[0028]
Note that a column gate circuit for selecting a column of the memory cell arrays 237 to 240 based on column selection signals output from the column decoders 246 to 249 is not shown.
[0029]
Reference numerals 250 to 253 denote sense amplifiers for amplifying and detecting data read from the memory cell arrays 237 to 240, respectively.
[0030]
An output switching circuit 254 selects and outputs a sense amplifier output SOUT1 output from the sense amplifiers 250 and 251 and a sense amplifier output SOUT2 output from the sense amplifiers 252 and 253.
[0031]
An output buffer 255 outputs the sense amplifier output SOUT (SOUT1 or SOUT2) output from the output switching circuit 254 to the outside.
[0032]
Reference numeral 256 denotes a chip enable signal / CE, an output enable signal / OE, and an address signal A0 supplied from outside, and an address buffer 241, address storage circuits 242 and 243, sense amplifiers 250 to 253, and an output buffer. /CE./OE.A0 logic circuit that outputs a control signal for controlling the operation of H.255 or the like.
[0033]
The address storage circuits 242 and 243 are configured, for example, as shown in FIG. In the drawing, 257 ₁ , 257 ₁₀ , 257 ₁₁ , 257 ₁₉ , 258 ₁ , 258 ₁₀ , 258 ₁₁ , and 258 ₁₉ are negative edge type D flip-flops.
[0034]
Here, the D flip-flops 257 _{1 to} 257 ₁₉ are configured to latch the address signals A0 to A19 in synchronization with the falling edge of the address signal A0.
[0035]
Further, the D flip-flops 258 _{1 to} 258 ₁₉ are configured to latch the address signals A1 to A19 in synchronization with the falling edge of the address signal / A0 having an inversion relationship with the address signal A0.
[0036]
The address signals A0 and / A0 are generated in a circuit provided in the /CE./OE.A0 logic circuit 256, for example, as shown in FIG.
[0037]
In the figure, reference numeral 259 denotes an address signal input terminal to which an externally supplied address signal A0 is input, and 260 denotes an internal chip enable signal input terminal to which an internal chip enable signal CEB is input.
[0038]
Reference numeral 261 denotes an OR circuit; 262, an inverter; 263, an address signal output terminal from which the address signal A0 is output; and 264, an address signal output terminal from which the address signal / A0 is output.
[0039]
Further, the sense amplifiers 250 to 253 are configured, for example, as shown in FIG. 9 showing a 1-bit portion thereof, similarly to the sense amplifiers 70 to 73 provided in the conventional mask ROM shown in FIG.
[0040]
The output switching circuit 254 is configured, for example, as shown in FIG. In the drawing, reference numeral 265 denotes a sense amplifier output / input terminal to which a 1-bit portion of the sense amplifier output SOUT1 of the sense amplifiers 250 and 251 is input, and 266 denotes a 1-bit portion of the sense amplifier output SOUT2 of the sense amplifiers 252 and 253. Sense amplifier output / input terminal.
[0041]
267 is an address signal input terminal to which the address signal A0 is input, 268 is an address signal input terminal to which the address signal / A0 is input, 269 and 270 are nMOS transistors, 271 is a 1-bit portion or sense of the sense amplifier output SOUT1. One bit portion of the amplifier output SOUT2 is an output terminal that is output as the sense amplifier output SOUT.
[0042]
In the output switching circuit 254, when the address signal A0 = “H” and the address signal / A0 = “L”, the nMOS transistor 269 = ON and the nMOS transistor 270 = OFF, and the sense amplifier output SOUT1 is used as the sense amplifier output SOUT. Is output.
[0043]
On the other hand, when the address signal A0 = “L” and the address signal / A0 = “H”, the nMOS transistor 269 = OFF and the nMOS transistor 270 = ON, and the sense amplifier output SOUT2 is set as the sense amplifier output SOUT. Output.
[0044]
Further, the output buffer 255 is configured, for example, as shown in FIG. 10 showing a 1-bit portion thereof, similarly to the output buffer 74 provided in the conventional mask ROM shown in FIG.
[0045]
The embodiment of the present invention thus configured can be operated as shown in an operation waveform in FIG. 5A shows a voltage waveform of the address signal A0, FIG. 5B shows a voltage waveform of the address signal / A0, and FIG. 5C shows a voltage waveform of the input address signals A1 to A19.
[0046]
FIG. 5D shows the voltage waveforms of the address signals A1 to A19 output from the address storage circuit 242, and FIG. 5E shows the voltage waveforms of the address signals A1 to A19 output from the address storage circuit 243. I have.
[0047]
5F is a voltage waveform of the sense amplifier output SOUT1 output from the sense amplifiers 250 and 251, FIG. 5G is a voltage waveform of the sense amplifier output SOUT2 output from the sense amplifiers 252 and 253, and FIG. (H) shows the voltage waveform of the output data D0 to D7.
[0048]
As described above, according to one embodiment of the present invention, the address signals A1 to A19 sequentially output from the address buffer 241 are stored in the two address storage circuits 242 and 243 in order, and these two address storage circuits 242 are stored. 243, and decodes address signals A1 to A19 from two memory areas (one memory area for the memory cell arrays 246 and 247, and another memory area for the memory cell arrays 248 and 249). The data read from these two memory areas is sequentially switched by the output switching circuit 254 and output.
[0049]
Therefore, even if the address access time TAC is the same as that of the conventional mask ROM shown in FIG. 8, the cycle time TCY can be halved, and the amount of data read per unit time can be increased. Thus, the speed of the read operation can be increased.
[0050]
In the embodiment of the present invention, the case has been described in which the address signal A0 is used as a control signal for regulating the address access time TAC. However, instead of this, a clock signal or the like supplied from outside is used. Can also be configured to be used.
[0051]
In the case where the address counter circuit shown in FIG. 6 is provided and serial reading is performed, an output of the address counter circuit may be supplied to the row decoders 244 and 245.
[0052]
6, reference numeral 272 denotes an address storage circuit for storing address signals A1 to A19 output from the address buffer 241. Reference numeral 273 denotes address signals A1 to A1 sequentially incremented by using the addresses stored in the address storage circuit 272 as initial values. A counter that outputs A19.
[0053]
An address storage circuit 274 stores and outputs the address signals A1 to A19 output from the counter 273 in synchronization with the falling edge of the address signal A0, and 275 stores the address signals A1 to A19 output from the counter 273. An address storage circuit that stores and outputs the data in synchronization with the falling edge of the address signal A0.
[0054]
These address storage circuits 274 and 275 may be provided separately and independently from the address storage circuits 242 and 243 shown in FIG. 1, or these address storage circuits 242 and 243 may be used.
[0055]
When reading is performed using the address counter circuit shown in FIG. 6, the operation can be performed as shown in the operation waveforms of FIG. 7A shows a voltage waveform of the address signal A0, FIG. 7B shows a voltage waveform of the address signal / A0, and FIG. 7C shows a voltage waveform of the address signals A1 to A19 output from the counter 273. I have.
[0056]
FIG. 7D shows the voltage waveforms of the address signals A1 to A19 output from the address storage circuit 274, and FIG. 7E shows the voltage waveforms of the address signals A1 to A19 output from the address storage circuit 275. I have.
[0057]
7F is a voltage waveform of the sense amplifier output SOUT1 output from the sense amplifiers 250 and 251, FIG. 7G is a voltage waveform of the sense amplifier output SOUT2 output from the sense amplifiers 252 and 253, and FIG. (H) shows the voltage waveform of the output data D0 to D7.
[0058]
As described above, when the address counter circuit shown in FIG. 6 is provided, even if the address access time TAC is the same as that of the conventional mask ROM shown in FIG. Since TCY can be halved, the amount of data read per unit time in serial read can be increased, and the read operation can be speeded up.
[0059]
【The invention's effect】
As described above, according to the present invention, it is the same as in the conventional address access time TAC, a simple circuit structure, since the cycle time TCY can be 1/2, the circuit scale The increase can be minimized, and the speed of data reading can be increased.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a main part of an embodiment of the present invention.
FIG. 2 is a circuit diagram of an address storage circuit provided in an embodiment of the present invention.
FIG. 3 is a circuit diagram showing a part of a /CE./OE.A0 logic circuit provided in an embodiment of the present invention.
FIG. 4 is a circuit diagram of a 1-bit portion of an output switching circuit provided in an embodiment of the present invention.
FIG. 5 is a waveform chart showing the operation of one embodiment of the present invention.
FIG. 6 is a circuit diagram showing a main part of an address counter circuit.
FIG. 7 is a waveform chart showing an operation of the embodiment of the present invention when the address counter circuit shown in FIG. 6 is used.
FIG. 8 is a block diagram showing a main part of an example of a conventional mask ROM.
FIG. 9 is a circuit diagram showing a 1-bit portion of a sense amplifier included in the conventional mask ROM shown in FIG.
FIG. 10 is a circuit diagram showing a 1-bit portion of an output buffer constituting the conventional mask ROM shown in FIG.
FIG. 11 is a waveform chart showing an operation of the conventional mask ROM shown in FIG.
[Explanation of symbols]
A0 to A19 Address signals SOUT1, SOUT2 Sense amplifier outputs D0 to D7 Output data

Claims (3)

An address buffer for inputting at least a part of an address signal composed of a plurality of bits;
A first and second address storage circuit for alternately storing the address signals sequentially output from the address buffer according to a timing corresponding to a predetermined bit and an inverted bit of the plurality of bits of the address signal;
The first and second address storage circuits are provided corresponding to the first and second address storage circuits, respectively. The first and second address storage circuits read data by decoding the address signals output from the first and second address storage circuits. A second memory area;
An output switching circuit for alternately switching and outputting data read from the first and second memory areas in accordance with timing according to the predetermined bit and its inverted bit;
The semiconductor memory device characterized by comprising a. 2. The semiconductor memory device according to claim 1, wherein said address signal comprising a plurality of bits is supplied from outside . A third address storage circuit for storing an address signal supplied from the address buffer;
An address signal indicating an address value generated by sequentially incrementing or decrementing the address value indicated by the address signal stored in the third address storage circuit as an initial value is output to the first and second address storage circuits. Address counter and
2. The semiconductor memory device according to claim 1, further comprising:

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