JPH09190689A - Dynamic random access memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To arbitrarily perform an external access by monitoring a low address for a refreshing operation and a low address for either of a read operation and a write operation. SOLUTION: A control circuit 12 and a refresh control circuit 1 always monitor the demands of both circuits. and when a time difference between both demands is very small or the demands are generated simultaneously, an operation of a reading line selector 4 is protected by delaying the demand for the refresh operation. In this case, since a time level of several nanoseconds to secure a set-up time and a holding time in inputting data to a latch circuit 31 is enough for the delaying time of the refresh operation, this is a very short time compared with several tens to several hundreds milliseconds of a refreshing cycle and the delaying time does not give any influence on the refresh operation at all.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory, and more particularly to a dynamic random access memory that does not require external interrupt refresh control.

[0001]

2. Description of the Related Art Conventionally, this kind of dynamic random access memory has a property that data stored in a memory cell is discarded after several seconds from several tens of msec, and in order to prevent this, a memory called a refresh operation is stored. The data reproducing operation is periodically performed. The dynamic random access memory has a problem that neither the read operation nor the write operation can be performed while the refresh operation is being performed. Even when the dynamic random access memory is in the read operation or the write operation, when the time when the refresh operation needs to be executed, either the read operation or the write operation is interrupted and the refresh operation is performed. There was a problem that the operation had to be interrupted.

As a method for solving this problem, for example, in Japanese Patent Laid-Open No. 3-263685, the access on the refresh side is prohibited when the address of the access to the memory from the outside and the address of the access by the refresh conflict. It describes the technology that enables external access.

[0003]

In the above-mentioned prior art,
If an external access occurs at the same row address during the refresh operation, the refresh operation is stopped and the external access is prioritized. Therefore, the stored data is read to the refresh bit line and the refresh can be stopped before being sufficiently amplified, so that the next time the data is read out, the normal data cannot be read.

It is an object of the present invention to allow arbitrary external access while periodically performing a refresh operation.

[0005]

In order to solve the above-mentioned problems, a dynamic random access memory of the present invention is a dynamic random access memory including a means for performing a refresh operation, and an external device using the means for performing the refresh operation. At least one of a write operation from the memory and a read operation to the outside is performed.

Another dynamic random access memory of the present invention is a word line selection signal corresponding to a first request for either an external write operation or an external read operation, and a refresh operation. For monitoring the refresh bit line selection signal corresponding to the second request for refreshing, a refresh sense amplifier for amplifying the stored data during the refresh operation, and the monitoring means for performing the refresh operation during the refresh operation. When there is a first request, the stored data amplified by the refresh sense amplifier is output to the outside.

In another dynamic random access memory of the present invention, a word line activated when operating in response to the first request, a sense amplifier amplifying stored data when operating in response to the first request, If the value of the word line selection signal and the value of the refresh word line selection signal match from the result of the monitoring means and the refresh word line activated during the operation for the second request, the first word Either the word line or the refresh word line is activated according to the time sequence of one request and the second request, and if they do not match, the word line is activated for the first request. , A control means for activating the refresh word line in response to the second request, a value of the word line selection signal and the refresh Further comprising the value of lead wires and a means for switching said sense amplifier and said sense amplifier refreshing.

Another dynamic random access memory of the present invention monitors the first request and the second request, and the time difference between the first request and the second request is smaller than a specified value. It further comprises a delay means for delaying the second request in some cases.

In another dynamic random access memory of the present invention, the delay means determines a first period determining means for determining a period for generating an instruction to delay the refresh operation, and a period for delaying the refresh operation. And a second period determining means for performing.

Further, in another dynamic random access memory according to the present invention, the delay means generates a pulse signal which becomes active only during the period determined by the first period determination means, and the pulse generation means. A clock generating circuit for generating a first clock signal for determining an instruction to delay the refresh operation from a pulse signal generated by the means, and a second clock signal for determining the timing of the refresh operation; and the first clock. And a means for generating a signal instructing execution of a refresh operation from the signal and the second clock signal.

Further, another dynamic random access memory of the present invention is a word line activated at the time of either an external read operation or a write operation, and a first memory cell connected to this word line. A bit line connected to the first memory cell, a refresh word line activated during a refresh operation, a second memory cell connected to the refresh word line, and a second memory A refresh bit line connected to a cell, a sense amplifier connected to the bit line, a refresh sense amplifier connected to the refresh bit line, and either an external read operation or write operation Monitoring a first request for performing a refresh operation and a second request for performing a refresh operation. A first row address of interest in a unit the time difference of the second request delaying the second request if less than the predetermined value, the first request,
The target second row address is monitored in the second request, and when the first row address and the second row address match, the first request and the second request Either the word line or the refresh word line is activated according to the time order of the requests, and if they do not match, the word line is activated for the first request and for the second request. Includes a control means for activating the refresh word line and a means for switching between the sense amplifier and the refresh sense amplifier.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of a dynamic random access memory of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a dynamic random access memory (hereinafter referred to as DRAM) which is an embodiment of the present invention.
The memory cell of (1) is configured such that the source terminals of the n-channel MOS transistor 100 and the n-channel MOS transistor 200 are commonly connected to one electrode of the capacitor 300. The other electrode of the capacitor 300 is grounded. n-channel MOS transistor 100
The gate terminal and drain terminal of each are word lines 1
01 and the bit line 102. The gate terminal and the drain terminal of the n-channel MOS transistor 200 are connected to the refresh word line 201 and the refresh bit line 202, respectively.

When either the word line 101 or the refresh word line 201 is activated and a high potential is applied, n
Channel MOS transistor 100 or n channel M
One of the OS transistors 200 is turned on, and data can be exchanged between the capacitor 300 and either the bit line 102 or the refresh bit line 202. When both the word line 101 and the refresh word line 201 are inactive and remain at a low potential, the n-channel MOS transistor 100 and the n-channel MOS transistor 200 are turned off and the memory cell holds the stored data.

Referring to FIG. 2, the DRAM of the present embodiment.
Is configured by arranging memory cells in 4 rows × 4 columns.
, 101-3 and refresh word lines 201-0, ..., 201-3 are connected to a word line selector 4 that exclusively selects one of these lines. There is. Bit line 102-0, ..., 102-
3 is connected to a sense amplifier circuit 9 that amplifies the data of each memory cell. Refresh bit line 202
-0, ..., 202-3 are connected to the refresh sense amplifier circuit 3 for amplifying the data of each memory cell.

The DRAM also includes a row address buffer 6 for latching a row address, a row decoder 8 for decoding the row address latched by the row address buffer 6, and a column address buffer 7 for latching a column address. , This column address buffer 7
It has a column decoder 10 which decodes the column address latched in.

Further, the DRAM of this embodiment has a control circuit 12, a refresh control circuit 1, a refresh row decoder 2 and a refresh sense amplifier circuit 3.

The control circuit 12 and the refresh control circuit 1 constantly monitor a request for a read operation or a write operation from the outside and a request for a refresh operation, and the time difference between the two is very small or the requests are generated at the same time. If so, the request for the refresh operation is delayed.

Referring to FIG. 3, the control circuit 12 receives the RAS signal from the outside and outputs the signal RASP.
The refresh control circuit 1 receives the signal RASP and outputs the control signal REF.

In the control circuit 12, the exclusive OR (E
The OR) circuit 52 receives the RAS signal from the outside and its RA
A signal obtained by delaying the S signal by the delay circuit 51 by the time td1 is used as an input, and the logical product (AND) circuit 53 outputs an exclusive logical sum (EO) with a signal obtained by inverting the external RAS signal.
R) The output signal of the circuit 52 is input. This logical product (A
The output signal of the ND) circuit 53 is the signal RASP. still,
The RAS signal from the outside is also used for other conventional operations.

The refresh control circuit 1 has a built-in timer and sends a control signal REF to the refresh row decoder 2 and the refresh sense amplifier circuit 3 in accordance with a prescribed refresh timing. The refresh control circuit 1 also includes a latch circuit 54, a REF clock generation circuit 55, a logical product (AND) circuit 56, and a logical product (AN).
D) circuit 57, delay circuit 58, and logical sum (OR) circuit 59
And

The REF clock generation circuit 55 generates two types of REF clock signals having a cycle of a prescribed refresh cycle time (refresh cycle divided by the number of row addresses). The two types of REF clock signals have the same period, but the ratios of the time of the "1" state (high level) and the time of the "0" state (low level) are different, and the REF clock signal 1 is "1". After the state, the REF clock signal 2 goes into the "1" state, and after the REF clock signal 2 goes into the "0" state, the REF clock signal 1 goes into the "0" state. The latch circuit 54 receives the REF clock signal 1 (signal H) as a clock input signal, and uses the signal RASP as a data signal.
The (signal G) is latched and the signal J is output. A logical product (AND) circuit 56 inputs the inverted signal of the signal J and the REF clock signal 2 (signal K) and outputs a signal L, and a logical product (AND) circuit 57 outputs the signal J and the REF clock signal 2 ( The signal K) is input and the signal M is output. Logical sum (O
The (R) circuit 59 inputs the signal L and the signal M delayed by the delay circuit 58 by the time td2, and outputs the signal P. This signal P is the control signal REF, and becomes the signal transmitted to the refresh row decoder 2 and the refresh sense amplifier circuit 3 as described above.

Referring to FIG. 2, the refresh row decoder 2 has a refresh counter, and when receiving the control signal REF from the refresh control circuit 1, the refresh word line selection signal RS is sequentially output according to the refresh counter. Activate exclusively.

When the word line selector 4 receives the refresh word line selection signals 2-0, ..., 2-3,
Refresh word line 201-corresponding to this signal
0, ..., 201-3 are activated.

The word line selector 4 constantly monitors the target row address in the refresh operation and the target row address in either the external read operation or the write operation. If the two addresses match, the word lines 101-0, ..., 10 corresponding to the row address are arranged according to the temporal order.
1-3 or refresh word line 201-0, ...
-Activate one of 201-3.

The word line selector 4 includes a word line 101-
0, ..., 101-3 and refresh word line 20
The word line selector circuit 41 for selecting 1-0, ..., 201-3 and the refresh word lines 201-0 ,.
.., 201-3 are used to perform a read operation or a write operation, and a sense amplifier switching circuit 42 that outputs a sense amplifier circuit switching signal SAR.

The bit line selector 5 receives the sense amplifier circuit switching signal output from the word line selector 4, and receives the bit lines 102-0, ..., 102-3 or the refresh bit lines 202-0 ,. , 202-3
Either of them is connected to the input / output data buffer 11.
The input / output data buffer 11 performs input / output with the outside.

Referring to FIG. 4, the word line selector circuit 41 of the present embodiment represents a request state of either a read operation or a write operation from the outside with respect to an arbitrary row address, and a word output from the row decoder 8. The line selection signal 8-N (N = 0, ... 3) and the refresh word line selection signal 2-N (N = N = N = N)
0, ..., 3) as input, and the refresh word lines 201-N (N = 0, ..., 3) and the word line 101.
The output is −N (N = 0, ..., 3). The word line selector circuit 41 includes a latch circuit 31, a logical product (AND) circuit 32, a logical sum (OR) circuit 33, a latch circuit 34, and a logical product (AND) circuit 35. The latch circuit 31 receives the refresh word line selection signal 2-N (N = 0, ..., 3) (signal A) as a clock input, and uses the refresh word line selection signal 8-N as a data signal.
N (N = 0, ..., 3) (signal B) is latched and the signal C is output as an inverted output. The logical product (AND) circuit 32 inputs the signal C and the signal A and outputs the signal D. The logical sum (OR) circuit 33 inputs the signal D and the signal B and outputs the signal E. The latch circuit 34 receives the signal E
Is used as a clock input signal to latch a signal D which is a data signal, and outputs an output data signal X and an inverted output data signal F. A logical product (AND) circuit 35 inputs the signal F and the signal B and outputs the signal Y. This signal X and signal Y
And the refresh word lines 201-N (N
= 0, ..., 3) and word lines 101-N (N =
0, ..., 3).

Referring to FIG. 5, the sense amplifier switching circuit 42 of this embodiment is a logical product (AND) circuit 36-N.
(N = 0, ..., 3) and a logical sum (OR) circuit 37. AND (AND) circuit 36-N (N = 0, ...
.. 3) are provided by the number of rows of memory cells, and the word line selection signals 8-N (N = 0, ..., 3) and the refresh word lines 201-N (N = 0 ,. 3) is input and the signal SAR-N (N = 0, ..., 3) is output. The logical sum (OR) circuit 37 takes the logical sum of all the row addresses of the signal SAR-N (N = 0, ..., 3) corresponding to each row address and outputs the sense amplifier circuit switching signal SAR. .

Next, the operation of one embodiment of the dynamic random access memory of the present invention will be described in detail with reference to the drawings.

Referring to FIGS. 2 and 4, the word line selector 4 always sets a target row address in the refresh operation and a target row address in either the external read operation or the write operation. Monitor. If the two match, the word line 101-corresponding to the row address depending on the temporal order.
Either N (N = 0, ..., 3) or refresh word line 201-N (N = 0, ..., 3) is activated. If they do not match, for the refresh operation, the refresh word line 201-N (N = 0, ..., 3) corresponding to the row address is activated, and either the external read operation or the write operation is performed. For that operation, the word line 101-N (N = 0, ..., 3) corresponding to the row address is activated. However, in actuality, read / write access from the outside is completely arbitrary, so it is conceivable that the time difference between the two is very small, and sometimes requests are issued at exactly the same time. In such a case, the word line selector 4 described above
The latch circuit 31 inside the word line select signal 8-N (N = 0, ..., 3) and the refresh word line select signal 2-N (N = 0, ...
If 3) is accepted, the desired operation may not be guaranteed and the operation may be undefined. Therefore, in one embodiment of the dynamic random access memory of the present invention, the control circuit 12
Also, the refresh control circuit 1 constantly monitors both requests, and when the time difference between the two is very small or requests are generated at the same time, the request for the refresh operation is delayed so that the word line selector 4 Guarantee operation. At that time, the time for delaying the refresh operation may be several ns as long as the setup time and the hold time are assured in the data input of the latch circuit 31.
It can be said that the delay time is extremely small as compared with the refresh cycle of several tens ms to several hundred ms, and the delay time does not affect the refresh operation at all. Further, since a request for a read operation or a write operation from the outside is accepted as it is, it does not affect the read / write access from the outside at all.

Referring to FIG. 6, a request for a read operation or a write operation from the outside in the DRAM can be recognized earliest when the RAS signal input from the outside falls, so that the control circuit 12 outputs the RAS signal. A signal RASP having a constant pulse width is generated on the "1" state (high level) side based on the fall. The width of the "1" state of the signal RASP corresponds to the delay time td1 of the delay circuit 51, and is set to be equal to or more than the sum of the setup time and the hold time in the data input of the latch circuit 31 in the word line selector 4. The refresh control circuit 1 uses the signal RASP input from the control circuit 12 as a timing for requesting a read operation or a write operation from the outside,
RE generated by the internal REF clock generator 55
The F clock signal is used as the timing of the refresh operation request, and the temporal relationship between the two is monitored.

The latch circuit 54 uses the REF clock signal 1
The signal RASP (signal G), which becomes a data signal, is latched by using (signal H) as a clock input signal. If REF
Signal RAS at the rising edge of clock signal 1 (signal H)
If the P (signal G) is in the "0" state, the latch circuit 54 is in operation while the REF clock signal 1 (signal H) is in the "1" state.
The "0" state is determined for the output signal J of. Conversely, when the REF clock signal 1 (signal H) rises, the signal RASP
When the (signal G) is in the "1" state, the output signal J of the latch circuit 54 is in the "1" state during the period in which the REF clock signal 1 (signal H) is in the "1" state. In FIG.
Patterns P6 and P7 represent the former state, and pattern P9 represents the latter state. The patterns P8 and P10 represent the states at the boundary points of the two, but the output signal J is determined to be either the "1" state or the "0" state, and there is no problem in either circuit operation. , Both cases are overlaid.
The latch circuit 54 causes the REF clock signal 1 (signal H) only when the refresh operation requests overlap each other within the time td1 immediately after the fall of the RAS signal indicating the external read operation or write operation request. Is “1”
The signal J is in the "1" state only during the state.

The REF clock signal 2 (signal K) is a reference signal for the control signal REF actually sent to the refresh row decoder 2 and the refresh sense amplifier circuit 3, but the signal J is in the "1" state. R, only when the request for the refresh operation overlaps within the time td1 immediately after the fall of the RAS signal indicating the request for the read or write operation from the outside.
The EF clock signal 2 (signal K) reaches the logical sum (OR) circuit 59 after being delayed by the delay time td2 of the delay circuit 58 via the logical product (AND) circuit 57 and the delay circuit 58. In other cases, the REF clock signal 2 (signal K) reaches the logical sum (OR) circuit 59 directly through the logical product (AND) circuit 56.

The output signal P of the logical sum (OR) circuit 59 is the control signal REF, which is sent to the refresh row decoder 2 and the refresh sense amplifier circuit 3.
At that time, the delay time td2 of the delay circuit 58 is equal to the delay circuit 5
Similar to the delay time td1 of 1, the data input of the latch circuit 31 in the word line selector 4 is set to be equal to or more than the sum of the setup time and the hold time. Also, R
The conditions of the EF clock signal 1 (signal H) are that they are synchronized with the REF clock signal 2 (signal K), that the REF clock signal 2 (signal K) is in the "1" state. 1) pulse has a width necessary for surely passing either the logical product (AND) circuit 56 or the logical product (AND) circuit 57.

Referring to FIG. 7, request pattern 1 is a case where a refresh operation request and an external read operation or write operation request do not temporally overlap. The refresh row decoder 2 receiving the refresh control signal REF from the refresh control circuit 1 causes the refresh word line selection signal 2-N (N =
0, ..., 3) is output. At this time, the word line selection signal 8-N (N = 0, ..., 3) is assigned to the same row address.
Is not input, the refresh word line 201-N (N = 0, ...,
3) is activated. This refresh word line 20
1-N (N = 0, ..., 3), each transistor 200 of the memory cell MC group is turned on, and the data stored in each memory cell MC is refreshed by each refresh bit line 202-N. (N = 0, ..., 3) is read out and amplified by the refresh sense amplifier 3.
Refresh word line selection signal 2 after the lapse of a prescribed time
-N (N = 0, ..., 3) is invalidated, and each refresh bit line 20 amplified when the refresh word line 201-N (N = 0, ..., 3) becomes inactive.
The data on 2-N (N = 0, ..., 3) are respectively written in the original memory cells MC. At this time, the sense amplifier switching signal SAR is in the invalid state, and the refresh sense amplifier 3 is not connected to the input / output buffer 11 and is used only for the refresh operation.

The request pattern 2 is a case where a request for an external read operation or write operation is issued to the same row address while the refresh operation is being executed.

First, the refresh word line selection signal 2-
N (N = 0, ..., 3) is input to the word line selector 4, and the corresponding refresh word line 201-
N (N = 0, ..., 3) is activated. Until the word line selection signal 8-N (N = 0, ..., 3) is input, the refresh operation is executed similarly to the pattern P1. Here, the refresh word line 201-N (N =
When the word line selection signal 8-N (N = 0, ..., 3) is input before 0, ..., 3) are inactivated, the word line selector 4 causes the word line selector 4 to refresh. -N
The active state of (N = 0, ..., 3) is continued, and the word lines 101-N (N = 0, ..., 3) are not activated.
The word line selector 4 validates the sense amplifier circuit switching signal SAR and sends it to the bit line selector 5, and the bit line selector 5 connects the input / output buffer 11 from the sense amplifier circuit 9 to the refresh sense amplifier circuit 3.
Switch to. This state does not change even when the refresh word line selection signal 2-N (N = 0, ..., 3) becomes invalid, and the word line selection signal 8-N (N = 0, ...
・ Ends when 3) becomes invalid. As described above, regardless of the progress status of the refresh operation being executed, an external request for either a read operation or a write operation is performed by using the signal path used for the refresh operation and performing a specified read operation. Alternatively, the write operation is executed at the timing of either operation.

The request pattern 3 is a refresh word line selection after a request for an external read operation or write operation is issued to the same row address while the refresh operation is being executed. Signal 2-
While N (N = 0, ..., 3) is once invalidated and the word line selection signal 8-N (N = 0, ..., 3) is valid, for the same row address again. This is the case where the refresh word line selection signal 2-N (N = 0, ..., 3) is input.

In this case, when the request for the second refresh operation is issued, either the read operation or the write operation is executed for the row address, and this operation causes the same operation as the refresh operation. The effect can be obtained. Therefore, the second refresh operation can be invalidated and omitted.

The request pattern 4 is a case where a refresh operation request is issued to the same row address while either the external read operation or write operation is being executed.

The request pattern 5 is the word line selection signal 8 after a refresh operation request is issued to the same row address while either the external read operation or write operation is being executed. -N (N = 0,
.., 3) is once invalidated and the refresh word line selection signal 2-N (N = 0, ..., 3) is valid, while the word line selection signal 8 is again applied to the same row address. This is the case where -N (N = 0, ..., 3) is input.

By the above operation of the refresh control circuit 1, when the request for the refresh operation overlaps the request for the read operation or the write operation from the outside within a short time (time td1), the request for the refresh operation is delayed by the time td2. be able to.

Then, the word line selection signal 8-N (N =
0, ..., 3) are synchronized with the signal RASP, and the refresh word line selection signal 2-N (N =
Since 0, ..., 3) are synchronized with the control signal REF, the word line selection signal 8-N for the signal RASP
(N = 0, ..., 3) delay time and control signal REF
Refresh word line selection signal 2-N (N =
By appropriately adjusting the delay time of 0, ..., 3), the word line selection signal 8-N (N = 0 ,.
3) A predetermined time before and after the rising (td1 and td2
Within the shorter time), the rising edges of the refresh word line selection signals 2-N (N = 0, ..., 3) do not overlap, and the operation of the word line selector 4 is completely guaranteed. You can

As described above, according to the dynamic random access memory of the embodiment of the present invention, the word line 101-N (N = N) which is opposed to the word line 101-N (N = N) is arbitrarily received in any case while receiving external read / write access. 0,
... 3) and refresh word line 201-N (N =
The refresh operation of each memory cell row can be automatically executed internally without simultaneously activating 0, ..., 3).

Next, a second embodiment of the dynamic random access memory of the present invention will be described.

The second embodiment is different only in that the latch circuit 34 of the word line selector circuit 41 in the first embodiment is replaced with a D-type flip-flop circuit. The result of the logical product (AND) of the inverted output data of the D-type flip-flop circuit and the signal A is the logical product (AND) of the inverted output data of the latch circuit 31 and the signal A in the first embodiment. A result equal to the signal D obtained is obtained.

Next, a third embodiment of the dynamic random access memory of the present invention will be described in detail with reference to the drawings.

In the third embodiment, the REF clock generator 55 inside the refresh control circuit 1 in the first embodiment is not built in the DRAM, but a refresh clock is input from the outside of the DRAM through a dedicated terminal. The point is different.

Referring to FIG. 8, the REF clock generation circuit 70 is composed of a delay circuit 71 and a logical product (AND) circuit 72. From this, the REF clock signal 2 (signal K) can be generated internally by only inputting one clock signal matching the REF clock signal 1 (signal H) from the outside.

According to the third embodiment, since the REF clock generator is not built in the DRAM, the chip area can be reduced.

Further, when a plurality of DRAMs are used at one time, the refresh cycles of the plurality of DRAMs can be specified to be equal and independent of read / write access. It is not necessary to pay attention to the skew between clock signals input to each DRAM as long as the clock cycle is correct. Therefore, layout / wiring design of the clock signal control system is not difficult. Therefore, it is possible to share one or a plurality of refresh clock signals among a plurality of DRAMs without distinguishing between the DRAMs.

[0053]

As is apparent from the above description, according to the present invention, the row address for the refresh operation and the row address for either the external read operation or the write operation are monitored, Since the output from the sense amplifier and the output from the refresh sense amplifier are switched according to the time difference between these requests, the read / write access from the outside can be received arbitrarily and the word line and refresh The refresh operation for each memory cell row can be automatically executed internally without simultaneously activating the word line and the word line.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a memory cell of an embodiment of a dynamic random access memory of the present invention.

FIG. 2 is a block diagram showing a configuration of an embodiment of a dynamic random access memory of the present invention.

FIG. 3 is a block diagram showing a configuration of an embodiment of a control circuit and a refresh control circuit of the present invention.

FIG. 4 is a block diagram showing a configuration of an embodiment of a word line selector circuit of the present invention.

FIG. 5 is a block diagram showing a configuration of an embodiment of a sense amplifier switching circuit of the present invention.

FIG. 6 is a timing chart showing the operation of an embodiment of the control circuit and the refresh control circuit of the present invention.

FIG. 7 is a timing chart showing the operation of one embodiment of the word line selector of the present invention.

FIG. 8 is a block diagram showing a REF clock generation circuit according to a third embodiment of the present invention.

[Explanation of symbols]

 1 refresh control circuit 2 refresh row decoder 3 refresh sense amplifier circuit 4 word line selector 5 bit line selector 6 row address buffer 7 column address buffer 8 row decoder 9 sense amplifier circuit 10 column decoder 11 input / output data buffer 12 control circuit

Claims (6)

[Claims] 1. A dynamic random access memory including a refresh operation unit, wherein at least one of an external write operation and an external read operation is performed by using the refresh operation unit. Access memory. 2. A word line selection signal corresponding to a first request for either an external write operation or an external read operation, and a refresh corresponding to a second request for a refresh operation. Monitoring means for monitoring the bit line selection signal for use, a refresh sense amplifier for amplifying the stored data during the refresh operation, and the monitoring means, when the first request is made during execution of the refresh operation, A dynamic random access memory, which outputs the stored data amplified by the refresh sense amplifier to the outside. 3. A word line activated when operating in response to the first request, a sense amplifier that amplifies stored data when operating in response to the first request, and activated when operating in response to the second request. When the value of the word line selection signal and the value of the word line selection signal for refresh match from the result of the word line for refresh and the monitoring means, the time of the first request and the second request Either the word line or the refresh word line is activated according to the target order, and if they do not match, the word line is activated for the first request, and the word line is activated for the second request. Control means for activating a refresh word line, the sense amplifier and the refresh circuit based on a value of the word line selection signal and a value of the refresh word line Dynamic random access memory according to claim 2, further comprising a means for switching the sense amplifier. 4. A delay means for monitoring the first request and the second request and delaying the second request when a time difference between the first request and the second request is smaller than a specified value. 4. The dynamic random access memory according to claim 3, further comprising: 5. The delay means further includes first period determining means for determining a period for generating an instruction to delay the refresh operation, and second period determining means for determining a period for delaying the refresh operation. 5. The dynamic random access memory according to claim 4, wherein: 6. The pulse delay means for generating a pulse signal that is active only during the period determined by the first period determination means, and the refresh operation from the pulse signal generated by the pulse generation means. A clock generation circuit that generates a first clock signal that determines an instruction to delay and a second clock signal that determines the timing of a refresh operation, and refresh from the first clock signal and the second clock signal. 6. The dynamic random access memory according to claim 5, further comprising means for generating a signal instructing execution of an operation.