JP3489497B2 - Memory controller - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory controller for accessing SDRAM.

[0002]

2. Description of the Related Art The DRAM market has changed dramatically over the last few years, driven by the development of personal computers. In recent years, instead of DRAM, SDRAM (Sync
Honous DRAM) is becoming the mainstream.

FIG. 10 is a general timing chart when accessing a DRAM. In FIG. 10, the signals prefixed with '/' are shown in negative logic. The same applies hereinafter. When accessing a general DRAM, mainly a row address strobe (RAS) signal,
A column address strobe (CAS) signal and a write enable (WE) signal are used. The timing of these signals may be asynchronous with the clock of the system, and in fact, the timing of rising and falling of each signal is precisely determined.

First, at the time of reading shown in FIG.
The RAS address is output to the address line to activate the RAS signal, and then the CAS address is output to the address line to activate the CAS signal. At this time, W
The E signal remains inactive. Then, after a predetermined period of time t, the data is read from the address indicated by the RAS address and the CAS address and output to the data line, so that this is taken in by the I / O, MPU, or the like. The RAS signal and the CAS signal are returned to inactive, and one read operation is completed.

The same is true for the write operation shown in FIG. 10B, and the RAS address is output to the address line to activate the RAS signal. At the time of writing, the WE signal is activated and the data to be written is output to the data line before the CAS signal is activated. When the CAS address is output to the address line and the CAS signal is activated after the data on the data line is stabilized, the data is fetched from the data line at that timing and the DRAM
Is written to the address indicated by the RAS address and the CAS address. The RAS signal and the CAS signal are returned to inactive, and one write operation is completed.

FIG. 11 is a general timing chart when accessing the SDRAM. The SDRAM operates in synchronization with the clock. First, at the time of reading shown in FIG. 11A, the RAS address is output to the address line and R
The AS signal is activated for one clock in synchronization with the clock. After that, the CAS address is output to the address line, and the CAS signal is activated for one clock in synchronization with the clock. At this time, the WE signal remains inactive. Then, after a predetermined number of clocks called latency, data is read out to the data line for about one clock. I / O or MPU
Will be taken in. FIG. 11A shows an example in which the latency is 1.

At the time of writing shown in FIG. 11B, the RAS address is output to the address line and the RAS signal is activated for one clock in synchronization with the clock. After that, while outputting the CAS address to the address line,
The data to be written to the data line is output and the CAS signal and WE are output.
The signal is activated for one clock in synchronization with the clock. As a result, the data output to the data line is written in the SDRAM.

As can be seen with reference to FIGS. 10 and 11,
The timing and sequence at the time of access are different between the DRAM accessed asynchronously and the SDRAM accessed synchronously with the clock. In addition, for example, at the time of reading, data is output only for one clock period,
An MPU or I / O device compatible with DRAM cannot capture read data. in this way,
SDRAM cannot be treated like DRAM.

As described above, in recent years, SDRAM has become the mainstream in place of DRAM, and each company has begun to discontinue the production of conventional DRAM. Some high-end microprocessors are initially configured to support this SDRAM. However, in other microprocessors, conventional DRAM-compatible ones are still used, and SDRAM cannot be used as they are. Therefore, support for SDRAM has become essential.

For example, in a device incorporating a microprocessor such as a FAX, the one-chip microcomputer for embedded devices is slower to cope with the change in memory as described above, and SDRAM is excluded except for some high-end chips.
Few things have an interface with. Therefore, the SDRAM is the same as the DRAM used conventionally.
Was available.

As a method of accessing the SDRAM in the same manner as the DRAM, for example, the clock applied to the SDRAM is delayed, the data output time is lengthened when the data is read, and the MPU or I / O device can acquire the data. It is possible to But S
By slowing the clock given to the DRAM, the access time becomes very long.

Also, in the DMA, a mode for transferring data from memory to memory is used instead of data transfer to / from an I / O device. For example, reading data from SDRAM and transferring data to I / O device. It is also possible to output the data in another sequence. However, there is a problem in that the transfer time becomes long as a whole by performing each in an independent sequence.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and it is possible to access the SDRAM by a control signal similar to that of the DRAM.
It is an object of the present invention to provide a memory controller that allows an MPU or I / O device to reliably acquire data read from SDRAM.

[0014]

According to the present invention, in a memory controller, a RAS signal for a DRAM is converted to an SDRAM.
Generating RAS for converting into a RAS signal for use in DRAM
Generating means for converting the CAS signal for use in SDRAM to the CAS signal for SDRAM, system clock and C for DRAM
It is characterized in that it is provided with a clock generation means for generating a clock to the SDRAM based on the AS signal and the WE signal. In such a configuration, the RA for DRAM
When the S signal becomes active, S is synchronized with the clock.
Generate RAS signal for DRAM, then C for DRAM
When the AS signal becomes active, the CAS signal for SDRAM is generated in synchronization with the clock. And DRA
SDRA if the WE signal is not active after a predetermined number of clocks in response to the active CAS signal for M
The clock to M can be held and operated to be thinned out.

With such a configuration, the RA for DRAM
It is possible to convert the S signal and the CAS signal into control signals for SDRAM and further control the clock used in SDRAM. As a result, the SDRAM can be controlled using the control signal for the DRAM. According to the present invention, the SDRAM is the same as the conventional D from the viewpoint of MPU.
Since it can be handled like RAM, even a one-chip microcomputer that does not have an access mechanism for SDRAM can be used without problem.
DRAM can be used.

According to the present invention, in a memory controller for accessing an SDRAM, RAS generating means for generating a RAS signal in synchronization with a clock, CAS generating means for generating a CAS signal in synchronization with a clock, and SD.
The present invention is characterized by comprising clock generation means for holding and thinning the clock to the SDRAM after a predetermined number of clocks after the CAS signal is generated by the CAS generation means at the time of read access to the RAM.

As described above, since the read data is held in the SDRAM only for about 1 clock, the MP
U or I / O device cannot capture data. However, in any of the above-described inventions, when the WE signal for the DRAM is not active (that is, at the time of read access) in the clock generation means, the CAS signal is generated and becomes active in response to the predetermined clock number. Later, hold the clock and thin out. By this, S
The data read from the DRAM is held as it is because the clock is held. Therefore, DR
Even an MPU or I / O device compatible with AM can capture the read data without any problem. Further, in this case, the access time is delayed by the amount by which the clock is held and thinned out, but in general, the access time with the SDRAM is sufficiently faster than the I / O device or the like.
During DMA, the transfer can be completed within about the access time of the I / O device side. Therefore, DRAM
SD does not decrease the transfer speed compared to when using SD
Access using RAM can be performed.

[0018]

1 is a block diagram showing an embodiment of a memory controller of the present invention. 1 in the figure
Is MPU, 2 is SDRAM, 3 is an address bus, 4 is a data bus, 5 and 6 are level shifters, 11 is a clock generator, 12 is a CAS generator, 13 is a RAS generator, 14 is an AND circuit, and 15 is an OR circuit. Is. The MPU 1 has a function of controlling access to the conventional DRAM, and is connected to the control bus together with the address bus 3 and the data bus 4. Here, the DRAM is used as a control line necessary for memory access in the control bus.
Only the / MPURAS signal corresponding to the RAS signal, the / MPUCAS signal corresponding to the CAS signal, and the / MPUWE signal corresponding to the WE signal are shown.

The SDRAM 2 is a memory that operates in synchronization with a clock input as an SDCLK signal, and receives / RAS signals, / CAS signals, / WE signals and the like as control signals. In accordance with these control signals, the data on the data bus is written to the address specified by the row address and column address sent from the address bus 3, or the data is read from the specified address and output on the data bus 4. To do. Furthermore, by manipulating these control signals, various functions provided in the SDRAM 2 can be executed.

If the signal levels on the address bus 3 and the data bus 4 of the MPU 1 and SDRAM 2 are different,
It may be adjusted by the level shifters 5 and 6, respectively. Of course, if both have the same signal level, it is not necessary to provide the level shifters 5 and 6. In addition, normally SDRAM2
In order to provide a plurality of bits, a part of the address bus 3 is decoded to generate a chip select (/ CS) signal, but it is omitted here.

The clock generator 11 uses the system clock SYSCLK to generate a clock to be supplied to the SDRAM 2 and supplies it to the SDRAM 2 as an SDCLK signal. The clock generator 11 normally outputs the system clock SYSCLK as it is, but the SDRAM 2
When reading data from, the clock is held and thinned. In this example, the CAS generator 12 / MPU
A signal indicating the state of CAS and a signal obtained by calculating the logical product of the signal and the / MPUWE signal by the AND circuit 14 are received. If the / MPUWE signal is inactive, the / CAS signal is output before the SDRAM
After delaying for a predetermined latency when reading 2,
Holds and thins the clock while the / MPUCAS signal is active.

The clock generator 11 causes the SDR
The clock of the AM2 is held while the data is still output on the data bus 4. Therefore, the data output on the data bus 4 is held as it is while the clock is held. by this,
The data setup / hold time is secured in the MPU 1 and other I / O devices, and the data output on the data bus 4 can be acquired by the MPU 1 and other I / O devices.

The CAS generator 12 receives the / MPUCAS signal and converts it to the / CAS signal of the SDRAM 2 according to the inverted signal of the system clock SYSCLK. Specifically, when the / MPUCAS signal becomes active, the / CAS signal for one clock is output. Also C
The AS generation unit 12 has a function of / M to the clock generation unit 11.
The PUCAS signal is output as an inversion signal synchronized with the inversion signal of the system clock SYSCLK.

The RAS generator 13 receives the / MPURAS signal and converts it to the / RAS signal of the SDRAM 2 according to the inverted signal of the system clock SYSCLK. Specifically, when the / MPURAS signal becomes active, the / RAS signal for one clock is output.

The AND circuit 14 is provided to supply the / MPUWE signal to the clock generator 11 only while the / MPUCAS signal is active. In particular,
An inverted signal obtained by synchronizing the / MPUCAS signal with the inverted signal of the system clock SYSCLK is input from one of the input terminals from the CAS generation unit 12, and becomes "H" when the / MPUCAS signal becomes active ('L'). At this time, the signal input to the other input terminal is / MPUWE
The signal is output to the clock generation unit 11.

The OR circuit 15 generates the / WE signal of the SDRAM 2 from the / MPUWE signal output from the MPU 1. SDRAM 2 output from the CAS generator 12
/ CAS signal is input to one input terminal of the OR circuit 15. The / MPUWE signal input to the other input terminal is SDRA for one clock period during which the input / CAS signal becomes active ('L').
It is output to M2. Especially when writing / MPU
Since the WE signal becomes active, write / C
The / WE signal becomes active for one clock in synchronization with the AS signal.

With this configuration, the MPUs 1 to D
/ MPURAS signal output for RAM, / MPUC
The AS signal and / MPUWE signal are SDRAM
It is converted into a signal corresponding to 2. Therefore, SDRA is performed in the same way as when accessing the DRAM from the MPU 1.
M2 can be accessed. Further, for example, when reading data, it is possible to lengthen the time during which the data is output from the SDRAM 2 and control so that the MPU 1 and other I / O devices can take in the data, and the data is read reliably. You can

FIG. 2 is a circuit diagram showing a specific example in one embodiment of the memory controller of the present invention. In the figure,
The same parts as those in FIG. 1 are designated by the same reference numerals. 21,2
2, 25, 26, 28, 29, 34, 35, 36 are D-
Flip-flops, 23, 24, 27, 30, 33, 3
7, 42 are OR circuits, 31 is an RS-flip-flop,
AND circuits 32, 39, 40, 38 decoders, 4
Reference numerals 1 and 43 are multiplexers, and 44 is an address control unit.

The CAS generator 12 has a one-shot circuit composed of two D-flip-flops 21 and 22 and an OR circuit 23. OR circuit 24 / MPU
Calculates the logical sum of the RAS signal and the / MPUCAS signal,
The / MPUCAS signal is input to the one-shot circuit under the condition that the MPURAS signal is active ('L'). / MPUCAS signal becomes active,
1 according to the inverted signal of the system clock SYSCLK
The active signal for the clock is output to the OR circuit 15 and the multiplexer 41. This signal is multiplexer 4
1 to be the / CAS signal of the SDRAM 2.

Further, the output signal (/ MPUCAS signal) of the OR circuit 24 is output from the / Q terminal of the D-flip-flop 21 as an inverted signal synchronized with the inverted signal of the system clock SYSCLK. This signal is input to the AND circuit 14 and the clock generation unit 11 via the AND circuit 32.

The RAS generator 13 has a one-shot circuit composed of two D-flip-flops 25 and 26 and an OR circuit 27. The / MPURAS signal is input to the one-shot circuit, and when the / MPURAS signal becomes active, the active signal for one clock is output according to the inverted signal of the system clock SYSCLK. This output is SD through the multiplexer 43.
It becomes the / RAS signal of RAM2. This output is also AN
It is also input to the D circuit 39, the OR circuit 33, and the multiplexer 41.

The clock generator 11 has a delay circuit composed of two D-flip-flops 28 and 29. This delay circuit delays by a delay amount corresponding to the latency at the time of reading in the SDRAM 2, and here the case of latency = 1 is shown. When the delay amount is large, more D-flip-flops may be connected in series. This delay circuit normally outputs / MPUCAS from the AND circuit 32.
The signal is started and stopped according to an inverted signal which is synchronized with the inverted signal of the system clock SYSCLK. While this delay circuit is being activated, the AND circuit 14 causes / W
The E signal becomes valid. Therefore, after approximately / MPUCAS signal becomes active and delayed by the delay amount,
The WE signal is output to the OR circuit 30. Since the / WE signal is inactive at the time of reading from the SDRAM 2, the output of the OR circuit 30 is held at "H". As a result, the system clock SYSCLK is held at the time when the data is output during reading, and the data output time can be extended by thinning out SDCLK.

The AND circuit 39 includes the RAS generator 13, C
AS generator 12 and D-flip-flops 35, 3
6 and the OR circuit 37, the output of the 1-shot circuit is received, and when a 1-shot signal is output from any one, the signal is supplied to the SDRAM 2 as the / CS signal.

The other circuits are circuits for utilizing various functions other than writing to or reading from the SDRAM 2. An example of the operation of the basic circuit portion up to this point will be described. Here, in a portion which has not been described yet, it is assumed that the output of the OR circuit 37 is “H” and the output of the OR circuit 15 is output from the AND circuit 40 as the / WE signal of the SDRAM 2. Further, the multiplexer 41 is the O of the CAS generation unit 12.
The output of the R circuit 23 is selected and output, and this output becomes the / CAS signal of the SDRAM 2. Further, it is assumed that the multiplexer 43 selects the output of the RAS generation unit 13, and this output becomes the / RAS signal of the SDRAM 2.

FIG. 3 is a timing chart for a read access to the SDRAM 2 in the specific example of the embodiment of the memory controller of the present invention.
FIG. 4 is a timing chart for the same write access. The MPU 1 activates the / MPURAS signal as described in FIG.
Activate UCAS. At that time, / MPUWE
If the signal is active, write access is performed, and if it is inactive, read access is performed.

First, the read access will be described. First, the / MPURAS signal becomes active. Then, the one-shot circuit of the RAS generation unit 13 changes to / MPUR.
The signal that becomes active only for the first one clock when the AS signal becomes active is output. This signal is output from the multiplexer 43 to output / R in the SDRAM 2.
It becomes the AS signal. Further, it is output from the AND circuit 39 and becomes the / CS signal of the SDRAM 2. At this time, the address output on the address bus 3 is taken in as the RAS address.

Next, the / MPUCAS signal becomes active. At this time, the / MPURAS signal remains active, and the / MPUCAS signal changes to CA via the OR circuit 24.
It is input to the S generation unit 12. 1 of the CAS generation unit 12
The shot circuit outputs a signal that becomes active only for the first one clock when the / MPURAS signal becomes active. This is output from the multiplexer 41 and S
It becomes the / CAS signal in the DRAM 2. Also, CAS
A signal that is active for one clock output from the one-shot circuit of the generation unit 12 is output from the AND circuit 39 and becomes the / CS signal in the SDRAM 2. At this time, the address output on the address bus 3 is RA
It will be taken in as the S address.

When one shot signal is input as the / CAS signal, the SDRAM 2 outputs data for one clock to the data bus 4 after the number of clocks set as the latency in advance. Here, the latency is 1
I am trying.

When the / MPUCAS signal becomes active, the signal "H" is output from the inverted output of the D-flip-flop 21 in the CAS generator 12, and the AND circuit 32
The delay circuit of the clock generation unit 11 is activated via. This signal is also input to the AND circuit 14 and / MPU
The WE signal is input to the delay circuit. At the time of read access, the / MPUWE signal is inactive ('H'), and the output of the delay circuit is delayed by one clock for outputting the / CAS signal and one clock of latency to become'H '. Therefore, the output of the OR circuit 30 is'H '.
The system clock SYSCLK is thinned out and becomes the SDCLK signal. The thinned clocks are indicated by broken lines.

Since the SDRAM 2 cannot detect the falling edge of the SDCLK signal (clock), it holds the read data as it is. Therefore, the data remains on the data bus 4, so that the data can be acquired even after the MPU 1 or another I / O device, for example, holds a predetermined hold time.

After that, the / MPURAS signal, / MPUC
The AS signal is returned to inactive. / MPUCAS
When the signal becomes inactive, the operation of the delay circuit of the clock generation unit 11 is stopped, the output to the OR circuit 30 becomes “L”, and the system clock SYSCL is returned again.
K will be supplied to the SDRAM as the SDCLK signal. In the SDRAM 2 as well, the output of data is completed, and the standby state is entered.

Next, the write access will be described.
As with the read access, the / MPURAS signal first becomes active. Then, the one-shot circuit of the RAS generation unit 13 outputs a signal that becomes active only for the first one clock when the / MPURAS signal becomes active. This signal becomes the / RAS signal and / CS signal in the SDRAM 2. At this time, the address output on the address bus 3 is taken in as the RAS address.

Next, the / MPUWE signal becomes active. However, since the inactive ('H') signal is input from the CAS generator 12 to the OR circuit 15,
/ WE of the SDRAM 2 remains inactive ('H'). The data to be written in the SDRAM 2 is output to the data bus 4 by the time the / MPUWE signal becomes active. In the DRAM, wait a certain time until this data stabilizes, then
Activate the CAS signal.

When the / MPUCAS signal becomes active, the / MPUCAS signal becomes CAS via the OR circuit 24.
The 1-shot circuit of the CAS generation unit 12 outputs the signal that is input to the generation unit 12 and is activated only for the first one clock when the / MPURAS signal is activated. This is output from the multiplexer 41, and SDRA
It becomes the / CAS signal in M2. In addition, the AND circuit 39
And becomes the / CS signal in the SDRAM 2. At this time, the address output on the address bus 3 is taken in as the RAS address.

The output of the CAS generator 12 is ORed.
It is also input to the circuit 15 and only for one clock / MPUWE
The signal is output. Since the / MPUWE signal is already active, an active signal for one clock is output. This signal is sent to the SDR via the AND circuit 40.
It is input as the / WE signal of AM2.

Although the / MPUCAS signal is activated, the delay circuit of the clock generator 11 is activated as described above. However, since the / MPUWE signal is active ('L'), the output of the AND circuit 14 is output. Is'L '
Therefore, the output to the OR circuit 30 remains'L '.
Therefore, the system clock SYSCLK is directly supplied to the SDRAM 2 as the SDCLK signal without being thinned.

The SDRAM 2 receives 1 as the / CAS signal.
A shot signal is input, and a 1-shot signal is input as the / WE signal at the same timing. SDRA
The M2 takes in the data on the data bus 4 at this timing and writes the data to the address indicated by the row address and the column address.

After that, the / MPURAS signal, / MPUC
The AS signal and / MPUWE signal are returned to inactive. As the / MPUCAS signal becomes inactive, the operation of the delay circuit of the clock generation unit 11 is stopped,
The output to the OR circuit 30 becomes “L”, and the system clock SYSCLK becomes SDRA again as the SDCLK signal.
Will be supplied to M. Also in SDRAM2,
The output of data is completed and the device enters the standby state.

In this way, the MPU 1 side has a DRAM
Just by performing access control in the same manner as
Can be accessed. Also, for example, SDR
Since the data read from the AM2 is also retained for a period of several clocks, it can be normally acquired by the MPU1 and other I / O devices.

Returning to FIG. 2, circuits other than the above-mentioned basic part will be described. The circuit part described below is SD
It is a circuit for utilizing various functions other than writing to or reading from the RAM 2. FIG. 5 is an explanatory diagram of a part of functions provided in an example of the SDRAM and a signal value of a control signal when the function is used. In the figure,
H and L indicate signal levels, x indicates either H or L, and V indicates that the SDRAM 2 receives the value. In the table shown in FIG. 5, R
By executing the AS address and read, or the RAS address and write, data can be read and written from the SDRAM 2. These functions are performed by the clock generator 11, the CAS generator 12,
It is realized by the RAS generation unit 13 and the like.

Generally, when handling a DRAM, a refresh operation is performed. The refresh operation for this DRAM corresponds to the execution of auto refresh in FIG. D
In the RAM refresh operation, the / MPUCAS signal is activated first, and then the / MPURAS signal is activated, contrary to the read or write access. In this order, / MPURAS signal, / MPUCA
It is detected that the S signal is controlled, and a control signal for auto-refresh or self-refresh entry in the SDRAM 2 is generated.

As circuits for this purpose, an RS-flip-flop 31, an AND circuit 32, an OR circuit 33, a D-flip-flop 34, etc. are provided. The RS-flip-flop 31 receives the / MPUCAS signal at the S terminal and / M.
The PURAS signal is input to the R terminal. At the time of normal read or write access, / MP as described above
URAS signal becomes active first and then / MPU
Since the CAS signal becomes active, the output of the RS-flip-flop 31 maintains'H '. However, since the / MPUCAS signal becomes active first during refreshing, the output of the RS-flip-flop 31 changes to "L" and is maintained even after the / MPURAS signal becomes active. The output of the RS-flip-flop 31 is the AND circuit 32, the OR circuit 33, and the multiplexer 4
Input to 1.

In the OR circuit 33, when the output of the RS-flip-flop 31 becomes'L ', the / RAS signal for one clock output from the RAS generator 13 is sent as the clock of the D-flip-flop 34.

In the D-flip-flop 34, the / RAS signal for one clock from the OR circuit 33 is obtained as a clock, and the CKEI signal is latched to CK of the SDRAM 2.
Output as E signal. The CKEI signal is a signal indicating whether to perform auto refresh or self refresh entry. Normally, it remains at “H”, and auto refresh is executed. When the CKEI signal changes to "L" and the refresh operation is performed,
The CKE signal changes from "H" to "L", and at that time, the self-refresh operation starts. The D-flip-flop 34 is initialized by the / RESET signal when the power of the device is turned on.

In the refresh operation, / MPUWE
The signal remains inactive. That is, since it is the same as in the read access, the clock is held and thinned out as it is. To prevent this,
A signal sent from the CAS generation unit 12 to the clock generation unit 11 is sent to the output of the RS-flip-flop 31 by the AND circuit 32, and is “L” at the time of refresh operation.
I have to. As a result, the delay circuit of the clock generation unit 11 does not operate, and the clock is not held and thinned.

Further, the output of the RS-flip-flop 31 is inputted as one of the selection signals of the multiplexer 41, and the output from the RAS generator 13 is selected by changing the selection signal to "L". / CAS signal is output. That is, as the / CAS signal /
The same signal as the RAS signal is output. Also, the OR circuit 2
4, the CAS generator 12 does not operate even if the / MPUCAS signal becomes active, and then / MPURA
When the S signal becomes active, the CAS generator 12
Outputs an active signal for one clock. This is R
This is a signal equivalent to the AS generation unit 13. Further, an equivalent active signal for one clock is input to the AND circuit 39 from the RAS generation unit 13 and the CAS generation unit 12, and the same signal is output to the SDRAM 2 as a / CS signal.

FIG. 6 is a timing chart showing an example of performing the refresh operation on SDRAM 2 in the specific example of the embodiment of the memory controller of the present invention. First, the / MPUCAS signal becomes active, but nothing happens. After that, when the / MPURAS signal becomes active, the RAS generation unit 13 outputs an active signal for one clock to become the / RAS signal, and the output of the RS-flip-flop 31 becomes'L '. The output of the RS-flip-flop 31 outputs the / RAS signal as the / CAS signal. Further, the signal given by the CKEI signal is output as the CKE signal. The / WE signal remains inactive.

In this way, similarly to the case of refreshing in the DRAM, by activating / MPUCAS and then activating / MPURAS, the SDRAM 2 can be refreshed.

Returning to FIG. 2 again, the circuit portion for performing all-bank precharge and mode register setting shown in FIG. 5 will be described. The mode register set performs, for example, latency setting during reading, burst length setting during burst mode, and the like.

In order to execute these two functions, in this example, the MPU 1 makes an access to a specific address. The decoder 38
The specific address that directs the execution of these functions is decoded and the output becomes active ('L') when the specific address is output to the address bus.

The D-flip-flops 35 and 36 and the OR circuit 37 constitute a one-shot circuit, and the decoder 38
Outputs a signal that becomes active only for the first one clock after the output changes from'H 'to'L'. This signal is output as the / WE signal of the SDRAM 2 via the AND circuit 40. Also, through the AND circuit 39, SD
It is also output as the / CS signal of RAM2. Further, it is also input to the multiplexer 41 and the multiplexer 43.

The inverted signal of the output of the decoder 38 is output from the / Q terminal of the D-flip-flop 35 according to the clock. Normally, the output of the decoder 38 is "H", so "L" is output. When either the all bank precharge or the mode register set is executed, the output of the decoder 38 becomes "L", so that this D-
The output of the / Q terminal of the flip-flop 35 becomes "H".

The multiplexer 43 has a RAS generator 13
The output signal from the D-flip-flop 35 and the output signal from the one-shot circuit including the D-flip-flops 35 and 36 and the OR circuit 37 are input.
Either is selected by the output of the terminal. Normally, the output of the / Q terminal of the D-flip-flop 35 is'L ', so R
The output signal from the AS generator 13 is selected to output the SDRAM
2 / RAS signal is output. When either the all-bank precharge or the mode register set is executed, the output of the / Q terminal of the D-flip-flop 35 becomes "H", so that 1 is output from the OR circuit 37.
The shot signal is output as the / RAS signal of SDRAM2.

The OR circuit 42 includes the D-flip-flop 3
The output of the Q terminal of 5 is used as one input, and the A10 signal of the address bus 3 is used as the other input to perform a logical sum operation.
Since the output of the Q terminal of the D-flip-flop 35 is normally "H", the output of the OR circuit 42 is also "H". When either the all-bank precharge or the mode register set is executed, the output of the Q terminal of the D-flip-flop 35 becomes'L ', so that the A10 signal of the address bus 3 becomes valid. As can be seen from FIG. 5, the A10 signal of the address bus 3 is "H" in the all-bank precharge, and the A10 signal of the address bus 3 is "L" in the mode register set.
A signal corresponding to this is output from the OR circuit 42.

The multiplexer 41 has an OR with the power supply voltage.
The output of the circuit 37, the output of the RAS generation unit 13, and the CAS
From the four input signals output from the generator 12, one signal indicated by the selection signal is selected and output. As the selection signal, the output of the RS-flip-flop 31 and the output of the OR circuit 42 are input. Since the output of the OR circuit 42 is normally "H", the output of the CAS generator 12 is selected when the output of the RS-flip-flop 31 is "H". This corresponds to normal read and write. OR circuit 42
Output is “H” and the output of the RS-flip-flop 31 is “L”, the output of the RAS generation unit 13 is selected. This corresponds to the refresh operation. When executing either all-bank precharge or mode register set, basically the RS-flip-flop 31
Output is'H '. Since the output of the OR circuit 42 becomes "H" during the all bank precharge, the CAS
The output of the generator 12 is selected, but the signal remains inactive. OR when the mode register is set
Since the output of the circuit 42 becomes'L ', the output from the OR circuit 37 is selected. In this case, since the OR circuit 37 outputs a one-shot signal, this one-shot signal is S
It is input to the DRAM 2 as a / CAS signal.

In this way, during the all-bank precharge, the one-shot signal output from the one-shot circuit composed of the D-flip-flops 35 and 36 and the OR circuit 37 is the / RAS signal and the / WE signal of the SDRAM 2. It is output as the / CS signal, and the / CAS signal is not output. As a result, the all bank precharge function is executed. When the mode register is set, the one-shot signal output from the one-shot circuit composed of the D-flip-flops 35 and 36 and the OR circuit 37 is the / RAS signal, / CAS signal, / WE of the SDRAM 2.
Signal and / CS signal. As a result, the function of the mode register set is executed and the address bus 3
The above data is set in the mode register in SDRAM2.

As described above, S as shown in FIG.
Regarding the various functions provided in the DRAM 2, D
It can be executed from the MPU 1 that can only access the RAM.

The address control unit 44 is an SDRAM.
When 2 has a multi-bank configuration, a part of the address on the address bus 3 is BANK when the / RAS signal is output.
The signals are separated as signals, and the same bank is designated when the next / CAS signal is output.

The specific example shown in FIG. 2 is a logical value of each signal (active low or active high).
It is organized according to. If the logical value of each signal is different, it is necessary to change the circuit accordingly. Although the configuration is shown here as a circuit that realizes the functions illustrated in FIG. 5, unnecessary functions may be deleted or circuits may be added by adding functions. Further, the logical value of the signal for executing each function may be designed according to the SDRAM to be used. Further, FIG. 2 shows only a part necessary for the description, and may include other circuit parts. of course,
It is also optional to replace part of the circuit shown in FIG. 2 with another known circuit configuration.

FIG. 7 is a block diagram showing another embodiment of the memory controller of the present invention. In the figure, 51 is D
MA controller, 52 SDRAM interface,
53 is a clock generation unit, 61 is a CAS generation unit, and 62 is R
AS generator, 63 is a CS generator, and 64 is a WE generator. In this example, an example of accessing the SDRAM 2 using DMA is shown. SDR using DMA
When accessing the AM2, each signal given to the SDRAM2 can be newly generated in the interface portion. However, as described above, at the time of read access, for example, the time interval for reading the data from the SDRAM 2 is very short, and the I / I compatible with the conventional DRAM is used.
The O device may not be able to acquire the data read from the SDRAM 2. Therefore, it becomes necessary to perform access control for the SDRAM 2 as described above.

In the example shown in FIG. 7, the DMA controller 5
1 sequentially generates addresses from preset addresses and outputs them to the SDRAM interface 52. Of course, various controls are also performed, such as acquiring the bus use right for the MPU for DMA transfer.

The SDRAM interface 52 is a DMA
The address output from the controller 51 is acquired, and the data on the data bus is SDRAM-addressed to the address.
Write to 2 (write access) or SDRAM
Data is read from the address in 2 and output on the data bus (read access). The SDRAM interface 52 controls the SDRAM 2 during such write access and read access. In this example, the / CAS signal, / RAS signal, / CS signal, and / WE signal used in the SDRAM 2 are generated by the CAS generation unit 61, RAS generation unit 62, CS generation unit 63, and WE generation unit 64, respectively. These signals are generated in synchronization with the system clock SYSCLK, and the generation of each signal may be controlled by, for example, a sequencer or a control unit (not shown).

The clock generator 53 sends SDCL to the SDRAM 2 based on the system clock SYSCLK.
Generate a K signal. Specifically, normally, the system clock SYSCLK is directly used as the SCLK signal SDR.
Supply to AM2. In addition, when performing read access to the SDRAM 2, the SDRAM interface 5
After the / CAS signal is generated by the second CAS generation unit 61,
The clock is held after a predetermined number of clocks, and the system clock SYSCLK is thinned out and output. In this example, the read access or the write access is determined by the output from the WE generation unit 64.

Next, the operation of the memory controller according to another embodiment of the present invention will be briefly described. FIG. 8 shows S in another embodiment of the memory controller of the present invention.
6 is a timing chart when performing a read access to the DRAM 2. Here, an example is shown in which the data read from the SDRAM 2 is acquired by another I / O device. The DMA controller 51 activates the DACK signal for the I / O device, and
/ IOW signal is activated, and the address to be read is passed to the SDRAM interface.

In the SDRAM interface 52, CS
While the generator 63 activates the / CS signal,
A signal sequence for a series of read access to the SDRAM 2 is started. After outputting the row address, R
The AS generation unit 62 generates and outputs the / RAS signal for one clock. Then, after outputting the column address, C
The AS generation unit 61 generates and outputs the / CAS signal. As a result, the SDRAM 2 outputs the data designated by the address to the data bus after a predetermined number of clocks (latency).

On the other hand, the clock generator 53 holds the clock at the timing when the SDRAM 2 outputs the data, and SDCL is obtained by thinning out the system clock SYSCLK.
The K signal is supplied to the SDRAM 2. I / O devices are
Predetermined data setup time (Tw (R) in Fig. 8)
Is required. Therefore, the clock generator 53 holds and thins out the clock so as to satisfy the predetermined data setup time Tw (R). This makes S
The DRAM 2 continues to output the read data as it is.

In the meantime, the DMA controller 51 operates the I / O
The / IOW signal is returned to inactive for the device, and the I / O device takes in the data output on the data bus at this timing. In this way, S
The data read from the DRAM 2 is surely taken into the I / O device.

After that, the clock generator 53 stops holding the clock, the CS generator 63 of the SDRAM interface 52 inactivates the / CS signal, and the DMA controller 51 inactivates the DACK signal. End read access twice.

FIG. 9 is a timing chart in the case of performing write access to the SDRAM 2 in another embodiment of the memory controller of the present invention. Here, an example is shown in which the data output from the I / O device is written to the SDRAM 2. DMA controller 5
1 activates the DACK signal to the I / O device, activates the / IOR signal, and passes the address to be written to the SDRAM interface.

In the SDRAM interface 52, the CS
While the generator 63 activates the / CS signal,
A signal sequence for a series of write access to the SDRAM 2 is started. After outputting the row address, R
The AS generation unit 62 generates and outputs the / RAS signal for one clock. Then, after outputting the column address, C
The AS generation unit 61 generates the / CAS signal, and the WE generation unit 64 generates and outputs the / WE signal. As a result, the SDRAM 2 writes the data on the data bus to the designated address.

However, in the I / O device, the output of data is started after a predetermined time has elapsed after receiving the / IOR signal, and after the predetermined time Tw (W) has elapsed, the data becomes stable. It is assumed that the data will be received. Therefore, in order to surely write the data in the SDRAM 2, it is necessary to comply with this timing.
In the example shown in FIG. 9, after a predetermined time Tw (W) has elapsed from the timing at which data is output from the I / O device, the CAS generator 61 and the WE generator 64 output / CA.
The S signal and / WE signal are output. This ensures that the data output from the I / O device is SD
It can be written to RAM2.

After that, the CS generator 63 of the SDRAM interface 52 inactivates the / CS signal, and the DMA controller 51 makes the / IOR signal and the DAC.
The K signal is made inactive to complete one write access.

In this way, I / O is performed using DMA.
Even when data is transferred between the device and the SDRAM, the data read from the SDRAM 2 can be surely transferred to the I / O.
O device can receive. Also, the data output from the I / O device can be reliably stored in the SDRAM 2
Can be written on.

Although FIG. 8 and FIG. 9 show the timing charts for the read access or the write access only once, the same control is used to ensure the data access even when the burst mode of the SDRAM 2 is used. Transfer is possible.

[0085]

As is apparent from the above description, according to the present invention, the SDRAM can be controlled from the MPU or the like by using the control signal for the DRAM, and the one having no access mechanism for the SDRAM is provided. Even a chip microcomputer or the like can use the SDRAM without any problem. Also,
Even in the MPU or I / O device corresponding to the DRAM, there is an effect that the data read from the SDRAM can be surely acquired and the data can be surely written in the SDRAM.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory controller of the present invention.

FIG. 2 is a circuit diagram showing a specific example in one embodiment of the memory controller of the present invention.

FIG. 3 is a timing chart when performing a read access to the SDRAM 2 in the specific example of the embodiment of the memory controller of the present invention.

FIG. 4 is a timing chart when performing write access to the SDRAM 2 in the specific example of the embodiment of the memory controller of the present invention.

FIG. 5 is an explanatory diagram of a part of a function provided in an example of an SDRAM and a signal value of a control signal when the function is used.

FIG. 6 is a timing chart showing an example when a refresh operation is performed on the SDRAM 2 in the specific example of the embodiment of the memory controller of the present invention.

FIG. 7 is a block diagram showing another embodiment of the memory controller of the present invention.

FIG. 8 is a timing chart when a read access is performed to the SDRAM 2 in another embodiment of the memory controller of the present invention.

FIG. 9 is a timing chart when write access is performed to the SDRAM 2 in another embodiment of the memory controller of the present invention.

FIG. 10 is a general timing chart when accessing a DRAM.

FIG. 11 is a general timing chart when accessing an SDRAM.

[Explanation of symbols]

1 ... MPU, 2 ... SDRAM, 3 ... Address bus, 4 ...
Data bus, 5, 6 ... Level shifter, 11 ... Clock generation unit, 12 ... CAS generation unit, 13 ... RAS generation unit, 14
... AND circuit, 15 ... OR circuit, 21, 22, 25, 2
6, 28, 29, 34, 35, 36 ... D-flip-flops, 23, 24, 27, 30, 33, 37, 42 ... O
R circuit, 31 ... RS-flip-flop, 32, 39,
40 ... AND circuit, 38 ... Decoder, 41, 43 ... Multiplexer, 44 ... Address control section, 51 ... DMA controller, 52 ... SDRAM interface, 53 ... Clock generation section, 61 ... CAS generation section, 62 ... RAS generation section, 63 ... CS generator, 64 ... WE generator.

─────────────────────────────────────────────────── ─── Continued Front Page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 12/00-12/02 G11C 11/40-11/4099 G06F 15/78

Claims (3)

(57) [Claims] 1. A RAS generating means for converting a RAS signal for DRAM into an RAS signal for SDRAM, and a C for converting a CAS signal for DRAM into a CAS signal for SDRAM.
AS generation means, system clock and CA for DRAM
A memory controller comprising a clock generation means for generating a clock to an SDRAM based on an S signal and a WE signal. 2. The clock generation means, when the WE signal for DRAM is not active, CAS for DRAM
After a predetermined number of clocks in response to the signal active,
The memory controller according to claim 1, wherein the clock is held and thinned. 3. A memory controller for accessing an SDRAM, RAS generating means for generating a RAS signal in synchronization with a clock, and CA in synchronization with a clock.
CAS generating means for generating an S signal and the CAS generating means at the time of read access to the SDRAM.
SDRA after a predetermined number of clocks after the signal is generated
A memory controller comprising clock generation means for holding and thinning out a clock to M.