JP2001043127A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory controller which can access an SDRAM with a control signal similar to that of a DRAM and allows an MPU and an I/O device to securely obtain data read out of the SDRAM. SOLUTION: A /MPURAS signal and a /MPUCAS signal outputted from the MPU 1 are converted into a /RAS signal and a /CAS signal for an SDRAM 2 by a RAS generation part 13 and a CAS generation part 12. Further, a /MPUWE signal is converted into a /WE signal synchronized with the /CAS signal. A clock generation part 11 after outputting the /CAS signal at the time of read access to an SDRAM 2 holds and thins out a clock a specific number of clocks later and supplies the resulting signal as an SDCLK signal to the SDRAM 2. Consequently, data outputted from the SDRAM 2 are held as they are and the MPU 1 and I/O device are able to obtain the data in the same timing with the DRAM.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory controller for accessing an SDRAM.

[0002]

BACKGROUND OF THE INVENTION The DRAM market has changed dramatically in recent years, driven by the development of personal computers. In recent years, instead of DRAM, SDRAM (Sync
(Hronous DRAM) is becoming mainstream.

FIG. 10 is a general timing chart for accessing a DRAM. In FIG. 10, signals preceded by '/' are each represented by negative logic. The same applies hereinafter. When accessing a general DRAM, mainly a row address strobe (RAS) signal,
A column address strobe (CAS) signal and a write enable (WE) signal are used. The timing of these signals may be asynchronous with the clock of the system. Actually, the rise and fall timing of each signal is determined in detail.

First, at the time of reading shown in FIG.
An RAS address is output to the address line to activate the RAS signal, and thereafter, a CAS address is output to the address line to activate the CAS signal. At this time, W
The E signal remains inactive. Thereafter, after a predetermined period t, data is read from the address indicated by the RAS address and the CAS address and output to the data line, and this is taken in by the I / O or MPU. The RAS signal and the CAS signal are returned to inactive, and one read operation ends.

The same applies to the write operation shown in FIG. 10B, in which the RAS signal is output to the address line to activate the RAS signal. At the time of writing, the WE signal is activated before the CAS signal is activated, and data to be written is output to the data line. After the data on the data line is stabilized, a CAS address is output to the address line to activate the CAS signal.
RAS address and CAS address. The RAS signal and the CAS signal are returned to inactive, and one write operation ends.

FIG. 11 is a general timing chart for accessing the SDRAM. The SDRAM operates in synchronization with a clock. First, at the time of reading shown in FIG. 11A, the RAS address is output to the address line,
The AS signal is activated for one clock in synchronization with the clock. Thereafter, the CAS address is output to the address line, and the CAS signal is activated for one clock in synchronization with the clock. At this time, the WE signal remains inactive. Thereafter, after a predetermined number of clocks called a latency, data is read out to the data line by about one clock. I / O and MPU
And so on. FIG. 11A shows an example in which the latency is one.

At the time of writing shown in FIG. 11B, the RAS address is output to the address line, and the RAS signal is activated for one clock in synchronization with the clock. After that, while outputting the CAS address to the address line,
Outputs data to be written to the data line, and outputs the CAS signal and WE
The signal is activated for one clock in synchronization with the clock. As a result, the data output to the data line is written to the SDRAM.

As can be seen with reference to FIGS. 10 and 11,
Timing and sequence at the time of access differ between a DRAM accessed asynchronously and an SDRAM accessed in synchronization with a clock. Also, for example, at the time of reading, data is output only for a period of one clock.
An MPU or I / O device compatible with a DRAM cannot read the read data. in this way,
SDRAM cannot be treated like DRAM.

As described above, in recent years, SDRAMs have become the mainstream in place of DRAMs, and all companies have begun to discontinue conventional DRAM production. Some high-end microprocessors are initially configured to support this SDRAM. However, in other microprocessors, conventional microprocessor-compatible ones are still used, and the SDRAM cannot be used as it is. Therefore, support for SDRAM has become essential.

For example, in a device incorporating a microprocessor such as a facsimile, a one-chip microcomputer for embedded devices is slower to respond to changes in memory as described above, and except for some high-end chips, an SDRAM is used.
Few have an interface with. For this reason, SDRAMs are used in the same way as DRAMs conventionally used.
It was hoped that it could be used.

As a method of accessing the SDRAM in the same manner as the DRAM, for example, a clock given to the SDRAM is delayed, for example, a data output time when data is read is lengthened, and data can be acquired by an MPU or an I / O device. It can be considered. However, S
The access time becomes very long by delaying the clock applied to the DRAM.

The DMA also uses a mode in which data is transferred from memory to memory, instead of data transfer between I / O devices. For example, data is read from SDRAM and data is transferred to I / O devices. It is also possible to output data in another sequence. However, there is a problem in that the transfer time as a whole becomes long by performing each in an independent sequence.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and enables access to an SDRAM by a control signal similar to that of a DRAM.
It is an object of the present invention to provide a memory controller that allows an MPU or an I / O device to reliably acquire data read from an SDRAM.

[0014]

SUMMARY OF THE INVENTION The present invention relates to a memory controller, comprising:
Generating means for converting RAS signal into RAS signal for use with DRAM
Generating means for converting a CAS signal for the SDRAM into a CAS signal for the SDRAM, and clock generating means for generating a clock for the SDRAM based on the RAS signal, the CAS signal and the WE signal for the DRAM. Things. In such a configuration, when the RAS signal for the DRAM becomes active, the SDRA
A RAS signal for M is generated, and the next time the CAS signal for DRAM becomes active, the SDR is synchronized with the clock.
A CAS signal for AM is generated. Then, after a predetermined number of clocks in response to the activation of the CAS signal for the DRAM, if the WE signal is not active, the operation can be performed such that the clock to the SDRAM is held and thinned out.

With such a configuration, the RA for the DRAM
The S signal and the CAS signal can be converted into control signals for the SDRAM, and further, a clock used in the SDRAM can be controlled. Thus, the SDRAM can be controlled using the control signal for the DRAM. According to the present invention, from the viewpoint of the MPU, the SDRAM is a conventional DRAM.
Since it can be handled like a RAM, even a one-chip microcomputer without an access mechanism for SDRAM can
A DRAM can be used.

According to the present invention, in a memory controller for accessing an SDRAM, a RAS generating means for generating a RAS signal in synchronization with a clock, a CAS generating means for generating a CAS signal in synchronization with a clock,
Clock reading means for holding and decimating the clock to the SDRAM after a predetermined number of clocks after the CAS signal is generated by the CAS generating means at the time of read access to the RAM.

As described above, in the SDRAM, the read data is held for only about one clock.
U or I / O device cannot capture data. However, in any of the above-mentioned inventions, when the WE signal for the DRAM is not active (that is, at the time of read access), the clock generating means responds to the generation of the CAS signal and becomes active in response to the generation of the CAS signal. Later, hold the clock and thin out. This gives S
The data read from the DRAM is held as it is because the clock is held. Therefore, DR
Even an MPU or an I / O device compatible with AM can take in the read data without any problem. Also, in this case, the access time is delayed by the amount of holding and decimating the clock, but generally the access time with the SDRAM is sufficiently faster than that of an I / O device or the like.
At the time of DMA, the transfer can be completed in about the access time of the I / O device or the like. Therefore, DRAM
Compared to the case using
Access using the RAM can be performed.

[0018]

FIG. 1 is a block diagram showing an embodiment of a memory controller according to the present invention. In the figure, 1
Is an MPU, 2 is an SDRAM, 3 is an address bus, 4 is a data bus, 5 and 6 are level shifters, 11 is a clock generator, 12 is a CAS generator, 13 is a RAS generator, 14 is an AND circuit, and 15 is an OR circuit. It is. The MPU 1 has a function of performing control for accessing a conventional DRAM, and is connected to the control bus together with the address bus 3 and the data bus 4. Here, a DRAM is used as a control line necessary for memory access in the control bus.
Only the / MPURAS signal corresponding to the RAS signal, the / MPUCAS signal corresponding to the CAS signal, and the / MPUWE signal corresponding to the WE signal are shown.

The SDRAM 2 is a memory that operates in synchronization with a clock input as an SDCLK signal, and receives a / RAS signal, a / CAS signal, a / WE signal and the like as control signals. In accordance with these control signals, data on the data bus is written to an address specified by a row address and a column address sent on the address bus 3, and data is read from the specified address and output on the data bus 4. I do. Further, by operating these control signals, various functions provided in the SDRAM 2 can be executed.

If the signal levels on the address bus 3 and the data bus 4 of the MPU 1 and the SDRAM 2 are different,
The adjustment may be made by the level shifters 5 and 6, respectively. Of course, if both are at the same signal level, there is no need to provide the level shifters 5 and 6. Normally, SDRAM2
Are provided, a part of the address bus 3 is decoded to generate a chip select (/ CS) signal, which is omitted here.

The clock generator 11 generates a clock to be supplied to the SDRAM 2 using the system clock SYSCLK, and supplies it to the SDRAM 2 as an SDCLK signal. The clock generator 11 normally outputs the system clock SYSCLK as it is.
At the time of reading data from, the clock is held and thinned out. In this example, the CAS generation unit 12 sends the / MPU
A signal indicating the CAS state and a signal obtained by calculating the logical product of the signal and the / MPUWE signal by the AND circuit 14 are received. When the / MPUWE signal is inactive, the / CAS signal is output before the SDRAM
After a delay of a predetermined latency at the time of reading 2,
While the / MPUCAS signal is active, the clock is held and thinned out.

The clock generator 11 generates the SDR
In AM2, the clock is held while data is output on the data bus 4. Therefore, the data output on the data bus 4 is held as it is while holding the clock. by this,
A data setup / hold time in the MPU 1 and other I / O devices is secured so that the data output on the data bus 4 can be acquired by the MPU 1 and other I / O devices.

The CAS generator 12 receives the / MPUCAS signal and converts it into a / CAS signal of the SDRAM 2 according to an inverted signal of the system clock SYSCLK. Specifically, when the / MPUCAS signal becomes active, the / CAS signal for one clock is output. Also C
The AS generation unit 12 sends a / M to the clock generation unit 11.
The PUCAS signal is output as an inverted signal synchronized with the inverted signal of the system clock SYSCLK.

The RAS generator 13 receives the / MPURAS signal and converts it into a / RAS signal of the SDRAM 2 according to an inverted signal of the system clock SYSCLK. Specifically, when the / MPURAS signal becomes active, one clock worth of / RAS signal is output.

The AND circuit 14 is provided to supply the / MPUWE signal to the clock generator 11 only while the / MPUCAS signal is active. In particular,
An inverted signal obtained by synchronizing the / MPUCAS signal with the inverted signal of the system clock SYSCLK from the CAS generation unit 12 is input to one input terminal. When the / MPUCAS signal becomes active ('L'), it becomes 'H'. At this time, the / MPUWE input to the other input terminal
The signal is output to the clock generation unit 11.

The OR circuit 15 generates the / WE signal of the SDRAM 2 from the / MPUWE signal output from the MPU 1. SDRAM 2 output from CAS generation unit 12
/ CAS signal is input to one input terminal of the OR circuit 15. The / MPUWE signal input to the other input terminal is applied to the SDRA signal during the period of one clock when the input / CAS signal becomes active ('L').
Output to M2. In particular, when writing / MPU
Since the WE signal becomes active, / C
In synchronization with the AS signal, the / WE signal becomes active for one clock.

With such a configuration, MPU 1
/ MPURAS signal output for RAM, / MPUC
AS signal and / MPUWE signal are each SDRAM
The signal is converted into a signal corresponding to 2. Therefore, in the same manner as when accessing the DRAM from the MPU 1, the SDRA
M2 can be accessed. In addition, for example, when reading data, the time during which data is output from the SDRAM 2 can be lengthened, and control can be performed so that the MPU 1 and other I / O devices can take in the data. Can be.

FIG. 2 is a circuit diagram showing a specific example of one embodiment of the memory controller of the present invention. In the figure,
1 are given the same reference numerals. 21 and 2
2,25,26,28,29,34,35,36 are D-
Flip-flops, 23, 24, 27, 30, 33, 3
7, 42 are OR circuits, 31 is an RS flip-flop,
32, 39 and 40 are AND circuits, 38 is a decoder,
Reference numerals 1 and 43 are multiplexers and 44 is an address control unit.

The CAS generator 12 has a one-shot circuit composed of two D-flip-flops 21 and 22 and an OR circuit 23. / MPU by OR circuit 24
The logical sum of the RAS signal and the / MPUCAS signal is calculated,
Under the condition that the MPURAS signal is active ('L'), the / MPUCAS signal is input to the one-shot circuit. When the / MPUCAS signal becomes active,
1 according to the inverted signal of the system clock SYSCLK.
The active signal for the clock is output to the OR circuit 15 and the multiplexer 41. This signal is output to multiplexer 4
1 to the / CAS signal of the SDRAM 2.

The output signal (/ MPUCAS signal) of the OR circuit 24 is output from the / Q terminal of the D-flip-flop 21 as an inverted signal synchronized with the inverted signal of the system clock SYSCLK. This signal is input to the AND circuit 14 and the clock generation unit 11 via the AND circuit 32.

The RAS generator 13 has a one-shot circuit composed of two D-flip-flops 25 and 26 and an OR circuit 27. When the / MPURAS signal is input to the one-shot circuit and the / MPURAS signal becomes active, an active signal for one clock is output according to the inverted signal of the system clock SYSCLK. This output is output to the SD via the multiplexer 43.
This becomes the / RAS signal of RAM2. This output is
It is also input to the D circuit 39, the OR circuit 33, and the multiplexer 41.

The clock generator 11 has a delay circuit composed of two D flip-flops 28 and 29. This delay circuit delays by a delay amount corresponding to the latency at the time of reading in the SDRAM 2, and here, the case where the latency = 1 is shown. When the delay amount is large, more D-flip-flops may be connected in series. This delay circuit normally outputs / MPUCAS output from the AND circuit 32.
The signal is started and stopped according to an inverted signal obtained by synchronizing the signal with the inverted signal of the system clock SYSCLK. While this delay circuit is activated, the AND circuit 14 outputs / W
The E signal becomes valid. Therefore, approximately after the / MPUCAS signal becomes active and is delayed by the delay amount,
The WE signal is output to the OR circuit 30. Since the / WE signal is inactive when reading from the SDRAM 2, the output of the OR circuit 30 is held at "H". Thus, the system clock SYSCLK is held at the time when data is output during reading, and the data output time can be extended by thinning out SDCLK.

The AND circuit 39 includes the RAS generator 13 and C
AS generator 12 and D-flip-flops 35 and 3
6 and the output of the one-shot circuit composed of the OR circuit 37, and when a one-shot signal is output from any one of them, the signal is supplied to the SDRAM 2 as a / CS signal.

The other circuits are circuits for utilizing various functions other than writing to or reading from the SDRAM 2. An example of the operation of the basic circuit part up to this point will be described. Here, it is assumed that the output of the OR circuit 37 is “H” and the output of the OR circuit 15 is output from the AND circuit 40 as the / WE signal of the SDRAM 2 in a portion which has not been described yet. The multiplexer 41 is connected to the Os of the CAS generator 12.
The output of the R circuit 23 is selected and output, and this output becomes the / CAS signal of the SDRAM 2. Further, it is assumed that the multiplexer 43 has selected the output of the RAS generation unit 13, and this output is the / RAS signal of the SDRAM 2.

FIG. 3 is a timing chart for a read access to the SDRAM 2 in a specific example of one embodiment of the memory controller of the present invention.
FIG. 4 is a timing chart when write access is performed. After activating the / MPURAS signal as described with reference to FIG.
Activate UCAS. At that time, / MPUWE
If the signal is active, it is write access, and if it is inactive, it is read access.

First, the case of read access will be described. First, the / MPURAS signal becomes active. Then, the one-shot circuit of the RAS generation unit 13 is set to / MPUR
A signal that is activated only for the first clock when the AS signal is activated is output. This signal is output from the multiplexer 43 to output / R in SDRAM2.
AS signal. Also, the signal is output from the AND circuit 39 and becomes the / CS signal of the SDRAM 2. At this time, the address output on the address bus 3 is taken in as the RAS address.

Next, the / MPUCAS signal becomes active. At this time, the / MPURAS signal remains active, and the / MPUCAS signal is
It has been input to the S generator 12. 1 of the CAS generation unit 12
The shot circuit outputs a signal that becomes active only for the first clock when the / MPURAS signal becomes active. This is output from the multiplexer 41 and S
This becomes the / CAS signal in the DRAM 2. Also, CAS
The signal that is active for one clock and output from the one-shot circuit of the generation unit 12 is output from the AND circuit 39 and becomes the / CS signal in the SDRAM 2. At this time, the address output on the address bus 3 is
It will be captured as an S address.

When a one-shot signal is input as the / CAS signal, the SDRAM 2 outputs data to the data bus 4 for one clock after the number of clocks set in advance as a latency. Here the latency is 1
And

When the / MPUCAS signal becomes active, an “H” signal is output from the inverted output of the D-flip-flop 21 in the CAS generator 12 and the AND circuit 32
To activate the delay circuit of the clock generation unit 11 via the. Further, this signal is also input to the AND circuit 14, and / MPU
The WE signal is input to the delay circuit. At the time of read access, the / MPUWE signal is inactive ('H'), and the output of the delay circuit becomes 'H' with a delay of one clock for outputting the / CAS signal and one clock of latency. Therefore, the output of the OR circuit 30 is “H”.
And the system clock SYSCLK is thinned out to become an SDCLK signal. The thinned clock is indicated by a broken line.

Since the SDRAM 2 cannot detect the falling edge of the SDCLK signal (clock), it holds the read data as it is. Therefore, since data remains on the data bus 4, the data can be obtained even after the MPU 1 or another I / O device has a predetermined hold time.

Thereafter, the / MPURAS signal, / MPUC
The AS signal is returned to inactive. / MPUCAS
When the signal becomes inactive, the operation of the delay circuit of the clock generation unit 11 stops, the output to the OR circuit 30 becomes “L”, and the system clock SYSCL is returned again.
K will be supplied to the SDRAM as the SDCLK signal. The SDRAM 2 also finishes outputting data and enters a standby state.

Next, write access will be described.
As in the case of the read access, first, the / MPURAS signal becomes active. Then, the one-shot circuit of the RAS generation unit 13 outputs a signal that has been activated only for the first clock in which the / MPURAS signal has been activated. This signal becomes the / RAS signal and / CS signal in the SDRAM 2. At this time, the address output on the address bus 3 is taken in as the RAS address.

Next, the / MPUWE signal becomes active. However, since an inactive ('H') signal is input from the CAS generation unit 12 to the OR circuit 15,
/ WE of SDRAM2 remains inactive ('H'). By the time the / MPUWE signal becomes active, data to be written to the SDRAM 2 has been output to the data bus 4. In the DRAM, after a predetermined time has passed until this data is stabilized, / MPU
Activate the CAS signal.

When the / MPUCAS signal becomes active, the / MPUCAS signal becomes CAS via the OR circuit 24.
The signal is input to the generation unit 12, and the one-shot circuit of the CAS generation unit 12 outputs a signal that is activated only for the first clock in which the / MPURAS signal is activated. This is output from the multiplexer 41 and the SDRA
It becomes the / CAS signal in M2. AND circuit 39
, And becomes the / CS signal in the SDRAM 2. At this time, the address output on the address bus 3 is taken in as the RAS address.

The output of the CAS generation unit 12 is OR
It is also input to the circuit 15 and only for one clock / MPUWE
A signal is output. Since the / MPUWE signal is already active, an active signal for one clock is output. This signal is sent through the AND circuit 40 to the SDR
It is input as the / WE signal of AM2.

When the / MPUCAS signal becomes active, the delay circuit of the clock generator 11 is activated as described above. However, since the / MPUWE signal is active ('L'), the output of the AND circuit 14 is output. Is 'L'
And the output to the OR circuit 30 remains 'L'.
Therefore, the system clock SYSCLK is supplied to the SDRAM 2 as the SDCLK signal without being thinned out.

The SDRAM 2 has 1 as the / CAS signal.
A shot signal is input, and a one-shot signal is input at the same timing as the / WE signal. SDRA
M2 takes in the data on the data bus 4 at this timing and writes the data to the address indicated by the row address and the column address.

Thereafter, the / MPURAS signal, / MPUC
The AS signal and the / MPUWE signal are returned to inactive. When the / MPUCAS signal becomes inactive, the operation of the delay circuit of the clock generation unit 11 stops,
The output to the OR circuit 30 becomes “L”, and the system clock SYSCLK is again output as the SDCLK signal by the SDRA signal.
M. Also in SDRAM2,
The data output ends, and the system enters a standby state.

As described above, the MPU 1 has the DRAM
Just by performing access control in the same manner as
It is possible to access. Also, for example, SDR
The data read from the AM 2 is also held for a period of several clocks, so that the MPU 1 and other I / O devices can normally acquire the data.

Returning to FIG. 2, circuits other than the above-described basic parts will be described. The circuit part described below is SD
This is a circuit for utilizing various functions other than writing to or reading from the RAM 2. FIG. 5 is an explanatory diagram of some of the functions provided in an example of the SDRAM and signal values of control signals when using the functions. In the figure,
H and L indicate signal levels, X indicates that the signal level may be either H or L, and V indicates that the SDRAM 2 receives the value. In the table shown in FIG.
By executing the AS address and the read or the RAS address and the write, data can be read and written from the SDRAM 2. These functions are performed by the above-described clock generator 11, CAS generator 12,
This is realized by the RAS generation unit 13 and the like.

Usually, a refresh operation is performed when a DRAM is handled. This refresh operation for the DRAM corresponds to the execution of the auto refresh in FIG. D
In the RAM refresh operation, the / MPUCAS signal is activated first, and then the / MPURAS signal is activated, contrary to the read or write access. In this order, the / MPURAS signal, / MPUCA
Upon detecting that the S signal has been controlled, a control signal for an auto-refresh or self-refresh entry in the SDRAM 2 is generated.

For this purpose, an RS flip-flop 31, an AND circuit 32, an OR circuit 33, a D flip-flop 34 and the like are provided. In the RS-flip-flop 31, the / MPUCAS signal is supplied to the S terminal and the / M
The PURAS signal is input to the R terminal. During normal read or write access, / MP
The URAS signal becomes active first, and then the / MPU
Since the CAS signal becomes active, the output of the RS-flip-flop 31 maintains 'H'. However, at the time of refresh, the / MPUCAS signal becomes active first, so that the output of the RS-flip-flop 31 changes to “L” and is maintained even after the / MPURAS signal becomes active. The output of the RS-flip-flop 31 is supplied to an AND circuit 32, an OR circuit 33, a multiplexer 4
1 is input.

When the output of the RS-flip-flop 31 becomes 'L', the OR circuit 33 sends out the / RAS signal for one clock output from the RAS generator 13 as the clock of the D-flip-flop 34.

In the D-flip-flop 34, the / RAS signal for one clock from the OR circuit 33 is obtained as a clock, the CKEI signal is latched, and the CK of the SDRAM 2 is
Output as E signal. This CKEI signal is a signal indicating whether to execute auto refresh or self refresh entry. Normally, it remains at “H”, and the auto refresh is executed. When the CKEI signal changes to 'L' and the refresh operation is performed,
The CKE signal changes from “H” to “L”, at which point the operation shifts to a self-refresh operation. The D-flip-flop 34 is initialized by a / RESET signal when the power of the device is turned on.

At the time of the refresh operation, / MPUWE
The signal remains inactive. That is, since the operation is the same as in the read access, the clock is held and thinned out as it is. To prevent this,
The signal sent from the CAS generation unit 12 to the clock generation unit 11 is output from the RS-flip-flop 31 by the AND circuit 32, and is "L" at the time of the refresh operation.
I have to. As a result, the delay circuit of the clock generation unit 11 does not operate, and the clock is not held and thinned.

Further, the output of the RS-flip-flop 31 is input as one of the selection signals of the multiplexer 41, and the output from the RAS generator 13 is selected by changing this selection signal to 'L'. / CAS signal. That is, as the / CAS signal /
The same signal as the RAS signal is output. OR circuit 2
4, the CAS generation unit 12 does not operate even if the / MPUCAS signal becomes active,
When the S signal becomes active, the CAS generator 12
Outputs an active signal for one clock. This is R
This signal is equivalent to that of the AS generation unit 13. Further, an equivalent active signal for one clock is input to the AND circuit 39 from the RAS generator 13 and the CAS generator 12, and the same signal is output to the SDRAM 2 as a / CS signal.

FIG. 6 is a timing chart showing an example when a refresh operation is performed on the SDRAM 2 in a specific example of one embodiment of the memory controller of the present invention. First, the / MPUCAS signal becomes active, but does nothing. Thereafter, when the / MPURAS signal becomes active, the RAS generation unit 13 outputs an active signal for one clock to become the / RAS signal, and the output of the RS-flip-flop 31 becomes 'L'. By the output of the RS-flip-flop 31, the / RAS signal is output as the / CAS signal. Further, a signal given by the CKEI signal is output as the CKE signal. Note that the / WE signal remains inactive.

In this manner, similarly to the case of refreshing in the DRAM, by activating / MPUCAS and then activating / MPURAS, refreshing in the SDRAM 2 can be performed.

Returning to FIG. 2, a circuit portion for performing all-bank precharge and mode register set shown in FIG. 5 will be described. The mode register set performs, for example, setting of a latency at the time of reading, and setting of a burst length at the time of burst mode.

In order to execute these two functions, in this example, it is executed by, for example, accessing a specific address from the MPU 1. The decoder 38
A specific address instructing the execution of these functions is decoded, and when the specific address is output to the address bus, the output is activated ('L').

The D-flip-flops 35 and 36 and the OR circuit 37 constitute a one-shot circuit.
The signal which becomes active only for the first clock after the output changes from "H" to "L". This signal is output as the / WE signal of SDRAM 2 via AND circuit 40. In addition, the SD
It is also output as the / CS signal of RAM2. Further, it is also input to the multiplexer 41 and the multiplexer 43.

From the / Q terminal of the D flip-flop 35, an inverted signal of the output of the decoder 38 is output in accordance with the clock. Normally, the output of the decoder 38 is "H", so that "L" is output. When either the all-bank precharge or the mode register set is executed, the output of the decoder 38 becomes "L".
The output of the / Q terminal of the flip-flop 35 becomes 'H'.

The multiplexer 43 includes the RAS generator 13
, And an output signal from a one-shot circuit composed of D-flip-flops 35 and 36 and an OR circuit 37.
Either is selected by the output of the terminal. Normally, the output of the / Q terminal of the D-flip-flop 35 is "L",
An output signal from the AS generation unit 13 is selected and the SDRAM is selected.
2 as the / RAS signal. When executing either the all-bank precharge or the mode register set, the output of the / Q terminal of the D-flip-flop 35 becomes “H”, so that the 1 output from the OR circuit 37 is output.
The shot signal is output as the / RAS signal of SDRAM2.

The OR circuit 42 includes a D-flip-flop 3
The output of the Q terminal 5 is used as one input, and the A10 signal of the address bus 3 is used as the other input to perform a logical sum operation.
Normally, the output of the Q terminal of the D-flip-flop 35 is “H”, so that the output of the OR circuit 42 is also “H”. When executing either the all-bank precharge or the mode register set, the output of the Q terminal of the D-flip-flop 35 becomes “L”, so that the A10 signal of the address bus 3 becomes valid. As can be seen from FIG. 5, the A10 signal on the address bus 3 is "H" during all-bank precharge, and the "A10" signal on the address bus 3 is "L" when the mode register is set.
A signal corresponding to this is output from the OR circuit 42.

The multiplexer 41 is connected to the power supply voltage and the OR.
The output of the circuit 37, the output of the RAS generator 13,
From the four input signals of the output of the generation unit 12, one signal indicated by the selection signal is selected and output. The output of the RS-flip-flop 31 and the output of the OR circuit 42 are input as selection signals. Normally, since the output of the OR circuit 42 is “H”, the output of the CAS generator 12 is selected when the output of the RS-flip-flop 31 is “H”. This corresponds to normal reading and writing. OR circuit 42
Is "H" and the output of the RS-flip-flop 31 is "L", the output of the RAS generator 13 is selected. This corresponds to a refresh operation. When performing either the all-bank precharge or the mode register set, basically, the RS-flip-flop 31
Is 'H'. Since the output of the OR circuit 42 becomes "H" at the time of all-bank precharge, CAS
The output of generator 12 is selected, but the signal remains inactive. OR when mode register set
Since the output of the circuit 42 becomes “L”, the output from the OR circuit 37 is selected. In this case, a one-shot signal is output from the OR circuit 37.
The signal is input to the DRAM 2 as a / CAS signal.

As described above, at the time of all-bank precharge, the one-shot signal output from the one-shot circuit constituted by the D-flip-flops 35 and 36 and the OR circuit 37 outputs the / RAS signal, / WE signal, The signal is output as the / CS signal and the / CAS signal is not output. Thereby, the function of all-bank precharge is executed. When the mode register is set, the one-shot signal output from the one-shot circuit composed of the D-flip-flops 35 and 36 and the OR circuit 37 outputs the / RAS signal, / CAS signal and / WE of the SDRAM 2.
The signal is output as a / CS signal. As a result, the function of the mode register set is executed, and the address bus 3
The above data is set in the mode register in SDRAM2.

As described above, S as shown in FIG.
Various functions provided in the DRAM 2 are also
It can be executed from the MPU 1 that can only access the RAM.

The address control unit 44 is an SDRAM
2 has a plurality of banks, a part of the address on the address bus 3 is set to BANK when the / RAS signal is output.
The same bank is designated when the next / CAS signal is output.

In the specific example shown in FIG. 2, the logical value of each signal (active low or active high)
It is assembled according to. If the logic value of each signal is different, it is necessary to change the circuit accordingly. Although the configuration is shown here as a circuit that realizes the functions shown in FIG. 5, it is optional to delete unnecessary functions or add circuits by adding functions. Furthermore, the logic value of the signal for executing each function may be designed according to the SDRAM to be used. Further, FIG. 2 shows only a portion necessary for description, and may include other circuit portions. of course,
It is optional to replace a part of the circuit shown in FIG. 2 with another known circuit configuration.

FIG. 7 is a block diagram showing another embodiment of the memory controller of the present invention. In the figure, 51 is D
MA controller, 52 is an SDRAM interface,
53 is a clock generator, 61 is a CAS generator, and 62 is R
The AS generation unit, 63 is a CS generation unit, and 64 is a WE generation unit. In this example, an example is shown in which access to the SDRAM 2 is performed using DMA. SDR using DMA
When accessing the AM2, each signal given to the SDRAM2 can be newly generated at the interface portion. However, as described above, at the time of read access, for example, the time interval at which data is read from the SDRAM 2 is very short, and the I / O corresponding to the conventional DRAM is performed.
In some cases, data read from the SDRAM 2 cannot be acquired by the O device. Therefore, it is necessary to perform the same access control to the SDRAM 2 as described above.

In the example shown in FIG.
1 sequentially generates addresses from a preset address and outputs the generated addresses to the SDRAM interface 52, for example. Of course, various controls are performed, such as acquiring the bus use right to the MPU for the DMA transfer.

The SDRAM interface 52 has a DMA
An address output from the controller 51 is obtained, and the data on the data bus is transferred to the SDRAM for the address.
2 (write access) or SDRAM
The data is read from the address in 2 and output on the data bus (read access). The SDRAM interface 52 controls the SDRAM 2 during such write access and read access. In this example, the / CAS signal, the / RAS signal, the / CS signal, and the / WE signal used in the SDRAM 2 are generated by the CAS generation unit 61, the RAS generation unit 62, the CS generation unit 63, and the WE generation unit 64, respectively. These signals are generated in synchronization with the system clock SYSCLK, and the generation of each signal may be controlled by, for example, a sequencer or a control unit (not shown).

The clock generation unit 53 supplies the SDRAM 2 with SDCL based on the system clock SYSCLK.
Generate a K signal. Specifically, normally, the system clock SYSCLK is used as it is as the SDCLK signal in the SDR
AM2. When performing read access to the SDRAM 2, the SDRAM interface 5
After the / CAS signal is generated by the second CAS generation unit 61,
After a predetermined number of clocks, the clock is held, and the system clock SYSCLK is thinned out and output. In this example, whether the access is a read access or a write access is determined based on the output from the WE generation unit 64.

Next, the operation of another embodiment of the memory controller of the present invention will be briefly described. FIG. 8 shows another embodiment of the memory controller of the present invention.
5 is a timing chart when performing a read access to a DRAM 2; Here, an example is shown in which data read from the SDRAM 2 is acquired by another I / O device. The DMA controller 51 activates the DACK signal for the I / O device,
Activates the / IOW signal and passes the address to be read to the SDRAM interface.

In the SDRAM interface 52, CS
The generator 63 activates the / CS signal,
A series of signal sequences at the time of read access to the SDRAM 2 is started. First, after outputting the row address, R
The AS generation unit 62 generates and outputs the / RAS signal for one clock. Then, after outputting the column address, C
The AS generator 61 generates and outputs a / CAS signal. Thus, the SDRAM 2 outputs the data specified by the address to the data bus after a predetermined number of clocks (latency).

On the other hand, at the timing when the SDRAM 2 outputs data, the clock generation unit 53 holds the clock, and the SDCL 2 which thins out the system clock SYSCLK.
The K signal is supplied to the SDRAM 2. I / O devices are
Predetermined data setup time (Tw (R) in FIG. 8)
Is required. Therefore, the clock generator 53 holds and thins out the clock so as to satisfy the predetermined data setup time Tw (R). This gives S
The DRAM 2 keeps outputting the read data as it is.

In the meantime, the DMA controller 51
The / IOW signal is returned to inactive for the device, and the I / O device takes in the data output on the data bus at this timing. Thus, S
The data read from the DRAM 2 is reliably taken into the I / O device.

Thereafter, the clock generation unit 53 stops holding the clock, the CS generation unit 63 of the SDRAM interface 52 makes the / CS signal inactive, and the DMA controller 51 makes the DACK signal inactive, and The read access of the times is ended.

FIG. 9 is a timing chart when a write access is made to SDRAM 2 in another embodiment of the memory controller of the present invention. Here, an example in which data output from the I / O device is written to the SDRAM 2 is shown. DMA controller 5
1 activates the DACK signal to the I / O device, activates the / IOR signal, and passes the address to be written to the SDRAM interface.

In the SDRAM interface 52, CS
The generator 63 activates the / CS signal,
A series of signal sequences at the time of write access to the SDRAM 2 is started. First, after outputting the row address, R
The AS generation unit 62 generates and outputs the / RAS signal for one clock. Then, after outputting the column address, C
The AS generator 61 generates a / CAS signal, and the WE generator 64 generates and outputs a / WE signal. Thus, the SDRAM 2 writes the data on the data bus to the specified address.

However, the I / O device starts outputting data after a predetermined time has elapsed after receiving the / IOR signal, and after the predetermined time Tw (W) has elapsed and the data has stabilized, It is assumed that data will be received. Therefore, in order to reliably write data to the SDRAM 2, it is necessary to observe this timing.
In the example shown in FIG. 9, after a lapse of a predetermined time Tw (W) from the timing at which data is output from the I / O device, the CAS generation unit 61 and the WE generation unit 64 transmit / CA
The S signal and the / WE signal are output. As a result, the data output from the I / O device can be reliably transferred to the SD
It can be written to RAM2.

Thereafter, the CS generator 63 of the SDRAM interface 52 makes the / CS signal inactive, and the DMA controller 51 sends the / IOR signal and the DAC
The K signal is made inactive, and one write access ends.

As described above, the I / O is performed using the DMA.
Also in the case of performing data transfer between the device and the SDRAM, the data read from the SDRAM 2 is surely transferred to the I / D memory.
O device can receive. Also, the data output from the I / O device is surely stored in the SDRAM2.
Can be written to.

FIGS. 8 and 9 show timing charts for only one read access or write access. However, for example, in the case of accessing using the burst mode of SDRAM 2, the same control is surely performed. It is possible to perform a transfer.

[0085]

As is apparent from the above description, according to the present invention, an SDRAM can be controlled by using a control signal for a DRAM from an MPU or the like, and an SDRAM having no access mechanism for the SDRAM is provided. Even a chip microcomputer can use an SDRAM without any problem. Also,
Even in an MPU or an I / O device compatible with the DRAM, there is an effect that the data read from the SDRAM can be reliably obtained and the data can be reliably written to the SDRAM.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a memory controller of the present invention.

FIG. 2 is a circuit diagram showing a specific example of an embodiment of the memory controller of the present invention.

FIG. 3 is a timing chart when a read access is made to the SDRAM 2 in a specific example of the memory controller according to the embodiment of the present invention;

FIG. 4 is a timing chart when a write access is made to the SDRAM 2 in a specific example of the memory controller according to the embodiment of the present invention;

FIG. 5 is an explanatory diagram of a part of functions provided in an example of an SDRAM and signal values of control signals when using the functions.

FIG. 6 is a timing chart showing an example when a refresh operation is performed on the SDRAM 2 in a specific example of the memory controller according to the embodiment of the present invention;

FIG. 7 is a block diagram showing another embodiment of the memory controller of the present invention.

FIG. 8 is a timing chart when a read access is made to the SDRAM 2 in another embodiment of the memory controller of the present invention.

FIG. 9 is a timing chart when performing a write access to the SDRAM 2 in another embodiment of the memory controller of the present invention.

FIG. 10 is a general timing chart when accessing a DRAM.

FIG. 11 is a general timing chart when accessing an SDRAM.

[Explanation of symbols]

1. MPU, 2. SDRAM, 3. Address bus, 4.
Data bus, 5, 6 level shifter, 11 clock generator, 12 CAS generator, 13 RAS generator, 14
... AND circuit, 15 ... OR circuit, 21, 22, 25, 2
6, 28, 29, 34, 35, 36... D flip-flops, 23, 24, 27, 30, 33, 37, 42.
R circuit, 31 ... RS flip-flop, 32, 39,
40 AND circuit, 38 decoder, 41, 43 multiplexer, 44 address controller, 51 DMA controller, 52 SDRAM interface, 53 clock generator, 61 CAS generator, 62 RAS generator, 63 ... CS generator, 64 ... WE generator.

Claims (3)

[Claims] An RAS generating means for converting a RAS signal for a DRAM to an RAS signal for an SDRAM, and a C for converting a CAS signal for a DRAM to a CAS signal for an SDRAM.
A memory controller comprising: an AS generation unit; and a clock generation unit that generates a clock for an SDRAM based on a RAS signal, a CAS signal, and a WE signal for a DRAM. 2. The method according to claim 1, wherein the clock generating means is configured to control the CAS for the DRAM when the WE signal for the DRAM is not active.
After a predetermined number of clocks in response to the activation of the signal,
2. The memory controller according to claim 1, wherein the clock is held and thinned out. 3. A memory controller for accessing an SDRAM, comprising: RAS generating means for generating a RAS signal in synchronization with a clock;
A CAS generating means for generating an S signal; and a CAS generating means for performing a read access to the SDRAM.
After a predetermined number of clocks from the signal generation, the SDRA
A memory controller comprising clock generation means for holding and decimating a clock to M.