JP3317912B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to DQS control at an optimal timing by controlling a DQS input for synchronizing with write data by a counter using the DQS itself. The present invention relates to a semiconductor memory device that generates a signal and enables a higher-speed write operation.

[0002]

2. Description of the Related Art Conventionally, SDRAM (Synchrono) has been used.
us DRAM (dynamic random ac)
cess memory)) Write DQS
In (DQSrobe), a clock for write data input timing is input to the memory. On the other hand, in DQS at the time of Read, a clock for read data output timing is output from the memory. Here, DQS is S
An input signal input from outside the DRAM,
This signal is input to synchronize with e-data.

Accordingly, DQS at the time of reading is Hi-Z
Level (floating state where the level of VCC, GND, etc. is not transmitted to the output terminal).
The DQS after the end of the item is preferably set to the Hi-Z level immediately because the Read may be performed next. Therefore, the shorter the DQS postamble, the better.

[0004]

However, between the time when the last write data (Data 7 and 8) of the burst is fetched and the time when it is sent to the Write Bus,
If the DQS moves carelessly, Data 7 and 8 remaining in the data fetch circuit (DIN fetch circuit) 9 described later with reference to FIG. 4 will be destroyed by fetching data by DQS clocking.

Therefore, even after the end of the Write operation, while the Data 7 and 8 remain in the data fetch circuit 9 (Da
Until ta7 and ta8 are output to the memory by the write internal clock), DQS needs to be fixed at Lo, and the specification of the postamble of DQS is required. Then, there is a problem that this hinders the speeding up of the data writing operation.

As a solution to the above problem, there is a method of controlling a DQS to be enabled only during a burst period by a control signal using a burst counter or the like, as generally performed in an SDRAM circuit. Conceivable.

FIG. 4 is a block diagram showing a configuration example of a conventional SDRAM circuit for controlling DQS by a burst counter. FIGS. 5 and 6 are timing charts showing two types of operations at the time of writing according to the present configuration. 5 and 6 are different in the timing at which the DQS clocks.

As shown in FIG. 4, the SDRAM circuit delays the timing of a burst counter 4 that operates based on the CLK input from the input terminal 31 via the first stage 1 and the output signal of the burst counter 4 to provide a DQS signal. A delay circuit 5 that outputs a control signal and enables or disables the first stage 6, and a rising and falling timing of DQS input from the input terminal 33 via the first stage 6 via the first stage 7 via the input terminal 34. Data capture circuit 9 for capturing external input data (DIN) input by
And the CLK input from the input terminal 31 via the first stage 1
From the input terminal 32 at the rising edge of
Captures and decodes commands entered through
A control signal corresponding to the command is supplied to the internal clock generation circuit 8.
And a command decoder 3 for supplying to the memory interior 10;
And a memory internal 10 for storing data supplied from the data fetch circuit 9 in accordance with a control signal from the command decoder 3.

Here, the first stages 1, 2, 6, 7 are circuits for amplifying and outputting the signal levels of the input signals inputted from the input terminals 31 to 34, respectively, and inputted to the respective input terminals 31 to 34. V according to the signal level of the input signal
It is designed to transmit a CC level or a GND level.

For example, as shown in FIG. 5, when the clocking of DQS is slow (when the interval between CLK and DQS is long), the last clock of DQS is counted after the burst counter 4 counts up. Since there is a time difference before the locking is completed, the burst counter 4 and the D
A delay is required between the QS control signals.

However, as shown in FIG.
Considering the operation when the clocking of the QS is fast (when the period between CLK and DQS is short), the clocking of the DQS has been completed due to the delay between the burst counter 4 and the DQS control signal. Until the DQS control signal disables the internal DQS (the period indicated by “a” in FIG. 6), the external DQS needs to be fixed at Lo.

As described above, since all the control signals in the conventional SDRAM are essentially synchronized with CLK, C
There is a problem that it is not possible to create a control signal for enabling or disabling DQS input asynchronously with LK at an optimum timing.

The present invention has been made in view of such a situation, and the DQ is controlled by a counter using DQS itself.
By controlling the S, the DQS
A control signal can be generated and a higher-speed write operation can be performed.

[0014]

According to a first aspect of the present invention, there is provided a semiconductor memory device which receives a synchronization signal for taking in data and outputs an internal synchronization signal, and a synchronization signal input means for synchronizing with the internal synchronization signal. Capturing means for capturing data, storage means for storing data, and control means for controlling enable or disable of the synchronization signal input means in response to input of a write command instructing writing of the data to the storage means. When a write command is input, the control means enables the synchronization signal input means to output an internal synchronization signal, starts counting the number of clocking times of the internal synchronization signal, and sets the count number to a predetermined value. When the reference number is reached, the synchronization signal input means is disabled. The capturing means can capture data when the synchronization signal input means is enabled, and can stop capturing data when the synchronization signal input means is disabled. Further, the control means can fix the signal level of the internal synchronization signal to a low level when the synchronization signal input means is disabled. Further, the control means, after counting the synchronization signal a predetermined number of times, until the supply of the data fetched by the fetch means to the storage means is completed, the signal level of the synchronization signal is fixed at a low level, Then Hi-Z
Can be level. The count of the number of clocking times of the internal synchronization signal can be reset to an initial state by inputting a write command. The semiconductor memory device according to claim 6, a data input means for inputting data, and fetches the data
Enter the fit of the synchronization signal, writing of a synchronization signal input means for outputting an internal synchronization signal, in synchronization with the internal synchronization signal, and capture means for capturing the data, and storage means for storing data, the data storage means Control means for controlling the enable or disable of the data input means in response to the input of the write command instructing, the control means,
When a write command is input, the data input means is enabled, and counting of the number of clocking of the internal synchronization signal is started. When the count reaches a predetermined reference number, the data input means is disabled, and The acquisition of data by the above is stopped. In the semiconductor memory device according to the present invention, the synchronization signal input means inputs a synchronization signal for capturing data , outputs an internal synchronization signal, and the capture means captures data in synchronization with the internal synchronization signal. The storage means stores data, and the control means controls enable or disable of the synchronization signal input means in response to input of a write command instructing writing of the data to the storage means.
Also, when a write command is input,
The synchronization signal input means is enabled to output the internal synchronization signal, the counting of the number of clocking of the internal synchronization signal is started, and when the count number reaches a predetermined reference number, the synchronization signal input means is disabled. .

[0015]

FIG. 1 shows an SDRAM (Synchronous DR) to which a semiconductor memory device according to the present invention is applied.
AM (dynamic random access)
FIG. 2 is a block diagram illustrating a configuration example limited to a Write operation of a circuit.

The command is a signal imagining a bus, and is composed of input signals such as RAS (row address select signal), CAS (column address select signal), and WE (write control signal). That is, here, the input of a control signal such as Write or Read from the outside through a plurality of input terminals is expressed as if the command is input through one input terminal. I have. In fact, RAS, CAS, W
By performing predetermined input to a plurality of input terminals such as E, control such as Write and Read of the memory is performed.

The command decoder 3 receives the signal C through the first stage 1.
An input terminal 31 for inputting an LK (clock signal) and an input terminal 32 for inputting a command via the first stage 2 are connected to each other. It receives an input command and outputs a control signal to the inside of the memory 10.

The internal clock generating circuit 8 is connected to a command decoder 3, a burst counter (not shown), and a data fetching circuit (DIN fetching circuit) 9 respectively. The internal clock is output to the data acquisition circuit 9 only half the number of times of the burst length (for example, four times when the burst length is 8).
Here, the Write internal clock is a signal for outputting Write data from the data acquisition circuit 9 to the memory inside 10.

The data fetch circuit 9 has an input terminal 33 for inputting DQS (DQ Strobe) through the first stage 6.
And the input terminal 34 for inputting the DIN via the first stage 7, and two write data fetched at the rise and fall of DQS are temporarily held therein. Then, when the internal clock for Write is input from the internal clock generation circuit 8, the two write data held inside is
The data is simultaneously output to the corresponding Write Buses 1 and 2 and written into the memory cell array constituting the memory interior 10.

As described above, a method of simultaneously writing two write data fetched at the rise and fall of DQS into the memory cell array is called a prefetch Wri.
It is called te system.

In the internal clock generating circuit 8, Writ
The timing at which the internal clock for e is generated is determined by two Writes captured at the rise and fall of DQS.
The e data is delayed by the time until it can be simultaneously output to the corresponding Write Buses 1 and 2. The amount of delay must be adjusted so that data output to Write Buses 1 and 2 is performed after data capture performed at the falling edge of DQS is surely completed. Therefore, the timing of data capture is controlled. D
Although it is determined by the specifications of QS, usually, CLK
Using a register that operates synchronously, it is delayed by one or two cycles.

The above is a description of a general DDR-SDRAM (D
available Data Rate system synchronous DR
AM) is a basic configuration example.

In this embodiment, the DQS
DQS control circuit 1 between (external DQS) and internal DQS
2 and the DQS counter 11 are inserted, and the DQS output from the DQS control circuit 12 except during the Write period.
The control signal fixes the internal DQS to Lo level to cut off the input of the external DQS.

That is, the added DQS control circuit 12
Based on inputs from the command decoder 3 and the DQS counter 11, the enable and disable of the internal DQS input from the first stage 6 is controlled via a DQS control signal.

The DQS counter 11 counts the number of clocks of DQS since the Write command is input from the command decoder 3 and counts the count to half the burst length (for example, four in the case of a burst length of 8). When the signal reaches the DQS control circuit 1, a disable signal for causing the DQS control circuit 12 to disable the DQS is output.
2 is supplied.

Next, with reference to FIG. 2, an operation at the time of writing of the embodiment shown in FIG. 1 will be described. FIG.
3 is a timing chart for explaining the operation of the embodiment shown in FIG.

As described above, the commands are RAS, CA
This signal is based on a combination of Hi / Lo of a plurality of signals such as S and WE, and is input with a setup / hold (setup time and hold time) with respect to the rising edge of CLK. At the time of data writing, a Write command is input.

CLK is clocked while maintaining a constant period, and serves as a synchronization signal for commands and addresses.
DQS is in the Hi-Z state except when writing data. However, before the Write command is input, the DQS is set to the Lo level in advance, and after the Write command is input, the CLK is kept at a predetermined time relative to CLK (“b” in FIG. Time of part shown with)
With a delay of, clocking is performed for a half of the burst length (in this case, the burst length is 8 and thus 4 times), and after the end of the burst write, the postamble (the portion indicated by “a” in FIG. 2) period or more is used. After maintaining the Lo level, the level is changed to the Hi-Z level again.

The data fetch circuit 9 stores write data (Data1 to Data8) in the internal memory for the burst length (eight times in FIG. 2 because the burst length is 8) in synchronization with the rise and fall of DQS. Enter and hold.

In the present embodiment, the internal DQS in the normal state is fixed at the Lo level regardless of the state of the external DQS, but is output from the DQS control circuit 12 when a Write command is input. Since the DQS control signal enables the first stage 6, the input of the external DQS causes the internal DQS to operate. That is, the internal DQS synchronized with the external DQS is supplied from the first stage 6 to the DQS counter 11 and the data fetch circuit 9.

The DQS counter 11 has a Write
It is reset to the initial state (the count number = 0) by inputting a command, and thereafter, clocking of DQS is counted. The count number of the DQS counter 11 is half of the burst length (in this example, the burst length is 8
Therefore, when 4) is reached, the internal DQS is fixed at the Lo level via the DQS control circuit 12 so that the DQS
Disable data capture by.

In the meantime, the data fetch circuit 9 synchronizes with the internal clock for Write supplied from the internal clock generation circuit 8 and stores the two Ws held in the internal memory.
Write data is written to corresponding Write Bus 1,2
And supplies the data to the memory array inside the memory 10 through the memory. In this example, Data1, 3, 5, 7 are W
The data is supplied to the internal memory 10 via the write bus 1, and the data buses Data 2, 4, 6, and 8 are
Is supplied to the memory inside 10 via the.

As described above, in the present embodiment, the control of the DQS control circuit 12 is performed by the DQS counter 11 which counts the number of clocks of the DQS itself.
And a DQS control signal can be supplied at an optimal timing to the first stage 6 which is internally inputted. As a result, immediately after receiving the last clocking of DQS, the internal DQS from the first stage 6 can be disabled, and the postamble of DQS (a period during which DQS must be fixed at Lo level after Write is completed) Can be shortened.

That is, Double Data R which outputs data in synchronization with the rise and fall of CLK.
ate type synchronous DRAM (DDR-SDRA)
In M), when data is written, the number of clocks of DQS input to synchronize with the write data is counted, and as soon as the required number of clocking is input, the first stage 6 of DQS is disabled. be able to. As a result, the postamble of DQS can be significantly improved.

FIG. 3 is a block diagram showing a configuration example of another embodiment of the semiconductor memory device of the present invention. In the embodiment shown in FIG. 3, instead of the DQS control circuit 12 in the embodiment shown in FIG.
2, when an enable signal is supplied from the command decoder 3, a DIN control signal is supplied to the first stage 7,
Control is performed so that the write data is captured by the data capturing circuit 9, and when the disable signal is supplied from the DQS counter 11, a DIN control signal is supplied to the first stage 7, and the write data is captured by the data capturing circuit 9. It is controlled not to be.

When the DQS counter 11 controls the first stage 7 of DIN, the output from the first stage 7 of DIN to the data acquisition circuit 9 must be such that the Write data already acquired by the data acquisition circuit 9 is not broken. No. Therefore, three states of “Hi data”, “Lo data”, and “data holding” are put on the output of the DIN from the first stage 7 to the data acquisition circuit 9. Therefore, when the output of DIN from the first stage 7 is floating (data holding), the data fetch circuit 9
Requires a structure for holding Write data already captured in an internal memory.

In the embodiment shown in FIG.
By controlling the first stage 6 of the DQS by the S counter 11, the postamble of the DQS is improved.
In the case of the embodiment shown in FIG.
By controlling the first stage 7 of N, the postamble of DQS can be improved. As described above, also in the embodiment shown in FIG. 3, the same effects as those in the embodiment shown in FIG. 1 can be obtained.

In the above embodiment, the case where the burst length is 8 has been described, but the present invention is not limited to this.

[0039]

As described above, according to the semiconductor memory device of the first aspect, a synchronization signal input means for inputting a synchronization signal for capturing data and outputting an internal synchronization signal, and synchronizing with the internal synchronization signal. Control means for controlling the enabling or disabling of the synchronization signal input means in response to the input of a write command instructing the writing of the data into the storage means; Control means, when a write command is input, enables the synchronization signal input means to output an internal synchronization signal, and starts counting the number of clocking times of the internal synchronization signal. When the predetermined reference number is reached, the synchronization signal input means is disabled, so that the synchronization signal input means is asynchronously input to the clock signal. The signal makes it possible to take in data at an optimum timing, and the period during which the synchronization signal must be fixed at a low level until the data taken in by the taking-in means is supplied to the storage means can be improved. Data writing becomes possible. According to the semiconductor memory device of the sixth aspect, a data input means for inputting data and a synchronous signal for fetching data are provided.
Enter the items, a synchronization signal input means for outputting an internal synchronization signal, in synchronization with the internal synchronization signal, instructs the capturing means to capture data, storage means for storing data, writing to the data storage means Control means for controlling the enable or disable of the data input means in response to the input of the write command, wherein the control means enables the data input means when the write command is input, and controls the internal synchronization signal. The counting of the number of times of locking is started, and when the counted number reaches a predetermined reference number, the data input means is disabled and the data capturing by the capturing means is stopped, so that the data is input asynchronously with the clock signal. The synchronization signal enables data to be captured at the optimal timing, and is captured by the capturing means. Data is able to improve the period for securing the synchronization signal to the low level until it is supplied to the storage means, thereby enabling high-speed data writing.

[Brief description of the drawings]

FIG. 1 shows a DDR-S to which a semiconductor memory device of the present invention is applied.
FIG. 3 is a block diagram illustrating a configuration example limited to a write operation of one embodiment of a DRAM.

FIG. 2 is a timing chart for explaining the operation of the embodiment of FIG. 1;

FIG. 3 shows a DDR-S to which the semiconductor memory device of the present invention is applied.
FIG. 15 is a block diagram showing a configuration example limited to a write operation of another embodiment of a DRAM.

FIG. 4 is a block diagram showing a configuration example of a conventional SDRAM.

FIG. 5 is a timing chart for explaining an operation of the SDRAM shown in FIG. 4;

FIG. 6 is a timing chart for explaining an operation of the SDRAM shown in FIG. 4;

[Explanation of symbols]

 1, 2, 6, 7 First stage 3 Command decoder 4 Burst counter 5 Delay circuit 8 Internal clock generation circuit 9 Data capture circuit (DIN capture circuit) 10 Internal memory 11 DQS counter 12 DQS control circuit 22 DIN control circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/40-11/4099

Claims (6)

(57) [Claims] 1. A inputs a synchronization signal for fetching data, and synchronization signal input means for outputting an internal synchronization signal, in synchronization with the internal synchronization signal, and capture means for capturing the data, storage for storing the data Means, and control means for controlling enable or disable of the synchronization signal input means in response to input of a write command instructing writing of the data to the storage means, wherein the control means comprises: When a write command is input, the synchronizing signal input means is enabled to output the internal synchronizing signal, and starts counting the number of clockings of the internal synchronizing signal, and the count reaches a predetermined reference number. The semiconductor memory device, wherein the synchronization signal input means is disabled. 2. The method according to claim 1, wherein said capturing means enables capturing of said data when said synchronous signal input means is enabled, and stops capturing of said data when said synchronous signal input means is disabled. The semiconductor memory device according to claim 1. 3. The control device according to claim 1, wherein the control unit fixes the signal level of the internal synchronization signal to a low level when the synchronization signal input unit is disabled.
3. The semiconductor memory device according to claim 1. 4. The control means, after counting the synchronization signal a predetermined number of times, until the supply of the data fetched by the fetch means to the storage means is completed, 2. The semiconductor memory device according to claim 1, wherein the signal level is fixed to a low level, and thereafter is set to a Hi-Z level. 5. The semiconductor memory device according to claim 1, wherein a count number of clocking times of said internal synchronization signal is reset to an initial state by inputting said write command. 6. A data input means for inputting data, enter the synchronization signal to capture data, a synchronization signal input means for outputting an internal synchronization signal, in synchronization with the internal synchronization signal, capturing the data Capture means, storage means for storing the data, and control means for controlling enable or disable of the data input means in response to input of a write command instructing writing of the data to the storage means. The control means, when the write command is input, enables the data input means, starts counting the number of clocking times of the internal synchronization signal, and when the count number reaches a predetermined reference number, Disabling the data input means and stopping the data capture by the capture means. That the semiconductor memory device.