JP4967850B2 - Memory interface circuit - Google Patents

Memory interface circuit Download PDF

Info

Publication number
JP4967850B2
JP4967850B2 JP2007167375A JP2007167375A JP4967850B2 JP 4967850 B2 JP4967850 B2 JP 4967850B2 JP 2007167375 A JP2007167375 A JP 2007167375A JP 2007167375 A JP2007167375 A JP 2007167375A JP 4967850 B2 JP4967850 B2 JP 4967850B2
Authority
JP
Japan
Prior art keywords
data
circuit
signal
strobe signal
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007167375A
Other languages
Japanese (ja)
Other versions
JP2009009621A (en
Inventor
幸雄 下村
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP2007167375A priority Critical patent/JP4967850B2/en
Publication of JP2009009621A publication Critical patent/JP2009009621A/en
Application granted granted Critical
Publication of JP4967850B2 publication Critical patent/JP4967850B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Description

  The present invention relates to a memory interface circuit capable of reading data from a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory).

As a memory, a DDR SDRAM having a double data rate (DDR) mode, which is a high-speed data transfer function, is widely used.
In the DDR mode, data can be read and written (read / write) both when the clock signal rises and falls, and input / output can be performed at twice the frequency of the external clock.

Also, DDR2 SDRAM (Double Data Rate 2-Synchronous Dynamic Random Access Memory), which is the latest generation DDR SDRAM technology, is known (for example, see Patent Document 1).
In the DDR2 SDRAM, functions such as reduction of power consumption, increase of data bandwidth, improvement of signal quality, introduction of an on-die termination method, and the like are performed.

  A system using a DDR (DDR2) SDRAM has a memory interface circuit that receives a data strobe signal for informing the timing of data transfer and receives data in accordance with the data strobe signal.

The data strobe signal received by this type of memory interface circuit is a signal that is output from the memory side, and enters the preamble state during a predetermined period that begins after the input of the read command and ends immediately before the output of burst data from the memory begins. In the burst data output period, the signal is in a toggle state that changes every time slot of burst data, and is in a postamble state for a predetermined period immediately after the burst data output period.
The memory interface circuit reads (reads) data of each time slot in the burst data from the memory.
JP 2005-276396 A

  However, in a system using DDR (DDR2) SDRAM, there are the following two problems regarding data transfer (read operation) from SDRAM.

One is that when the memory data is received, the data strobe signal DQS for notifying the timing to transfer the data is a bidirectional bus signal. Therefore, when the read data burst period ends and the state returns to the idle high impedance state, There is a possibility that a glitch occurs for the reason and the received data is destroyed.
When the bus line of the data strobe signal DQS is opened to a high impedance state, a termination voltage of Vtt (0.9 V in DDR2) is reached. This voltage level is the JSTEC SSTL which is the receiver of the data strobe signal DQS of the DDR2 memory system. In the −18 standard, the logic level is indefinite, and a glitch that may be generated in the data strobe signal DQS due to noise may cause a malfunction in the read operation.

  FIG. 1 shows an example of a circuit in which the data signal DQ is captured by a 4-stage FIFO (First-IN First-Out) register when the read data burst length is 4, and the glitch is detected when the burst period ends in the data strobe signal DQS. It is a figure which shows the example which generate | occur | produces.

In the DDR (DDR2) memory system, the read data signal DQ is strobed by a delayed data strobe signal DQSD obtained by delaying the data strobe signal DQS.
The first burst data D0 is strobed at the edge edge0 and stored in the register REG0. Similarly, the second burst data D1 is stored in the register REG1 at the edge edge1, the third burst data D2 is stored in the register REG2 at the edge edge2, and the fourth burst data D3 is stored in the register REG3 at the edge edge3.

If there is no glitch in the data strobe signal DQS, each register data is held for 4 burst data periods, but if there is a glitch, the register data strobed by the signal DQSD obtained by delaying the data strobe signal DQS is There is a possibility of being destroyed.
When there is no glitch, the data holding period is a maximum of four burst data periods. However, when the data is destroyed by the glitch as shown in FIG. 1, the data valid period is shortened.
Particularly affected is the register REG3 for fetching the fourth burst data D3, and the data holding period is one burst data period. This is very short, for example, 1.5 ns in the DDR2-667 speed class.

There are mainly the following two methods for preventing this.
The first is a method of immediately transferring the fetched register data to a clock domain where no glitch is carried.
The second is a method of eliminating the glitch by masking the data strobe signal DQS except for the valid period of the data strobe signal DQS.

  The first method is effective if the effective data period of the received data is less than the operating speed with a margin (for example, DDR-333, the effective data period is 3 ns in one burst period). In the DDR2 generation, the effective data width is greatly reduced in proportion to the clock cycle (in DDR2-667, the effective data period is 1 burst period of 1.5 ns).

Further, the data strobe signal DQS and the read data signal DQ are not constant in delay, and vary depending on voltage, temperature, process variations, and SDRAM devices.
This is called so-called flight time variation. As shown in FIG. 2, the data strobe signal DQS and the read data signal DQ at the time of the read operation are after a CL (CAS latency) cycle set in advance by the SDRAM 1 as a read command reception. Output from the SDRAM.
Here, when viewed from the logic circuit (System Logic) 2 inside the system, the delay from the output of the read command to the reception of the data strobe signal DQS is determined by the DRAM clock CK which is the strobe of the read command in addition to the delay cycle number CL. The I / O driver to output, the data strobe signal DQS, the I / O receiver that receives the read data signal DQ, and the DRAM are affected by delay variations of the delay tDQSCK from the input of CK to the output of DQS (printed circuit board) Wiring variations are relatively small and are ignored here).

Since the variation in tDQSCK is compensated to some extent within the SDDRAM, the flight time variation is dominated by the I / O driver and receiver delay variations.
As shown in FIG. 3, the effective data width further decreases due to the flight time variation, and when it becomes less than or equal to the system clock period, there is no clock edge to be transferred and clock transfer becomes difficult.
Furthermore, when the flight time variation exceeds one burst data width, the effective data width itself disappears.

In order to correct the flight time variation, as shown in FIG. 4, a method of using a feedback clock obtained by mirroring a data transmission path as a transfer clock has been proposed. FIG. 5 is a timing chart of the circuit of FIG.
In FIG. 4, 3 is a DDR2 SDRAM, and 4 is a logic circuit inside the system.

However, with this method, the feedback clock FB An I / O circuit for adding CLK, an external terminal, a printed circuit board wiring pattern, a write PLL, a read PLL, and a variable delay circuit are necessary. As shown in FIG. There is a drawback in that the amount of hardware increases because it is necessary to switch back to the system clock for capturing.

  On the other hand, as disclosed in Patent Document 1, the second method is to create a mask signal and gate the data strobe signal DQS to mask signals other than the valid period of the data strobe signal DQS. Is eliminated (timing diagram of FIG. 6).

In this method, the mask signal is delayed in order to make the mask release point within the run period (preamble period defined by tRPRE) in which the data strobe signal DQS is fixed at a low level until the toggle starts from the high impedance state. There is a need.
However, as the operating frequency increases, as shown in FIG. 7, the DQS delay variation of the data strobe signal due to the flight time variation may exceed the DQS preamble period of the data strobe signal, and the delay setting value of the mask signal is It will not be a fixed value.

For this reason, Japanese Patent Application Laid-Open No. H10-228561 discloses a technique for enabling variable delay of the mask signal, performing expected value determination using a calibration pattern at the time of device initialization, and individually setting the optimum delay amount according to flight time variation. .
However, this technique results in an increase in design amount such as having a calibration mechanism, test time, and initialization time.

On the other hand, the second problem is when the received data is interfaced to the system, and the received data acquired on the basis of the data strobe signal varies in delay due to the above-mentioned flight time variation. Synchronization with the system clock is not easy.
Generally, a FIFO circuit is used to synchronize data transfer to different clock domains. However, an ordinary FIFO circuit has a large overhead of accompanying circuits such as latency and a data read pointer circuit.

  It is an object of the present invention to provide a memory interface circuit that eliminates glitches generated in a data strobe signal and enables accurate data reception while suppressing an increase in the amount of hardware without requiring a special calibration operation. .

  A first aspect of the present invention is a memory interface circuit that receives a data strobe signal for notifying the timing of data transfer, and receives data in accordance with the data strobe signal. The memory interface circuit receives the data strobe signal. An input buffer for input; a mask control signal generator for generating a mask control signal in synchronization with a system clock; and a first delay circuit for delaying the data strobe signal input by the input buffer and outputting the delayed data strobe signal A replica circuit having delay characteristics equivalent to those of the input buffer and the CK output buffer and outputting the mask control signal by delaying the mask control signal by a delay amount corresponding to the input delay characteristics, and mask control output from the replica circuit The signal was delay controlled following the delay of the data strobe signal. A mask signal is generated with reference to a second delay circuit that outputs as an extended mask control signal and a mask control signal that is delay-controlled by the second delay circuit, and the delayed data strobe signal is generated according to the mask signal. A mask circuit that generates a data strobe signal that is masked for a predetermined period to remove glitches, and captures the data signal in accordance with the data strobe signal from the mask circuit, and resynchronizes and outputs the captured data by a clock synchronized with the system clock. Resynchronizing circuit.

  Preferably, the first delay circuit is a delayed data strobe in which the data strobe signal received by the input buffer is positioned at the center of the effective data width of the data signal and the delay is controlled by adding a data reception timing margin. Output a signal.

  Preferably, the mask control signal generation unit generates a mask control signal so that the mask of the data strobe signal can be released at the center timing of the preamble period of the ideal data strobe signal without delay from the read instruction signal. .

  Preferably, the mask control signal is a signal which becomes a first level at the edge of the system clock in the preamble period and becomes a second level at the edge of the next system clock.

  Preferably, the second delay circuit controls the delay so that the delay mask control signal is positioned at a timing at which the mask is released at the center of the preamble period of the delayed data strobe signal.

  Preferably, the mask circuit generates the mask signal inactive only for a predetermined period when the delay mask control signal is active and is input, and outputs the delayed data strobe signal when the mask signal is inactive. To do.

  Preferably, the resynchronization circuit generates a write strobe signal from a plurality of FIFO registers for writing a data signal in response to a write strobe signal and a data strobe signal from the mask circuit, and supplies the write strobe signal to the FIFO register. A generation circuit, a resynchronization strobe control circuit that generates a clock to be switched to synchronize the latch data of the FIFO register with the system clock from the system clock, and resynchronization of the latch data of the FIFO register in synchronization with the transfer clock. A resynchronization register to output.

According to the present invention, the data signal and the data strobe signal are received and input in the memory interface circuit.
The data strobe signal is input via the input buffer, delayed by the first delay circuit, and output as a delayed data strobe signal to the mask circuit.
Further, in the mask control signal generator, for example, a mask control signal is generated in synchronization with the system clock in response to a read instruction signal.
This mask control signal is output to the second delay circuit after being delayed by a delay amount corresponding to the input / output delay characteristic by a replica circuit having a delay characteristic equivalent to the input buffer for the data strobe signal and the CK output buffer 109. The
In the second delay circuit, the mask control signal output from the replica circuit is output as a delay mask control signal subjected to delay control following the delay of the data strobe signal.
In the mask circuit, a mask signal is generated using the mask control signal delayed by the second delay circuit as a reference timing, and the data strobe signal from which the delayed data strobe signal is masked for a predetermined period according to the mask signal to remove glitches Is generated and output to the resynchronization circuit.
In the resynchronization circuit, a data signal is captured according to the data strobe signal from the mask circuit, and the captured data is resynchronized and output by a clock synchronized with the system clock.

  According to the present invention, a special calibration operation is unnecessary, and an accurate data reception can be performed by removing a glitch generated in the data strobe signal while suppressing an increase in the amount of hardware.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 8 is a block diagram showing a configuration example of the read system of the memory interface circuit according to the embodiment of the present invention.

As shown in FIG. 8, the memory interface circuit 100 includes input / output (I / O) receivers (input buffers) 101 and 102, an I / O replica circuit 103, a variable delay circuit 104 as a first delay circuit, a second delay circuit 104, and a second delay circuit 104. The delay circuit 105 includes a variable delay circuit 105, a data strobe signal (DQS) mask circuit 106, a mask control signal generation circuit 107, a read data resynchronization circuit 108, a clock transmission I / O buffer 109, and a clock generation circuit 110.
In addition, the memory interface circuit 100 according to the present embodiment is configured as a circuit that receives the read data signal DQ of the DDR2 SDRAM 200 in accordance with the data strobe signal DQS, resynchronizes it, and outputs it.

The I / O receiver 101 is a receiver that receives a read (read) data signal DQ from the DDR2-SDRAM 200.
The I / O receiver 102 is a receiver that receives the data strobe signal DQS output from the DDR2-SDRAM 200.
The I / O receivers 101 and 102 are bi-directional buffers, but in the present embodiment, the I / O receivers 101 and 102 are shown as input buffers because they are on the input side.

The I / O replica circuit 103 is formed to have a delay characteristic similar to that of the I / O receiver (I / O buffer), delays the mask control signal REN generated by the mask control signal generation circuit 107, and generates a signal RENFB. To the variable delay circuit 105.
The I / O replica circuit 103 in FIG. 8 has buffers 1031 and 1032 as delay elements at the input and output portions of the mask control signal REN, and includes the buffers 1031 and 1032 and the wiring delay. The delay characteristics are similar to those of the I / O buffer.

  The variable delay circuit 104 positions the data strobe signal DQS received by the I / O receiver 102 at the center of the effective data width of the data signal DQ, and receives the signal DQSD that has been optimally delay-controlled to maximize the data reception timing margin. Output.

  The variable delay circuit 105 outputs, to the DQS mask circuit 106, a delay mask control signal REND (active at a high level in this embodiment) that is optimally delay-controlled with respect to the data strobe signal DQS in accordance with the delay of the data strobe signal DQS. To do.

The mask control signal RENFB input to the variable delay circuit 105 includes an I / O replica circuit 103 for replicating (simulating) the mask control signal REN generated from the mask control signal generation circuit 7 as an I / O buffer and an I / O receiver. It is output via.
These are the same circuits (equivalent circuits) as the transmission I / O buffer 109 for the DRAM clock CK and the I / O receiver 101 for receiving the data signal DQ or the I / O receiver 102 for receiving the data strobe DQS. The delay variation of the I / O circuit due to the process variation is mirrored.

  The DQS mask circuit 106 generates (creates) a mask signal DQSG using the mask control signal REND adjusted by the variable delay circuit 105 as a reference timing, and masks the delayed data strobe signal DQSD to remove a glitch. DQSM is generated and output to the read data resynchronization circuit 108.

The read data resynchronization circuit 108 includes a FIFO write (Write) strobe generation circuit 1081, a resynchronization strobe control circuit 1082, a FIFO register 1083, and a resynchronization register 1084.
The data strobe signal DQSM from which glitches have been removed in the DQS mask circuit 106 is input to the read data resynchronization circuit 108.
In the read data resynchronization circuit 108, the FIFO write strobe generation circuit 1081 generates a FIFO write (WRITE) strobe signal and distributes it to the FIFO register 1083 as strobe signals DQS0 and DQS1.
As a reset signal, the mask signal DQSG is initialized and disabled when DQSG = L except when the read operation is performed, and the FIFO WRITE strobe signal is initialized.

In this embodiment, the FIFO is composed of four stages.
The output of the FIFO register 1083 is expanded to a data period width that is four times the burst data width (the transfer rate is naturally ¼), and after being output as 4-bit data DREG10, DREG11, DREG12, DREG13, Synchronized to the system clock CLK domain by the synchronization register 1084, output as RDATA [3: 0], and passed to the system.
The resynchronization strobe control circuit 1082 selects an optimum strobe point edge that maximizes the timing margin within the data width expanded by the FIFO register 1083. This edge selection is performed by a 2-bit (bit) edge control (selection) signal SEL_EDGE.

  FIG. 9 is a diagram showing a detailed circuit configuration of the DQS mask circuit 106 according to the present embodiment. FIG. 10 is a diagram showing a timing chart (ideal delay) of the circuit of FIG.

  The DQS mask circuit 106 includes an AND circuit 1061 and a mask signal generation circuit 1062, and the AND circuit 1061 has a function of masking the delayed data strobe signal DQSD.

The mask control signal generation circuit 107 generates a mask control signal REN for releasing the masking of the data strobe signal DQS from the read instruction signal READ_EN signal at the center timing of the ideal (no delay) data strobe signal DQS.
In the present embodiment, as shown in FIG. 10, the mask control signal REN becomes high (first level) at the falling edge of the system clock CLK in the preamble period, and the next system clock CLK rises. This signal becomes a low (LOW) level (second level) at the falling edge.
Of course, this is a case where the burst length is 4, and even a burst length of 8 or more can be easily handled.

Thereafter, the mask control signal REN is input to the I / O replica circuit 103, and a signal RENFB with an I / O delay added is output.
Further, the signal RENFB is input to the mask signal generation circuit 1062 of the DQS mask circuit 106 by the variable delay circuit 105 and the delay mask control signal REND in which the delay control of the data strobe signal DQS and the alignment of the wiring skew are matched.
The delay mask control signal REND is also positioned at the mask release timing at the center of the preamble of the delayed data strobe signal DQSD.

As shown in FIG. 9, the mask signal generation circuit 1062 includes two D-FFs (D flip-flops) 10621 and 10622, an OR circuit 10623, and an inverter 10624. The D-FFs 10621 and 10622 are reset at the initial stage. Since the mask signal DQSG is maintained at a low (LOW) level (active level) and the delayed data strobe signal DQSD is masked, the data strobe signal DQSM is also at a low level.
When the delay mask control signal REND by the variable delay circuit 105 becomes high level, the mask signal DQSG becomes high level (inactive level) by the OR circuit 10623 and one input of the AND circuit 1061 becomes high level. The data strobe signal DQSM is unmasked and output of the strobe signal is started.
In parallel with this, the two D-FFs 10621 and 10622 are also set to the asynchronous preset terminal S high level connected to the supply line of the delay mask control signal REND, so that the output Q0 of the D-FFs 10621 and 10622 which are register outputs. , Q1 also goes high.

  The D-FF 10621 changes its output at the rising edge of the data strobe signal DQSM, but the delay mask control signal REND as the preset signal is still at the high level at the first rising edge of the data strobe signal DQSM, so the output Q0 is also at the high level. To maintain.

Next, since the delay mask control signal REND is already at the low level at the second rising edge of the data strobe signal DQSM, the preset operation is canceled, and the D input of the D-FF 10621 is fixed at the low level. The output Q0 transitions to a low level.
Then, at the second falling edge of the data strobe signal DQSM, since the D input of the D-FF 10622 is inputted with the low level output Q0 of the D-FF 10621, the output Q1 also becomes low level through the OR circuit 10623. Since the mask signal DQSG becomes low level and the OR circuit 10623 masks the received data strobe signal and the data strobe signal DQSM also becomes low level, the data strobe signal DQSM from which the glitch has been deleted can be obtained.
Since this masking operation is continued until the read instruction signal READ_EN is input again, noise outside the read data period can be eliminated.

  FIG. 11 shows the mask timing of the DQS mask circuit when the delay of the data strobe signal DQS changes due to the flight time variation.

Although the delay of the data strobe signal DQS input from the DRAM (not shown) changes due to the flight time variation, the I / O replica circuit 103 generates a signal corresponding to the variation in I / O delay even if the timing of the mask control signal REN is fixed. RENFB is delayed and output.
For this reason, since the DQS mask signal DQSG generated based on this also follows the flight time variation of the data strobe signal DQS, the mask is always released at the timing near the center of the preamble period of the data strobe signal DQS, and a reliable mask operation is performed. It can be guaranteed.

  FIG. 12 is a diagram showing a detailed circuit configuration of the read data resynchronization circuit 108 according to the present embodiment. FIG. 13 is a diagram showing a timing chart (ideal timing) of the circuit of FIG.

  The FIFO write (Write) strobe generation circuit 1081 includes a register REG_WPT, latches LTC0 and LTC1, AND circuits 10811 and 10812, and an inverter 10813. The write strobe signal from the glitch-removed data strobe signal DQSM to the FIFO register 1083 DQS0 and DQS1 are generated.

The register REG_WPT creates the strobe control signals WPT0 and WPT1 so that the output is inverted at every rising edge of the data strobe signal DQSM from which the glitch has been removed, and the FIFO strobe signal operates alternately.
The latches LTC0 and LTC1 synchronize the strobe control signals WPT0 and WPT1 with the data strobe signal DQSM to prevent glitch generation in the AND circuits 10811 and 10812.

  The mask signal DQSG is input to the reset terminal of the register REG_WPT, and is initialized to a low level (WPT0 is high level and WPT1 is low level) outside the read operation, and the first burst data D0 is sequentially stored in the register REGE00 of the FIFO register 1083. It is captured.

  The glitch-removed strobe signal DQSM is output to the strobe signal DQS0 to the registers REG00 and REG01 of the FIFO register 1083 by the two AND circuits 10811 and 10812, and to the registers REG02, REG10, REG11, REG12, and REG13 of the FIFO register 1083. Distributed to signal DQS1.

The burst data D0, D1, D2, and D3 of the received data signal DQ are sequentially latched in the first stage registers REG00, REG01, and REG02 of the FIFO register 1083, respectively, and at the timing when the data D3 is latched in the register REG13. The values of the registers REG00, REG01, and REG02 are latched in the second stage registers REG10, REG11, and REG12, respectively.
Accordingly, the burst data D0, D1, D2, and D3 are parallelized into 4-bit data that is four times the data width (transfer rate is 1/4) and aligned at the same timing.
For example, in the case of DDR2-667, the burst data length of 1.5 ns becomes the FIFO data length of 6 ns.

The resynchronization strobe control circuit 1082 includes D-FFs 10821 and 10822, exclusive OR circuits 10823 and 10824, an AND circuit 10825, and an inverter 10826, and a clock CLK that is switched to synchronize the FIFO data with the system clock. RESSYNC is generated from the system clock CLK and supplied to the resynchronization register 1084.
Since the FIFO data ideally has a data width twice that of the system clock CLK, if both rising and falling edges of the system clock CLK are used, four strobe points edge0, 1, 2, 3 can be selected.
Here, the transfer edge is selected by setting the 2-bit control signal SEL_EDGE [1: 0]. At the timing illustrated in FIG. 13, edge 0 with SEL_EDGE [1: 0] = 00 having the maximum timing margin is selected.

  The operation at the ideal timing has been described above. Here, the case where there is a variation in the flight time will be considered below.

Since the FIFO output data is received based on a data strobe signal DQS from a DRAM (not shown), the FIFO output data has a delay variation as shown in FIG. 14, and resynchronization strobe that can strobe both FIFO data as shown in FIG. The edge is within the effective data width where both FIFO data overlap.
In the example of FIG. 14, the edge is edge2 and the setting is SEL_EDGE [1: 0] = 01.

As described above, even if the flight time variation is taken into consideration, the FIFO data fetched with DRAM data can be easily resynchronized with the system clock CLK.
The output RDATA [3: 0] of the resynchronization register 1084 is easily interfaced to the system because it is synchronized with the system clock CLK.

  As described above, according to the present embodiment, the input receiver (buffer) 102 that receives and inputs the data strobe signal, the mask control signal generation circuit 107 that generates the mask control signal in synchronization with the system clock, and the input The first delay circuit 104 that delays the data strobe signal input by the buffer and outputs it as a delayed data strobe signal, and has a delay characteristic equivalent to that of the input buffer. The mask control signal is output with a delay amount corresponding to the input delay characteristic. An I / O replica circuit 103 that outputs after delay, and a second delay circuit 105 that outputs a mask control signal output from the replica circuit as a delay mask control signal that is delay-controlled following the delay of the data strobe signal; The mask control signal that is delay-controlled by the second delay circuit 105 is used as a reference timing. A mask circuit 106 for generating a skew signal, masking the delayed data strobe signal for a predetermined period according to the mask signal, and generating a data strobe signal from which glitch is removed, and capturing the data signal according to the data strobe signal by the mask circuit, Since it has the resynchronization circuit 108 that resynchronizes and outputs the captured data by a clock synchronized with the system clock, the following effects can be obtained.

First, accurate data reception is possible by eliminating glitches generated in the strobe signal during the read operation.
Secondly, in the mask signal generation timing control for glitch elimination by the I / O replica circuit, the calibration operation by the test pattern transmission / reception or the like becomes unnecessary, so that the design amount and the test time can be reduced.
Third, the data resynchronization circuit enables reliable synchronization of received data with the system clock, and facilitates data interface with the system.

It is a figure which shows the example which a glitch generate | occur | produces when the burst period is complete | finished in the data strobe signal DQS by taking as an example the circuit which takes in the data signal DQ with a four-stage FIFO register when the read data burst length is 4. It is a figure for demonstrating flight time variation. It is a figure for demonstrating the reduction | decrease of the effective data width by flight time dispersion | variation. It is a figure which shows the example of a circuit which employ | adopted the method of using the feedback clock which mirrored the data transmission path path | route as a transfer clock in order to correct | amend flight time variation. 5 is a timing chart of the circuit of FIG. It is a figure for demonstrating the method of removing a glitch by masking signals other than the effective period of a data strobe signal. It is a figure which shows the case where the delay variation of the data strobe signal by flight time variation may exceed a preamble period. It is a block diagram which shows the structural example of the memory interface circuit which concerns on embodiment of this invention. It is a figure which shows the detailed circuit structure of the DQS mask circuit which concerns on this embodiment. It is a figure which shows the timing chart (ideal delay) of the DQS mask circuit which concerns on this embodiment. It is a figure which shows the mask timing of a DQS mask circuit when the delay of a data strobe signal changes with flight time dispersion | variation. It is a figure which shows the detailed circuit structure of the read data resynchronization circuit which concerns on this embodiment. It is a figure which shows the timing chart (ideal timing) of the read data resynchronization circuit which concerns on this embodiment. It is a figure which shows the timing chart in case there exists a flight time variation of the read data resynchronization circuit which concerns on this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Memory interface circuit, 101 ... Data input / output (I / O) receiver (buffer), 102 ... I / O receiver (buffer) of data strobe signal, 103 ... I / O replica circuit 104, 105 ... variable delay circuit, 106 ... data strobe signal (DQS) mask circuit, 1061 ... AND circuit, 1062 ... mask signal generation circuit, 107 ... mask control signal generation circuit , 108 ... Read data resynchronization circuit, 1081 ... FIFO write strobe generation circuit, 1082 ... Resynchronization strobe control circuit, 103 ... FIFO register, 1084 ... Resynchronization register, 109 ... Clock transmission I / O buffer.

Claims (8)

  1. A memory interface circuit for receiving a data strobe signal for notifying the timing of data transfer and receiving data in accordance with the data strobe signal;
    An input buffer for receiving and inputting the data strobe signal;
    A mask control signal generator for generating a mask control signal in synchronization with the system clock;
    A first delay circuit that delays the data strobe signal input by the input buffer and outputs the delayed data strobe signal;
    A replica circuit having a delay characteristic equivalent to the input buffer, and delaying and outputting the mask control signal by a delay amount according to the input delay characteristic;
    A second delay circuit that outputs a mask control signal output from the replica circuit as a delay mask control signal that is delay-controlled following the delay of the data strobe signal;
    A mask signal is generated using the mask control signal delayed by the second delay circuit as a reference timing, and the delayed data strobe signal is masked for a predetermined period according to the mask signal to generate a data strobe signal from which glitch is removed A mask circuit to perform,
    A memory interface circuit comprising: a resynchronization circuit that captures a data signal in accordance with a data strobe signal from the mask circuit and resynchronizes and outputs the captured data by a clock synchronized with the system clock.
  2. The first delay circuit includes:
    2. The memory interface circuit according to claim 1, wherein the data strobe signal received by the input buffer is positioned at a central portion of the effective data width of the data signal, and a delay data strobe signal that is delay-controlled by adding a data reception timing margin is output. .
  3. The mask control signal generator is
    The memory interface circuit according to claim 1, wherein a mask control signal is generated from the read instruction signal so that the masking of the data strobe signal can be released at a central timing of a preamble period of an ideal data strobe signal without delay.
  4. 4. The memory interface circuit according to claim 3, wherein the mask control signal is a signal that becomes a first level at an edge of a system clock in a preamble period and becomes a second level at an edge of the next system clock.
  5. The second delay circuit includes:
    4. The memory interface circuit according to claim 3, wherein the delay mask control signal is delay-controlled so as to be positioned at a timing at which the mask is released at a center of a preamble period of the delayed data strobe signal.
  6. The mask circuit is
    6. The memory interface circuit according to claim 5, wherein when the delay mask control signal is active and input, the mask signal is generated inactive only for a predetermined period, and the delayed data strobe signal is output when the mask signal is inactive. .
  7. The resynchronization circuit
    A plurality of FIFO registers for writing data signals in response to a write strobe signal;
    A write strobe generation circuit for generating the write strobe signal from the data strobe signal by the mask circuit and supplying the write strobe signal to the FIFO register;
    A resynchronization strobe control circuit that generates from the system clock a clock to be switched to synchronize the latch data of the FIFO register with the system clock;
    The memory interface circuit according to claim 3, further comprising: a resynchronization register that resynchronizes and outputs the latch data of the FIFO register in synchronization with the transfer clock.
  8. The resynchronization circuit
    A plurality of FIFO registers for writing data signals in response to a write strobe signal;
    A write strobe generation circuit for generating the write strobe signal from the data strobe signal by the mask circuit and supplying the write strobe signal to the FIFO register;
    A resynchronization strobe control circuit that generates from the system clock a clock to be switched to synchronize the latch data of the FIFO register with the system clock;
    The memory interface circuit according to claim 6, further comprising: a resynchronization register that resynchronizes and outputs the latch data of the FIFO register in synchronization with the transfer clock.
JP2007167375A 2007-06-26 2007-06-26 Memory interface circuit Expired - Fee Related JP4967850B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007167375A JP4967850B2 (en) 2007-06-26 2007-06-26 Memory interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007167375A JP4967850B2 (en) 2007-06-26 2007-06-26 Memory interface circuit

Publications (2)

Publication Number Publication Date
JP2009009621A JP2009009621A (en) 2009-01-15
JP4967850B2 true JP4967850B2 (en) 2012-07-04

Family

ID=40324556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007167375A Expired - Fee Related JP4967850B2 (en) 2007-06-26 2007-06-26 Memory interface circuit

Country Status (1)

Country Link
JP (1) JP4967850B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5450112B2 (en) * 2010-01-08 2014-03-26 株式会社メガチップス Memory interface circuit
US20110299346A1 (en) 2010-06-03 2011-12-08 Ryan Fung Apparatus for source-synchronous information transfer and associated methods
EP2721500B1 (en) * 2011-06-14 2015-08-12 Marvell World Trade Ltd. System and method for dqs gating

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08221315A (en) * 1995-02-15 1996-08-30 Hitachi Ltd Information processor
JP3317912B2 (en) * 1999-01-28 2002-08-26 エヌイーシーマイクロシステム株式会社 Semiconductor storage device
JP2003059267A (en) * 2001-08-08 2003-02-28 Mitsubishi Electric Corp Semiconductor memory device
JP4450586B2 (en) * 2003-09-03 2010-04-14 株式会社ルネサステクノロジ Semiconductor integrated circuit
JP4284527B2 (en) * 2004-03-26 2009-06-24 日本電気株式会社 Memory interface control circuit
JP2006085650A (en) * 2004-09-17 2006-03-30 Fujitsu Ltd Information processing circuit and information processing method
JP4747621B2 (en) * 2005-03-18 2011-08-17 日本電気株式会社 Memory interface control circuit
JP4936421B2 (en) * 2005-09-14 2012-05-23 エルピーダメモリ株式会社 DRAM, input control circuit, and input control method
JP5052056B2 (en) * 2005-09-29 2012-10-17 エスケーハイニックス株式会社SK hynix Inc. Data input device for semiconductor memory device

Also Published As

Publication number Publication date
JP2009009621A (en) 2009-01-15

Similar Documents

Publication Publication Date Title
JP5855726B2 (en) Clock transfer low power signaling system
US9306584B2 (en) Multi-function delay locked loop
US8441888B2 (en) Write command and write data timing circuit and methods for timing the same
US9001594B2 (en) Apparatuses and methods for adjusting a path delay of a command path
US7983094B1 (en) PVT compensated auto-calibration scheme for DDR3
EP2223227B1 (en) Low-power source-synchronous signaling
US6100733A (en) Clock latency compensation circuit for DDR timing
US8301932B2 (en) Synchronising between clock domains
JP5013768B2 (en) Interface circuit
KR100813424B1 (en) Delay line synchronizer apparatus and method
KR100470995B1 (en) multi clock domain data input processing device having clock receiving locked loop and method for providing clock signals therefore
TW550587B (en) Memory system having stub bus configuration
US6209072B1 (en) Source synchronous interface between master and slave using a deskew latch
US8209562B2 (en) Double data rate converter circuit includes a delay locked loop for providing the plurality of clock phase signals
US7079446B2 (en) DRAM interface circuits having enhanced skew, slew rate and impedance control
JP4444277B2 (en) Method and apparatus for establishing and maintaining a desired read latency in a high speed DRAM
US7421606B2 (en) DLL phase detection using advanced phase equalization
KR100541131B1 (en) Memory system and control method for the same
JP4700636B2 (en) System having a memory module equipped with a semiconductor memory device
US6791381B2 (en) Method and apparatus for reducing the lock time of a DLL
EP1040404B1 (en) Method and apparatus for coupling signals between two circuits operating in different clock domains
US7198197B2 (en) Method and apparatus for data acquisition
DE10084993B3 (en) Dual Data Rate Dynamic Random Access Memory Output Circuit (DDR DRAM), Double Data Rate Dynamic Random Access Memory (DDR DRAM), A Method of Clocked Reading Data from Dual Data Rate Dynamic Random Access Memory ( DDR DRAM)
US7706210B2 (en) Semiconductor memory device including delay locked loop and method for driving the same
US6920080B2 (en) Methods for generating output control signals in synchronous semiconductor memory devices and related semiconductor memory devices

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100427

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120302

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120306

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120319

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150413

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150413

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees