JPS63114000A - Control system for dynamic random access memory - Google Patents

Abstract

PURPOSE:To improve the executing speed of a memory access by delaying a refreshing operation to a refreshing unit refreshed by a reading/writing and decreasing the number of times of the refreshing operation. CONSTITUTION:When a refreshing request generating circuit 3 is activated and the circuit 3, when the refreshing request is absent to the refreshing unit, stores the data that the refreshing request to the unit is present, to a static RAM5. On the other hand, when the request is present, the circuit 3 requests the refreshing to a refreshing control circuit 6. The circuit 6 obtains a refreshing permission to an arbitrating circuit 8 when the request is executed. The circuit 8 gives the permission of the refreshing operation. The circuit 6 drives a memory control circuit 9 and executes a refreshing operation. According to the above-mentioned control system, the information is not lost. Further, the number of times of a refreshing operation per unit time can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a control method for a dynamic random access memory, and particularly to a refresh control method thereof.

(Conventional technique 1 (i) Dynamic random access, memory (hereinafter referred to as D
The RAM (hereinafter referred to as RAM) stores information as a capacitive charge under the gate electrode of a MOSFET. This charge is gradually lost due to leakage current. Therefore, the stored information is lost over time. In order not to lose stored information, it is necessary to regenerate this charge before it is lost. Generally, this charge regeneration operation, that is, information regeneration operation, is called DRAM refresh.

In a typical DRAM, only a portion of the information is reproduced in one refresh operation. The unit that is reproduced by one refresh operation is called a refresh unit.0 Normal DRAM consists of several hundred refresh units, so it takes several hundred refreshes to reproduce all the information. I need.

Furthermore, for one refresh unit, 1
Refreshing once is not enough, but the interval specified by the DRAM specifications (hereinafter referred to as the maximum refresh interval)
If the information is not refreshed repeatedly at a shorter period, the information will be lost because the charge storing the information will never stop discharging.

For this reason, in a typical DRAM system, refresh operations are repeatedly performed several hundred times at a cycle shorter than the maximum refresh interval.

(Problem to be solved by the invention) By the way, the time required for one refresh operation is D
This is about the same time as one normal access to RAM. During refresh, normal access cannot be performed.

In other words, the memory access execution speed of the DRAM system is suppressed by the refresh operation. An object of the present invention is to provide a DRAM control method that improves memory access execution speed by reducing the number of refresh operations.

(Means for Solving the Problems) The means provided by the present invention in order to solve the problems mentioned above and to combine the above objects is to reduce the number of refresh units refreshed by one refresh operation to one. A DRAM control method having the above, in which a refresh unit identifier is defined to uniquely identify each refresh unit, and data representing the presence or absence of a refresh request for each refresh unit is stored for each refresh unit. refresh request storage means; refresh request setting means for causing the refresh request storage means to store given data representing the presence or absence of a refresh request for the refresh unit represented by the given refresh unit identifier; refresh request retrieval means for retrieving data representing the presence or absence of a refresh request for the refresh request storage unit from the refresh request storage means; generating refresh check requests for refresh units that occur in the order in which they occurred and are represented by each refresh unit identifier that occurs, and that is sufficiently shorter than half the maximum refresh interval;
and a refresh check requesting means that performs the refresh check with a repetition period sufficiently longer than one-third, and a refresh request retrieving means that retrieves data indicating the presence or absence of a refresh request for the refresh unit represented by the given refresh unit identifier. It is retrieved from the storage means, checks whether there is a refresh request, and if there is no refresh request, the refresh request setting means stores data indicating that there is a refresh request for the refresh unit in the refresh request storage means, and when there is a refresh request, has a refresh request generating means that generates a refresh request along with an identifier of the refresh unit; and a refresh request generator that immediately permits refresh if memory access is not in progress when a refresh request is received, and terminates memory access if memory access is in progress. Wait and allow refresh, and refresh at the same time when there is a memory access request! , an arbitration means for arbitrating to avoid conflict between refresh and memory access by immediately permitting memory access if there is no request, and permitting memory access after waiting for completion of refresh if refresh is in progress; With the permission of the means, the refresh request storage means refreshes the refresh unit represented by the identifier given by the generated refresh request, and the refresh request setting means refreshes data indicating that there is no refresh request for the refresh unit. Refresh system p stored in the request storage means
p means and when access to memory occurs from outside,
Execute the memory access with permission from the arbitration means, and provide the refresh request setting means with an identifier of the refresh unit including the accessed address and data indicating that there is no refresh request, so that there is no refresh request for the refresh unit. and memory access control means for storing the information in the refresh request storage means.

(Operation) In the DRAM refresh operation, a refresh unit to be refreshed is specified and that refresh unit is refreshed. The refresh level identifier of the refresh unit to be refreshed is 7 to 10 of the address signals (f! several) used during normal reading and writing.
(hereinafter referred to as a refresh unit identification signal) is used to provide the data to the DRAM. The refresh unit identification signal differs depending on the type of DRAM.

-DRAM in M is used not only during refresh operation, but also when
Refreshing is performed at the same time when reading and writing. What is refreshed at this time is not only the information at the read or write address, but also all the information within one refresh unit that includes that address.

The refresh unit that is refreshed at this time is an address signal that is shared for the refresh unit identification signal that specifies the refresh unit during a refresh operation among the address signals used to specify the address to be read or written. specified by.

The DRAM control method according to the present invention, instead of the conventional method of periodically performing refreshes independently of read and write operations, delays refresh operations for refresh units refreshed by read and write operations as much as possible. , which reduces the number of refresh operations.

That is, when the memory access control means of the DRAM control system according to the present invention performs a read/write operation in response to an external request, the identifier of the refresh unit (including the accessed address) that was refreshed at that time and the refresh request. Data indicating that there is no refresh request is given to the refresh request setting means to cause the refresh request storage means to store that there is no refresh request for the refresh unit. Further, at the same time as the refresh operation is performed, the refresh control means causes the refresh request setting means to store data indicating that there is no refresh request for the refresh unit in the refresh request storage means.

For simplicity, the explanation will focus on one refresh unit. The refresh check request means generates a refresh check request with this refresh unit identifier at a repetition period that is sufficiently longer than half of the maximum refresh interval and sufficiently longer than one third.

When the refresh request generation means receives a refresh check request together with this refresh unit identifier,
Data representing the presence or absence of a refresh request for the refresh unit represented by this refresh unit identifier is retrieved from the refresh request storage means by the refresh request retrieval means, and the presence or absence of a refresh request is checked. If there is no refresh request, the refresh request setting means stores data indicating that there is a refresh request for this refresh unit in the refresh request storage means, and if there is a refresh request, a refresh request is generated together with the identifier of this refresh unit. do. When a refresh request is generated, the refresh control means, with permission from the arbitration means, refreshes the refresh unit indicated by the refresh unit identifier and causes the refresh request storage means to store that there is no refresh request for this refresh unit.

For one refresh unit, such an operation is repeatedly performed at a repetition period that is sufficiently shorter than half of the maximum refresh interval and sufficiently longer than one-third of the maximum refresh interval. Furthermore, during the - period, the above operations are performed for all refresh units in a predetermined order.

Further, the arbitration means permits memory access and refresh so that refresh by the refresh control means and memory access by the memory access means do not conflict. The memory access control means waits for permission from the arbitration means and performs the aforementioned operations on the memory access and refresh request storage means.

The DRAM control method according to the present invention operates as described above to reduce the number of refresh operations.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The DRAM III control method shown in Fig. 1 is for controlling 32 DRAMs of 256 bits to configure a memory system of 32 bits per word and 256 words in total. Contains.

There are a total of 256 refresh units in this 256-bit DRAM, and their identifiers are composed of 8 bits.

The clock signal CL supplied from the outside has a frequency f=
10MHz, that is, the period T=100nS.
Drive memory system in diagram. This memory system can read and write in units of one word. In other words, when writing the address for reading and writing to the address signal ○ at predetermined time intervals after setting the memory access signal HACC to "1'°," and writing the read/write information to the read/write control signal R8, the data signal is By setting each write data, it is possible to read and write one word at a time.The completion of the reading and writing operation can be known by the value of the ready signal RDY.For example, when the ready signal RDY reaches “1°°” When this happens, the operation is completed, and in the case of reading, one word of data read out according to the data signal is obtained.

Now, the refresh request storage means is a 256x 1-bit static RAM (hereinafter referred to as SRAM) 5
Consisting of The access time of SRAM5 is, for example, 20
It is nS. Each address in the SRAM 5 stores data indicating the presence or absence of a refresh request for a refresh unit whose refresh unit identifier value is the same as the value of that address.0 For example, if the value of the stored data is “ 0'' indicates that there is no refresh request, and "1" indicates that there is a refresh request.

Give the identifier signal 10 to the address terminals 〇 to 〇,
O7 Write control signal W with value “0” to write enable terminal W
When RITE is applied, data indicating the presence or absence of a refresh request for the refresh unit represented by the refresh unit identifier on the identifier signal ID is obtained at the data output terminal D as a request signal RQ.

Furthermore, when the identifier signal 10 is applied to the address terminal D7 and the write control signal WRITE with the value "1" is applied to the write enable terminal WE, the refresh unit represented by the refresh unit identifier on the identifier signal 10 is refreshed. The value of the data signal DATA applied to the data input terminal D1 is stored as data representing the presence or absence of a request.

The refresh request setting means and the refresh request retrieving means consist of the setting reading time 11@4, and the following 4.
perform one action.

(2) Identifier signal ID: Outputs data indicating the presence or absence of a refresh request for the refresh unit represented by the above refresh unit identifier to the request signal RQ. That is, when the read request signal RDRQ becomes "1", "0" is output to the write control signal -RITE, the value of the identifier signal 10 is output to the identifier signal 10, and the refresh unit identifier on the identifier signal 10 is output from the RAM 5. Data indicating the presence or absence of a refresh request for the refresh unit represented by is obtained as a request signal RQ, and the value is outputted as a request signal RQ.

(2) Identifier Signal ID Data indicating that there is a refresh request is stored in the SRAM 5 as data representing the presence or absence of a refresh request for the refresh unit represented by the above refresh unit identifier. That is, when the set request signal 5ETRQ becomes "1", the value of the identifier signal ID is set to the identifier signal ID, "1" is set to the data signal RI8TA, and the write control signal WR is set to "1".
"1" is output to each ITE, and the identifier signal 10 is used as data indicating the presence or absence of a refresh request for the refresh unit represented by the above refresh unit identifier.
Data indicating that there is a refresh request is stored in the SRAM 5.

(Refresh on first reset identifier R3TID) Data indicating that there is no refresh request is stored in the S RAM 5 as data representing the presence or absence of a refresh request for the refresh unit represented by the reset unit identifier. That is, the first reset request signal R8TRQ
becomes 1", the value of the first reset identifier R3TID is set to the identifier signal 10, and the value of the first reset identifier R3TID is set to "0' to the data code DAT.
'' and 1'° to the write control signal WRITE, and output data indicating no refresh request to the SRAM 5 as data representing the presence or absence of a refresh request for the refresh unit represented by the refresh unit identifier on the first reset identifier R3TID. to be memorized.

(2) Data indicating that there is no refresh request is stored in the SRAM 5 as data representing the presence or absence of a refresh request for the refresh unit represented by the refresh unit identifier on the second reset identifier R8TID2.

That is, the second reset request signal R3TRQ2 is “1”.
'°, outputs the value of the second reset identifier R8TID2 to the identifier signal ID, °'0' to the data signal DATA, '1' to the write control signal RITE, and outputs the value of the second reset identifier R8TID2 to the data signal DATA. Data indicating that there is no refresh request is stored in the SRAM 5 as data representing the presence or absence of a refresh request for the refresh unit represented by the above refresh F rank identifier.

The setting reading circuit 4 operates in synchronization with the clock signal CL. While the value of the clock signal CL is "1", the operation shown in (1) or (2) is performed, and while the value of the clock signal CL is "1", the operation (2) or (2) is performed.

The refresh check request means is a 1/72 frequency divider 1.
and a 256-decimal hex counter 2, which increments by 1 from "0" until it reaches °'255" and returns to "0'°, and the refresh level identification is performed every 7.2 μs.
It generates an ID and a check request signal CKRQ, and issues a refresh check request. That is, 1/72 frequency divider 1
divides the supplied clock signal CL by 1/72 to generate the check request signal CKRQ, and at the same time divides the supplied clock signal CL by 1/72 to generate the check request signal CKRQ.
Drive hexadecimal counter 2. The 256 hexadecimal counter 2 counts the check request signal CKRQ and generates an 8-bit refresh unit identifier CKID.

The refresh request generation means includes a refresh request generation circuit 3, and upon receiving the check request signal CKRQ,
The refresh unit identifier 〇KID is taken in and it is checked whether there is a refresh request for that refresh unit. To do this, the fetched refresh unit identifier CKID is output to the identifier signal ID, and the read request signal RtlRQ is set to "1" to set readout circuit 4.
A request is made to read data indicating whether there is a refresh request for the refresh unit identifier CKID. Refresh unit identifier CK from setting readout circuit 4
When data indicating the presence or absence of a refresh request for ID is obtained in the request signal RQ, its value is checked, and if it is "o", that is, there is no request, the refresh unit identifier CKID is output to the identifier signal In, and the set request signal SE is output.
T is set to "1" and this refresh unit identifier CKI
The setting reading circuit 4 is requested to store data indicating that there is a refresh request for the refresh unit represented by D. The value of request signal RQ is °
``1'', that is, if there is a request, the refresh unit identifier CKI is set to the refresh unit identifier signal REFID.
D and refresh request signal REFRQ,
1'' and generates a refresh request for the refresh unit represented by the refresh unit identifier CKID.

The arbitration means consists of an arbitration circuit 8, which outputs a refresh request signal (REFRQ) and a memory access request signal (IARQ).
and operates as follows to set the refresh permission signal REFAC and the memory access permission signal MAAC.
Generates K. That is, the refresh request signal REF
When the value of RQ is "1", that is, there is a refresh request, a signal (not shown in the figure) in the arbitration circuit indicating whether memory access is in progress is checked regardless of whether there is a memory access request. . If this signal indicates that the memory is not being accessed, the refresh permission signal REFAC is generated. do. At this time, although not shown in the figure, a signal in the arbitration circuit indicating whether refresh is in progress is made to indicate that refresh is in progress, and after the time required for the refresh operation, it is determined that refresh is not in progress. I urge you to show me. Also, if the value of the refresh request signal REFRQ2 is '0' and the value of the memory access request signal (IARQ) is '1', that is, there is no refresh request but there is a memory access request, it is determined whether or not refresh is in progress. Check the signal that indicates.If it is not being refreshed, immediately, if it is being refreshed,
It waits until that signal indicates that it is not being refreshed, and then generates the memory access permission signal HAAC. At this time, the signal indicating whether or not memory access is in progress is made to indicate that memory access is in progress, and after the time required for memory access, it is made to indicate that memory access is not in progress.

The refresh control means consists of a refresh control circuit 6, and the first refresh request signal REFRQ is “
1”, the first refresh unit identifier REFI
D and outputs the second refresh request signal REF.
RQ is set to "1" to request permission from the arbitration circuit 8. When permission is obtained, the refresh permission signal REFACK becomes “
1'', so after waiting for that, the second refresh request signal R [FRQ2 is set to ``0'', the value of the first refresh unit identifier REFID taken into the refresh unit identifier REFID is output, and the refresh is performed. The signal REF is set to "1" and a refresh operation is started for the memory control circuit 9. At the same time, the value of the first refresh unit identifier REFID that has been taken in is output to the first reset identifier R3TID, and the first Reset request] Set the request signal R8TRQ to "1" and store data indicating that there is no refresh request for the refresh unit represented by the first refresh unit identifier REFID in the SRAM 5 via the setting readout circuit 4. .

The memory access control means includes a memory access control circuit 7, and executes memory access from the outside.

That is, when the memory access signal MACC becomes "1'°, each memory access control circuit U 7 sets the memory access request signal HARQ to "1'°, and requests permission for memory access from the arbitration circuit 8. In parallel, address signals A are applied in a predetermined order.
When permission is obtained from the arbitration circuit 8 and the memory access permission signal HAACK becomes 1", the memory access permission signal HAACK becomes 1".
The memory access control circuit 7 sets the memory access request signal 14ARQ to 0'°, and sends the read/write control signal R/ to the address signal that has been read or is being read.
W, and when writing, the data signal is sent to the address signal respectively〇, , read/write control signal R/u+
, and data signal D, sets the memory access signal HACC to "1", and controls the memory control time! 189 to initiate memory access.

When the time required for memory access has passed, the ready signal RDY is set to "1" for a predetermined period of time to complete the memory access. In the case of a read operation, since the read data is obtained in the data signal D, the value of the data signal D is output to the data signal while the ready signal RDY is "1'°.Memory access control port l!87 Also, while accessing the memory, outputs the refresh unit identifier including the address specified by the edge of the address signal to the second reset identifier R8TID, and sets the second reset request signal R8TR0 to "1'°. , the data indicating that there is no refresh request for the refresh unit including the address specified by ◯ in the address signal is stored in the SRAM 5 via the setting readout circuit 4.

The memory control circuit 9 includes DRAM 1000 to DRAM
This circuit controls the 3j1031 to perform refresh operations, read operations, and write operations, and when the value of the refresh signal REF becomes "1", it specifies the refresh unit represented by the refresh unit identifier REFID and performs the normal RAS Performs a refresh operation called only refresh. In addition, memory access signal HAC
When C becomes "1", the read or write operation specified by the read/write control signal R/W is performed for the address specified by the address signal.

DRAM1000~DRAM3.1031 is 2
It is a 56-bit DRAM-LSI. This LSI has a cycle time of 210nS and an access time of 150nS.
There are 256 refresh units in the nS, ft large refresh interval of 54 mS, and one refresh unit is 1024 bits and is specified by the upper 8 bits of the so-called row address.

Next, the overall operation will be explained. 1/72 frequency divider 1 and 256-decimal counter 2 are refresh unit identifier CK
ID is updated every 7.2μs and check request signal CK
RQ is generated to request a check for the presence or absence of a refresh request for the refresh unit represented by the refresh unit identifier CKID. Refresh request generator 83
is activated by the check request signal CKRQ, and checks whether there is a refresh request for the refresh unit represented by the refresh unit identifier CKID.

That is, the identifier signal 10. outputs the value of the refresh unit identifier CKID to “
1'', a request is made to the setting readout circuit 4 to read out data indicating the presence or absence of a refresh request for the refresh unit represented by the refresh unit identifier CKID.

The setting reading circuit 4 and the SRAM 5 operate as described above, and refresh the data indicating the presence or absence of a refresh request for the refresh unit represented by the refresh unit identifier KID as a request signal RQ to the refresh request generating circuit 3. The refresh request generation circuit 3 then checks the value of the request signal RQ. The value is
If it is "0", data indicating that there is no refresh request for that refresh unit is written into the SRAM 5. That is, the value of I[+ is output to the refresh unit identifier C to the identifier signal 101, and the set request signal 5ETRQ is output.
is set to "1" and requests the setting readout circuit 4 to set data indicating that there is no refresh request for the refresh unit represented by the refresh unit identifier 〇KID.

The setting reading circuit 4 and the SRAM 5 operate as described above, and store data indicating that there is no refresh request for the refresh unit represented by the refresh unit identifier 〇KID in the SRAM 5. Then, the operation ends.

The operations explained so far can be summarized as follows. That is, when the refresh request generation circuit 3 is activated by the check request signal CKRQ, the refresh request generation circuit 3 generates the refresh unit identifier C.
Checks whether there is a refresh request for the refresh unit represented by KID, and if there is no request, sends SRA
Data indicating that there is a refresh request for the refresh unit is stored in M5, and the process ends.

Now, returning to the explanation of the operation when the value of the request signal RQ is "1pa", the refresh request generation circuit 3 outputs the value of the refresh unit identifier 〇KID to the refresh unit identifier CKID, and requests a refresh request. The signal REFRQ is set to 1'' to request the refresh control circuit 6 to refresh the refresh unit represented by the value of the refresh unit identifier CKID.

The refresh control circuit 6 receives a refresh request signal RE.
Since FRQ becomes '1'', the following operation starts. First, refresh request signal REFRQ
is set to "1" to request permission for refreshing from the arbitration circuit 8. Arbitration circuit 8 operates as described above to grant permission for the refresh operation. That is, if the memory is not being accessed, the value of the refresh permission signal REFACK is immediately set to 1'' regardless of the value of the memory access request signal MARQ, and if the memory is being accessed, the value of the refresh permission signal REFAC is immediately set to 1'' after the memory access is completed. When the refresh control circuit 6 detects that the value of the refresh permission signal REFAC has become "1", it sets the refresh unit identifier signal REFID to "1".
, that is, the value of the refresh unit identifier CKID, is output as the refresh unit identifier REFID, the refresh signal REFO value is set to "1", the memory control circuit 9 is driven, and the refresh unit indicated by the refresh unit identifier CKID is Perform a refresh operation. At the same time, the refresh unit identifier signal REF
The value of ID, that is, the value of ID to the refresh unit identifier C, is output as the first reset identifier R8TID1, and the value of the first reset request signal R3TRQ is output as "
1'', data indicating that there is no refresh request for the refresh unit represented by the refresh unit identifier CKID is sent to the setting readout circuit 4 from the SRAM.
Request to make it 5. Setting readout circuit 4 and S R
A M 5 operates as described above and stores data indicating that there is no refresh request for the refresh unit represented by the refresh unit identifier CKID. Then, when the refresh:L operation is completed, the refresh request signal REFRQ is set to 0.

The above operations can be summarized as follows. That is, when the check request signal CKRQ is generated, the presence or absence of a refresh request for the refresh unit represented by the refresh unit identifier CKID is checked, and if there is no request, data indicating that there is a refresh request for the refresh unit is stored in the SRAM 5. and exit.

If there is a request, a refresh operation is performed on the refresh unit immediately if the memory is not being accessed, or immediately after the access is completed if the memory is being accessed, and data is stored in the SRAM 5 indicating that there is no refresh request for the refresh unit. and exit.

This operation is performed for all refresh units when the value of the refresh unit identifier is 0, 1, . ..., 255.0.1. ....

255, 0. 1. ...is repeated in this order. Regarding one glue french unit, it is 7.2μsX 25
6=1843.2us, i.e. 1.8432m S
This operation is repeated at a cycle of .

Next, the movement of external memory access operations will be explained. An external memory access operation is started when the value of the memory access signal 14ACC becomes '1', and the address signal AD is activated in a predetermined order.
, read/write control signal R/W, and data signal D (only during write access) are input. The memory access control circuit 7 performs memory access.

When the value of the access signal HACC becomes 1", the memory access request signal MARQ is set to "1" to request permission for memory access from the arbitration circuit 8. 1'', it operates as described above and allows memory access. That is, the value of the refresh request signal REFRQ from the refresh control circuit 6 is "0°."

, and if a refresh operation is not in progress, immediately, otherwise the requested or ongoing refresh operation ends, and at that point, the value of the refresh request signal REFRQ□ becomes “ 0'' is satisfied, and the memory access permission signal HAA is
Set CK to “1”. Upon receiving permission from the arbitration circuit 8, the memory access control circuit 7 sends the memory access signal HACC, read/write control signal R/W, address signal 〇, and data signal D at a predetermined timing.
(Only during write access) is supplied to the memory control circuit 9 to perform the desired access. At the time of read access, read data is obtained as the data signal D, and its value is output as the data signal. At this time, a ready signal RDY is output to synchronize with the outside. During write access, the ready signal RDY is similarly output to synchronize with the outside.

Further, when permission is obtained from the arbitration circuit 8, the second reset identifier R3TI (l) is outputted as a refresh+B rank two-unit identifier to which the address accessing the address belongs, and a second reset request signal is output. Set R3TIIQ2 to "1" and request the setting readout circuit i?84 to store data indicating that there is no refresh request for the refresh unit to which the accessed address belongs. operates as described above, and stores in the SRAM 5 data indicating that there is no refresh request for the refresh unit to which the address that is accessing the memory belongs.Then, when the memory access is completed, the memory access request signal HAFIQ is output. ° Set to 0pa.

The memory access operation described above can be summarized as follows. That is, memory access from the outside is executed by selecting a timing when there is no refresh request and is not in the middle of refresh, and data indicating that there is no refresh request for the refresh unit including the address accessed at the same time is stored in the SRAM 5.

The above is an explanation of the operation of the apparatus of this embodiment. Next, it will be explained how this device achieves the object of the present invention. In this device, as in conventional devices, no information is lost. Furthermore, the number of refresh operations per unit time is reduced compared to conventional devices. The above two points will be explained below with reference to the drawings.

FIG. 2 is a diagram illustrating an outline of the operation of the apparatus of this embodiment regarding one refresh unit.

The horizontal axis is time, CPi, CPi+1, CPi+2,
CPi+3 and CPi+4 are the 1st, i+1st, i+21st, and i+ for this refresh unit, respectively.
It represents the time point at which the third and i+4th refresh check requests occur (i is a positive integer). In this figure, (a), (
b), (c), and (d) respectively show operations due to different temporal combinations of memory access and refresh operations. In these figures, ■ marked with "↓" indicates refresh for this refresh unit. Represents an operation, “↓
Φ with " is a memory access to an address belonging to this refresh unit. The pulse shape is SR
It represents the value of the refresh request for this refresh position held by AM5. A high level represents "refresh request", and a low level represents "no refresh request". Below, (a), (b), (C
) and (d) will be explained in this order.

FIG. 2(a) shows that at the refresh check request generation point CPi, the value "refresh request present" is read out from the SRAM 5, and after the refresh operation is performed at the immediately following ■, the refresh check request generation point CPi+
This is the operation when there is no memory access to the address belonging to this refresh unit during the period up to 2. In this case, when the refresh operation is performed in (2), the refresh control circuit 6 changes the value stored in the SRAM 5 to "no refresh request". Since there is no memory access to this refresh unit between refresh check request generation time CPi and CPi+1, at refresh check request generation time CPi+1, refresh request generation circuit 3 changes the value stored in SRAM 5 to "
Change it to "Refresh requested". Furthermore, since there is no memory access to this refresh unit between refresh check request generation time CPi+1 and CPi+2, refresh check request generation time CP
At i'-,2, the refresh request generation circuit 3 requests refresh, and at (2), the refresh operation is performed. At this time, the value stored in SRAM 5 is determined by the refresh control circuit 6 as "no refresh request".
can be changed to

FIG. 2(b) shows the refresh check request generation point CPi, which is the same as FIG.
, +1, and there is no refresh check request at all between CPi+1 and CPi+2. Now, when the memory access is performed in ・■, the memory access control circuit 7
The value ``No refresh request J'' is stored in the RAM 5. Refresh check request generation point CPi+1
In this case, as shown in the figure, the value "No refresh request" is read out, and since there is no memory access to the address belonging to this refresh unit between the refresh check request generation time CPi+1 and CPi+2, the refresh check request is not executed. Check request generation point C
The operation after Pi+1 is as shown in FIG. 2(a).
The operation is the same as that after the check request generation point CPi+1. Note that memory access performed when the value held by the SRAM 5 is "no refresh request" does not affect the subsequent operation, so it will be omitted from the following explanation. 6 Figure 2 (C) shows the refresh・The check request generation time point CPi is the same as in FIG.
More than once, CP at the time of refresh check request
The case where there is no data between i+2 and CPi+3 is shown. ■ indicates the first access point among these memory accesses. At this time, the value held in the SRAM 5 is set to "No refresh request" by the memory access control circuit 7.
It can be changed to the value . As shown in the figure, at the refresh check request generation time point CP i +2,
Since the value "No refresh request" is read and there is no memory access to this refresh unit until the refresh check request generation time point CPi+3, the operation after the refresh check request generation time point CP1+2 is , CPi+ in FIG. 2(a)
The operation is the same as after 1.

FIG. 2(d) is the same as FIG. 2(a) at the refresh check request generation time CPi, and the memory access for this refresh unit is 1 between the refresh check request generation time CPi+1 and CPi+2.
At least once, and at least once between CPi+2 and CPi+3, at the time of refresh check request CPi+
Between 3 and CPi+4, there is no case at all.

Similarly to FIG. 2(C), (2) indicates the first memory access time in each period. The operation from the refresh check request generating time point CPi to CPi+2 is the same as that in FIG. 2(C). At the second @, S R
The value of A M 5 is changed to the value ``No Reflet Soche Request''. The operation after the refresh check request generation point CP i +3 is the same as the operation after the refresh check request generation point CPi+1 in FIG. 2(a).

In FIG. 2(d), the operation is similar when there is a memory access to an address belonging to this refresh unit between the refresh check request generation time point CPi+3 and CPi+4.

From this, a refresh operation is performed, and n-1 periods including the next refresh check request generation time and separated by n subsequent refresh check request generation times (n is an integer greater than or equal to 2) If there is at least one memory access to an address belonging to this refresh unit in each period of
As can be seen from C) and (d), the time point at which the second refresh operation is performed is shifted n-1 periods later than in FIG. 2(a).

As mentioned above, when a memory access is performed, the refresh unit that includes that address is automatically refreshed, so at the time point ■ in Figure 2, the refresh unit has been refreshed just like at one time point. . In Figure 2, the longest interval between two consecutive refreshes, that is, between the successive ■ and 0.10 and Φ, ■ and Ol, and ■ and ・■, is the longest between O and ■ in Figure 2 (a). It is between. This time interval is approximately equal to the time interval of 3.6864 mS between three successive refresh request occurrences. ``Habo'' means that the first point ◯ is one memory cycle (300n in the device of this embodiment) due to competition with memory access.
S) may be delayed, or the second O may be delayed by one memory cycle due to conflict with memory access. Still, the worst value is 3.6867 mS, which is the maximum refresh interval 4
mSufficiently shorter than S. Since the above is true for all refresh units, no IrW volume is lost in the device of this embodiment.

In addition, refresh operations are performed as shown in FIGS. 2(C) and (d), and the subsequent n times including the time when the next refresh check request is generated (n is an integer of 2 or more)
n- separated at the time the refresh check request is generated
If there is at least one memory access to an address belonging to this refresh unit in each period, the interval between one refresh operation and the next refresh operation will be as shown in FIG. 2(a). In comparison, ((n-
1) x 1.8432) m S becomes longer. Since this is true for all refresh units, the frequency of refresh operations also decreases.

As described above, in the device of this embodiment, the frequency of refresh operations can be reduced and the memory access execution speed can be improved without losing the memory of the DRAM.

Note that in the device of this embodiment, the storage capacity is 256K.
W, but 512KW, IMW, etc. are also acceptable. In this case, the 256-bit DRAM is divided into two or four banks, and the upper one or two bits of the address are decoded to select the bank for reading and writing. At this time, for banks that are not selected, RA is applied to the refresh unit to which the address belongs.
All you need to do is perform an S-only refresh.
A refresh operation triggered by a check is performed on all banks simultaneously. Further, although the data width that can be accessed per time is 32 bits, it may be 8 bits, 16 bits, etc.

(Effects of the Invention) As explained in detail above, the present invention makes it possible to reduce the number of refresh operations by effectively utilizing the refresh effect of normal memory accesses, thereby increasing the memory access execution speed. improve.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 (
a) to (d) are timing diagrams showing an overview of the operation of the embodiment. 1...1/72 frequency divider, 2...256 hexadecimal counter, 6...Refresh request generation circuit, 4...Setting reading circuit, 5...SRAM, 6...Refresh control Circuit, 7... Memory access control circuit, 8...
Arbitration circuit, 9...Memory control circuit, 1000-103
1...DRAM.

Claims (1)

[Claims] In a control method for a dynamic random access memory system having one or more refresh units that are refreshed by one refresh operation, a refresh unit identifier that uniquely identifies each refresh unit is defined, For all refresh units, a refresh request storage means stores data representing the presence or absence of a refresh request for each refresh unit, and a refresh request storage means stores data representing the presence or absence of a refresh request for the refresh unit represented by a given refresh unit identifier. a refresh request setting means for storing the given data in the refresh request storage means; a refresh request retrieval means for retrieving data representing the presence or absence of a refresh request for the refresh unit represented by the given identifier from the refresh request storage means; Generates refresh unit identifiers for all refresh units in a predetermined order at time intervals that are sufficiently larger than the cycle time of the random access memory, and then generates refresh unit identifiers for the refresh units represented by each generated refresh unit identifier. refresh check request means for generating a check request at a repetition period that is sufficiently shorter than half of the maximum refresh interval and sufficiently longer than one-third of the maximum refresh interval; and a refresh indicated by a given refresh unit identifier. The refresh request retrieving means retrieves data indicating whether there is a refresh request for the unit from the refresh request storage means, checks whether there is a refresh request, and if there is no refresh request, refreshes the data indicating that there is a refresh request for the refresh unit. a refresh request generating means for storing the refresh request in the refresh request storage means by the request setting means, and generating a refresh request together with an identifier of the refresh unit when there is a refresh request; Permits refresh immediately, if memory access is in progress, waits for the end of memory access and then allows refresh; if there is a memory access request and there is no refresh request at the same time, immediately permits memory access, and if refresh is in progress Then, there is an arbitration means that waits for the completion of the refresh and then permits memory access, thereby arbitrating so that refresh and memory access do not conflict; and a refresh request generated by the refresh request generation means with permission from the arbitration means. refresh control means for refreshing a refresh unit represented by an identifier given by and causing the refresh request setting means to store data indicating that there is no refresh request for the refresh unit in the refresh request storage means; When a refresh request occurs, the memory access is executed with permission from the arbitration means, and an identifier of the refresh unit including the address to be accessed and data indicating that there is no refresh request are given to the refresh request setting means, and refresh for that refresh unit is performed. 1. A control method for a dynamic random access memory, comprising: memory access control means for causing a refresh request storage means to store that there is no request.