JPS6049421A - Generating system of timing pulse - Google Patents

Abstract

PURPOSE:To generate various types of timing pulses with a small quantity of hardware by storing the timing waveform data to a memory for each type of the data. CONSTITUTION:The timing waveform data corresponding to various types of identification signals are previously stored to each storage area of an RAM9. Then an access is given to the RAM9 by the type identification signal given from a register 3 and the signal given from a counter 1 for designating the type storage area. Thus the timing waveform data stored in the storage areas are read successively out of the RAM9 in response to the count-up of the counter 1. Then the timing pulses are produced. It is possible to produce various types of timing pulses with a small quantity of hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a timing pulse generation method, and more particularly to a timing pulse generation method that is capable of generating various timing pulses with a small amount of hardware.

(Background of sigma technology) Some circuits under test are configured to operate at predetermined timings. For example, this is a memory used in an information processing device. This type of circuit under test In order to test whether or not the circuit operates successfully, a technique is generally adopted in which a predetermined timing pulse is supplied to the circuit under test and the operation is checked.
Depending on the circuit under test, not only one type of timing pulse but many types may be required to be supplied to the circuit.

When attempting to generate many types of timing pulses, conventional circuits of this type not only require an increase in the amount of hardware due to their configuration constraints, resulting in a lack of compactness, but also the pulse generation There are problems such as the fact that the type is fixed and βJ modification cannot be provided for, and there is a need for ways to improve this problem.

Q-Cooling Prior Art and Problems Among the many types of conventional timing pulse generation circuits, there is one that uses a counter and generates various required timing pulses by switching the operation mode of the counter.

If such a circuit configuration is adopted, the amount of hardware will inevitably have to be increased. As a result, it lacks compactness. In addition, the types of timing pulses that can be generated from the circuit are fixed to the pulses R at the time of designing the circuit, and the request to change the type of timing pulses as necessary cannot be satisfied at all.

(Object of the Invention) The present invention was devised in view of the drawbacks of the conventional techniques as described above. The object of the present invention is to provide a pulse generation method.

g) Structure of the Invention In order to achieve this object, the method of the present invention stores timing waveform data for each type in a storage device, and uses the type identification signal and access signal for the type storage area to access the storage. The timing pulse is generated by accessing the device.

(f) Examples of the invention Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The accompanying drawings illustrate one embodiment of the invention. In this diagram,
■ is a counter that receives clock pulses via line 2, and 3
is a register which receives a type identification signal via the type identification signal line 4.5, for example, when the circuit under test that operates at a predetermined timing is a memory, its operation mode signal. The cottons 4,5 are also connected to a resistor 6. The output of counter l is via line 7 and the output of register 3 is via line 8.
It is connected to the addressing section of a random access memory (hereinafter abbreviated as RAM) 9 through the RAM. R
If AM9 is iK x hint capacitance, then line 8 is R
The upper two bits Δ9. of the address for accessing AM9. The two lines for transferring A8 are shown, and the line 7 represents eight lines for transferring the lower 8 bits A7 to AO of the access address of RAM9.

If the line 8 is as shown in the above example, this RAM 9 is divided into four storage areas, and each storage area has one
- Timing waveform data corresponding to the above identification signal is stored in advance (in this sense, each storage area is referred to as a type storage area), or is written by the data writing circuit 10 as necessary.

)? The output of AM9 is connected to a timing fine adjustment circuit 11, from which timing pulses are supplied via line 12 to a memory (not shown). Further, the output of the register 6 is connected to the timing fine adjustment input of the circuit 11.

Next, the operation of the above-mentioned configuration circuit will be explained.

It is assumed that timing waveform data is stored in advance in the RAM 9 in the following manner. That is, the timing pulse output via line 12 is supplied to a dynamic memory (not shown), and the timing waveform data for that timing pulse, that is, the data when the memory is in read mode, and the data when the memory is in write mode. Data for a certain case, data for when the memory is in refresh mode, and other data for example options are stored in the storage areas that are accessed as distinguished by the upper two bits.

Once the circuit is ready, an operating mode signal is set in registers 3 and 6 via line 4.5 and a clock pulse is applied to counter 1 via line 2 to clock the counter 1's count. A 1-up operation is initiated. The callan l is supplied to the addressing section of the RAM 9 together with the operation mode signal of the register 3, that is, the signal specifying the above-mentioned storage area. If the operation mode signal is, for example, a read mode signal, the timing waveform data in the storage area assigned to the read mode is read out from the RAM 9 one after another in step with the count up of the counter 1, forming a timing pulse. To go. The timing pulse is subjected to timing adjustment as necessary by a timing fine adjustment circuit 11 which receives the contents of the register 6 at its timing fine adjustment input, and is converted into a pulse with a desired timing and sent onto a line 12. be done.

The manner in which the other timing pulses are generated is also the same, except that the storage area accessed differs due to the different operation mode signals, and the timing waveform data read out differs.

In this way, various timing pulses can be generated, but the amount of hardware required for the generation is small, as is clear from the above. Therefore,
Helps make the circuit more compact.

The generation of the various timings described above is achieved by providing more storage areas corresponding to the operation mode signals described above, and supplying operation mode signals corresponding to the operation mode signals as necessary to select the storage area. By doing so, the generation of timing pulses can be changed freely.

Further, by rewriting the timing waveform data in the RAM 9 in the data write circuit 10 between the generation of the timing pulses described above, it is possible to provide variability in the timing pulse generation.

Each of the timing pulses generated as described above is used to test a circuit under test, for example, to measure the timing margin of a memory.

In addition, in the embodiment described in -A, RA is used as the storage device 7.
Although the explanation has been given using M as an example, it may also be a ROM.

(G) Effects of the Invention As described above, according to the present invention, it is possible to reduce the amount of hardware, and also to generate timing pulses while providing variability in the generation of various timing pulses. Compactness is achieved by reducing the amount of hardware.

[Brief explanation of drawings]

The accompanying drawings illustrate one embodiment of the invention. In the figure, 3 is a counter, 3 is a register, and 9 is a RAM.

Claims (1)

[Claims] A timing pulse characterized in that timing waveform data is stored in a storage device for each type, and the storage device is accessed using the type identification signal and an access signal for a type storage area to generate a timing pulse. How it occurs.