JP2590712B2 - Memory controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device having a refresh control mechanism for a dynamic random access memory (hereinafter referred to as DRAM).

[0002]

2. Description of the Related Art In a conventional memory control device, when refreshing a DRAM, refreshing is performed when a refresh timer times out, and normal memory access is controlled during refreshing. For example, JP-A-4-364295 discloses a DR
A DRAM control circuit that includes a refresh timer that generates timing for refreshing an AM at regular intervals and a refresh address counter that counts addresses for refreshing the DRAM and generates a refresh request signal at regular intervals is described. I have.

[0003]

In this prior art,
Periodically triggered by the refresh timer timeout
In order to refresh the RAM, if a normal memory access coincides with the refresh timing of the DRAM,
There is a problem that the normal memory access is kept waiting and the memory access performance is reduced.

[0004]

In order to solve the above-mentioned problems, the present invention arbitrates access from a central processing unit to a storage device comprising a plurality of memory banks and arbitration of a DRAM refresh operation in the storage device. A memory control device that specifies which memory bank in the storage device is to be accessed based on a memory access address requested by the central processing unit; and a plurality of storage devices in the storage device. A plurality of refresh timer means for counting the time elapsed since the memory bank was last refreshed, and generating a timeout signal when the memory bank reaches a limit value; If a signal is generated, the refresh timer means that generated the timeout signal Selecting a corresponding memory bank, otherwise the corresponding memory bank has been refreshed most recently, except for the refresh timer means corresponding to the memory bank specified by the bank control means among the refresh timer means. Means for selecting a memory bank corresponding to the refresh timer means indicating that the refresh is required, and a memory for refreshing the DRAM of the corresponding memory bank of the storage device in response to a request from the timer comparison means. Refresh activation means.

Further, there is provided a timer threshold value storage means for defining a range in which refreshing is to be suppressed within a limit value range of the refresh timer means. Except for the refresh timer means corresponding to the memory bank specified by the bank control means, the value of the refresh timer means indicating that the corresponding memory bank has been refreshed most recently is specified by the timer threshold value storage means. Only when it is out of the range, the memory bank corresponding to the refresh timer means is selected and refresh is requested.

The refresh timer means is reset at the time of refreshing the DRAM of the corresponding memory bank, and thereafter counts up at every clock.
When the count reaches the predetermined upper limit value, the count-up is stopped and a time-out signal is transmitted to the timer comparing means.The timer comparing means sets the memory bank corresponding to the refresh timer means having the largest value to the earliest one. Treated as a refreshed memory bank.

[0007]

Next, a first embodiment of the memory control device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a memory control device 200 according to a first embodiment of the present invention includes a bank control unit 210.
And n refresh timers 221 to 22n and a memory refresh control unit 230. further,
The memory refresh control unit 230 includes the timer comparison unit 23
3 and a memory refresh activation unit 236.
The memory controller 300 is connected to the central processing unit 100 by the bank control unit 210, and includes a storage device 300 including n memory banks 311 to 31 n and a memory refresh activation unit 2.
36.

[0009] The bank control unit 210 is a central processing unit 10
When a memory access occurs from 0, it determines which memory bank of the storage device 300 is to be accessed from the address to be accessed and transmits it to the timer comparison unit 233. For example, from the address “00000000” to the address “0FFFFFF” (in hexadecimal notation) is assigned to the first bank, and
Memory allocation, such as allocating up to address 1FFFFFF "to a second bank, is performed in advance.

The refresh timers 221 to 22n are provided corresponding to the respective memory banks 311 to 31n of the storage device 300, and transmit the time elapsed since the last refresh of the corresponding memory bank to the timer comparator 233. That is, these refresh timers 221 to 22
n is reset at the time of refresh, and thereafter is counted up every clock. When the refresh timers 221 to 22n reach a predetermined upper limit, they stop counting up, and transmit a timeout signal to the timer comparison unit 233.

The timer comparing section 233 has a function of specifying the refresh timer indicating the largest value among the values indicated by the refresh timers 221 to 22n. When a memory access occurs from the central processing unit 100, a refresh timer indicating the largest value is specified from among the refresh timers other than the refresh timer corresponding to the memory bank related to the memory access, and this refresh timer is specified. The timer comparing unit 233 refreshes the memory bank corresponding to the refresh timer.
From the memory refresh start unit 236.
In addition, the timer comparing unit 233 controls the refresh timer 221.
When a time-out signal is received from any one of .about.22n, the timer comparator 233 instructs the memory refresh activation unit 236 to refresh the memory bank corresponding to the refresh timer that generated the time-out signal.

The memory refresh activation unit 236 performs a memory refresh for a memory bank in the storage device 300 that has been instructed by the timer comparison unit 233 to request a memory refresh. This memory refresh activation unit 236
Has n refresh address counters corresponding to each memory bank, and supplies a refresh address to the storage device 300 so as to refresh the designated memory bank. If the DRAM has the memory refresh control function, it is sufficient to simply transmit the refresh request to the memory bank.

Next, the operation of the first embodiment of the present invention will be described with reference to a flowchart.

Referring to FIG. 2, in the memory control device according to the first embodiment of the present invention, first, it is determined whether or not a timeout has occurred in any of the refresh timers by the timer comparison unit 233 (step 501). ). If a timeout has occurred, the refresh operation for the memory bank corresponding to the refresh timer in which the timeout has occurred is performed by the memory refresh activation unit 23.
6 (step 504). At this time,
Even if a memory access request is issued from the central processing unit 100, the memory access is prohibited until the memory refresh ends. After the memory refresh is completed, the corresponding refresh timer is reset (step 505), and the determination in step 501 is performed again.

If it is determined in step 501 that no timeout has occurred, then the central processing unit 100
It is determined whether or not a memory access request has been issued (step 502). If the memory access request has been issued, the timer comparison unit 233 simultaneously determines whether a refresh timer other than the refresh timer corresponding to the memory bank related to this memory access has occurred. The refresh timer indicating the largest value is specified from among them (step 503). The memory refresh activation unit 23 refreshes the memory bank corresponding to the refresh timer.
To 6. Upon receiving the refresh request, the memory refresh activation unit 236 performs a refresh operation on the corresponding memory bank in the storage device 300 (Step 504). After completion of the memory refresh, the corresponding refresh timer is reset (step 50).
5) The determination of step 501 is performed again.

As described above, according to the first embodiment of the present application, at the same time when a memory access occurs, the memory bank that has been refreshed most recently among the memory banks other than the memory bank related to the memory access is set. By performing the refresh, the degree of occurrence of the refresh timeout can be suppressed low, and the refresh operation and the normal memory access can be prevented from overlapping at the same time as much as possible.

Next, a second embodiment of the memory control device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 3, a memory control device 200 according to a second embodiment of the present invention has the same configuration as that of the first embodiment except that a timer threshold value storage unit 290 is provided. doing. When a memory access is generated from the central processing unit 100, the timer threshold value storage unit 290 stores a refresh timer indicating the largest value among the refresh timers other than the refresh timers corresponding to the memory bank related to the memory access. Hereinafter, a threshold value for the value of the maximum refresh timer is stored. That is, the value of the maximum refresh timer is compared with the threshold value of the timer threshold value storage unit 290 by the timer comparison unit 234, and only when the value of the maximum refresh timer is larger, the memory refresh activation unit 236 Signal to refresh. By doing so, it is possible to control so as to suppress the occurrence of unnecessary refresh.

The threshold value of timer threshold value storage section 290 can be set to any value in accordance with an instruction from central processing unit 100. For example, it is conceivable to set the value to about half of the maximum value of the refresh timer. However,
In this case, the rate of occurrence of the timeout of the refresh timer may be higher than in the first embodiment.

Next, the operation of the second embodiment of the present invention will be described with reference to a flowchart.

Referring to FIG. 4, in the memory control device according to the second embodiment of the present invention, first, whether or not a timeout has occurred in any of the refresh timers is determined by the timer comparison unit 234 (step 601). ). If a timeout has occurred, the refresh operation for the memory bank corresponding to the refresh timer in which the timeout has occurred is performed by the memory refresh activation unit 23.
6 (step 605). At this time,
Even if a memory access request is issued from the central processing unit 100, the memory access is prohibited until the memory refresh ends. After the completion of the memory refresh, the corresponding refresh timer is reset (step 606), and the determination in step 601 is performed again.

If it is determined in step 601 that no timeout has occurred, then the central processing unit 100
It is determined whether or not a memory access request has been generated (step 602). If the memory access request has been generated, the timer comparison unit 234 determines whether a refresh timer other than the refresh timer corresponding to the memory bank related to this memory access has occurred at the same time as the memory access. The refresh timer indicating the largest value is specified from among them (step 603). Then, the value of the refresh timer is compared with the threshold value of the timer threshold value storage unit 290 (step 604).
If the value of the refresh timer is larger, the value is transmitted to the memory refresh activation unit 236 so as to refresh the memory bank corresponding to the refresh timer.
Upon receiving the refresh request, the memory refresh activation unit 236 performs a refresh operation on the corresponding memory bank in the storage device 300 (step 60).
5). After the completion of the memory refresh, the corresponding refresh timer is reset (step 606), and the determination in step 601 is performed again.

As described above, according to the second embodiment of the present application, by providing the timer threshold value storage unit 290,
Compared with the first embodiment of the present application, the frequency of refresh can be suppressed lower, and the power consumption of the DRAM can be suppressed.

[0024]

As described above, the memory control device according to the present invention reduces the occurrence of the refresh timeout by refreshing the DRAM of the memory bank not accessed during the access from the central processing unit. Thus, the refresh operation and the normal memory access can be prevented from overlapping at the same time as much as possible, and the operation and effect of the present invention can be achieved while suppressing power consumption by adjusting the timer threshold value. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a memory control device of the present invention.

FIG. 2 is a flowchart showing the operation of the first embodiment of the memory control device of the present invention.

FIG. 3 is a block diagram showing a second embodiment of the memory control device of the present invention.

FIG. 4 is a flowchart showing the operation of the second embodiment of the memory control device of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 central processing unit 200 memory control device 210 bank control unit 221 to 22n refresh timer 230 memory refresh control unit 233, 234 timer comparison unit 236 memory refresh activation unit 290 timer threshold storage unit 300 storage device 311 to 31n memory bank

Claims (1)

(57) [Claims] 1. A storage device comprising a plurality of memory banks.
Access from the central processing unit to the
Refresh operation of dynamic random access memory
A memory control device that arbitrates between operations and an address of a memory access requested by the central processing unit.
Which memory bank in the storage device
Bank control means for specifying whether access to the memory device, and a plurality of memory banks corresponding to each of the plurality of memory banks in the storage device.
The memory bank is refreshed immediately before
Count the elapsed time from when the limit was reached, and when the limit was reached
Multiple refresh timers that generate timeout signals
Means within the limits of these refresh timer means.
Timer that defines the range in which refresh is to be suppressed
Value storage means and the time-out signal if the time-out signal has been generated.
Corresponding to the refresh timer that generated the reset signal.
Select the memory bank and generate the timeout signal.
If not, the refresh timer means
Link corresponding to the memory bank specified by the link control means.
Other than the refresh timer means, the corresponding memory bank
Also indicates that it has been previously refreshed.
The value of the timer is stored in the timer threshold storage means.
If it is out of the specified range,
Select the memory bank corresponding to the row and refresh
Requesting timer comparing means, and the storage device according to the request from the timer comparing means.
Dynamic random access memo of the corresponding memory bank
Memory refresh activation means for refreshing memory
A memory control device comprising: