JPH0241108B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a main memory refresh control method using dynamic MOS RAM. Main memory refresh control in general-purpose computer systems is performed in interleave units at a low priority so as not to impede access to the processing unit (for example, central processing unit CPU or channel processor CHP) as much as possible. The time is monitored so that 1 ^LN (LN is line) is completed within the period of . Here, interleaving refers to the process of dividing main memory into a large number of individually controllable blocks for the purpose of improving throughput when using relatively slow RAM for reasons such as economy. It refers to a block, and 1 ^IL (IL is interleaved) is defined as a division of, for example, 8 ^B (B is byte). Also, 1 ^LM is
For example, a 64 ^K RAM consists of a matrix of 256 ^LM × 256 ^b (b is bit), so
1 ^LM , or 256 ^b cell rows. However, large-capacity main memory generally has a large number of RAM elements ( ^64K
RAM, etc.), so the lines common to each RAM element are collectively referred to as 1 ^LM . The above-mentioned refresh control system changes a lower priority to a higher priority when the remaining time becomes short as a result of time monitoring, thereby ensuring that the refresh is completed within a certain period of time. However, if this refresh method is directly applied to special computers used for science and technology, such as vector processors, the following problems arise. (1) In general, main memory access in vector operations requires accessing consecutive data at high speed and throughput. However, when refreshing is performed in units of interleave, a specific interleave must be set to "BUSY" a number of times equal to the total number of interleaves in a certain period of the first half. Therefore, the probability that access from the vector unit to the main memory will be interrupted by refresh is higher than in a general-purpose computer. (2) Moreover, in vector processors, the number of interleaves tends to be increased in order to improve the throughput of access to the main memory, so the problem (1) becomes even more serious. The present invention attempts to perform refresh in a system that frequently accesses main memory, such as a vector processor, in a manner that suppresses interference with the access as much as possible, and is characterized by a dynamic random In a main memory refresh control method of a system in which a main memory composed of access memory elements is divided into a plurality of interleaves and each interleave can be accessed independently, during refresh, all interleaves are simultaneously accessed and each memory element is The cells within the line are refreshed line by line, and the corresponding line is refreshed once within a certain refresh period assigned to each line, and a predetermined first number of cycles is required. a first time monitoring means for determining that a memory access for which the specified time is not performed during the cycle; and a memory access that requires a second number of cycles different from the first number of cycles; providing a second time monitoring means for determining what has not been done between cycles;
The refresh cycle is divided into three periods, the priority of the refresh with respect to the normal memory access is set for each of the three divided periods, and the first period at the beginning of the three divided periods is: Prioritizing access to the memory, the first time monitoring means and the second time monitoring means each perform a refresh when it is determined that no access has been made, and Prohibits access to the memory when either the first time monitoring means or the second time monitoring means detects that no access is performed during the period 2;
Thereafter, when the first time monitoring means and the second time monitoring means each determine that no access has been made, the refresh is performed, and in the third and final period of the three divided periods, , second
When neither the first time monitoring means nor the second time monitoring means detects that there is no access during the period, access to the memory is prohibited, and then the first time monitoring means and the second time monitoring means prohibit access to the memory. The second time monitoring means performs refresh when determining that no access has been performed, and the priority of refresh over normal memory access is low at the beginning of the refresh period and becomes high toward the end; The point is to determine the optimum refresh time within the refresh cycle. This will be explained in detail below with reference to illustrated embodiments. As mentioned above, a 64 ^K -bit RAM element is 256 ^LM ×
It consists of a matrix of 256 ^b , and 1 ^LM (256 ^b ) is refreshed in one refresh. Therefore 1
If you try to refresh an entire RAM element, it will take 256 refreshes. For example 1
Maximum refresh interval for all RAM elements
16 ^ms , for this RAM element within 16 ^ms .
Refresh processing for each line must be sequentially performed 256 times, that is, once every 62 ^seconds . General refresh time monitoring control is
To reduce the amount of hardware and simplify control
This is done in units of 1 ^IL . In other words, control is performed so that 1 ^LM of all the RAM elements existing in the system are refreshed in 62 ^s . Figure 1 is a configuration diagram of a main memory MS with a capacity of 256 ^MB (MB is megabyte), and is an example of a main memory MS divided into 256 ^ILs . One ^IL is 8 ^B (72 bits in this example), and the shaded area is one 64 ^Kb RAM element. Accordingly
32 ^IL is 32 x 8 ^B x 2 x 64 ^K bits. The access throughput from the memory control unit MCU to the main memory MS is 8 ^B x 8/cycle, and each memory access controller MAC controls 32 ^IL . The MCU individually monitors the “BUSY” status of 256 ^ILs . There is a 256-bit "BUSY" flag FG ₀ to FG ₂₅₅ , and when this flag is "off", access can only be activated for interleaving. 8 MAC #0~
#7 can initiate an 8 ^B unit access every cycle to one of each 32 ^IL using the address specified by the MCU. In the present invention, 256 ^IL x 8 ^B (72 bits) x 2 are refreshed at one time. This region is indicated by the dashed line AR ₁ ,
It is AR ₂ , and in one refresh, the conventional 256
Equivalent to twice as much. When the MCU activates refresh for 8 MACs #0 to #7 at the same time, each MAC has 32 ^IL × 8 ^B connected to itself.
(72 bits) Refresh 1 ^LN of all 2 RAM elements. At this time, the MCU prohibits access to the main memory MS for a certain period of time until "BUSY" due to refresh is released. or,
The MCU also prohibits access to the main memory MS for a certain period of time when starting refresh. This is to prevent refresh from overlapping with normal access, but if it is prohibited for too long, performance problems will occur. Monitor and use your free time to refresh as much as possible. FIG. 2 shows a time monitoring circuit during a period when the MCU is not initiating access. Assuming that the cycle time of one interleave that constitutes the main memory is 24 cycles, the partial write takes 48 cycles. In the circuit shown in Figure 2, the partial light is
Counter that 48 cycles were not activated
CNT ₁ and counter CNT ₂ detect that all accesses have not been activated for 24 cycles. When starting refresh, all interleaves must be in a non-BUSY state, so in the worst case, access to the main memory MS must be prohibited for 48 cycles. In order to shorten this prohibition period, refresh is actively activated during free time by detecting the number of cycles in which the above-mentioned access is not activated within a certain fixed period (62 ^s in this example). FIG. 3 shows the refresh activation algorithm. In other words, the counter for NPW detection
_CNT1 counts up (+1) when the output of OR gate _G1 is 0, and is set when it is 1 (ALL "0" is written). The output of OR gate _G1 is 0 when there are 2 inputs PW G, +REF G
are both 0, otherwise the output is 1. +PW G becomes 1 when partial write is activated, and +REF G becomes 1 when refresh is activated. Therefore the counter
The output NPW48 of CNT ₁ becomes 1 when the period in which partial write is not activated reaches 48 consecutive cycles. On the other hand, NMA detection counter CNT ₂
monitors all accesses such as partial write, store, full store, fetish, etc. It counts up (+1) at the 0 output of OR gate _G2 ,
It is reset with 1 output (ALL "0" is written). The two inputs of the OR gate _G2 are +MAG, and +MAG becomes 1 if there is any memory access. Therefore, the output of counter CNT ₂
NMA24 has consecutive periods with no access.
It becomes 1 when it reaches 24 cycles. The refresh activation algorithm shown in FIG. 3 has three types of modes (periods) A, B, and C.
Period A is the earliest period of 62 ^seconds , and during this period, refresh is given the lowest priority and other accesses are prioritized. However, if there is no other access during this period, you can refresh it.
If both NPW48 and NMA24 become 1, all interleaves are not "BUSY", so refresh is performed immediately. In this case, the period in which access is prohibited for refreshing activation is unnecessary as shown in the table below.

[Table] Period B is an intermediate period of 62 μs, and has a higher refresh priority than period A. In other words,
When one of NPW48 and NMA24 becomes 1, subsequent access is prohibited, and when both NPW48 and NMA24 become 1, refresh is started.
Therefore, in this case, the access prohibition period for starting the refresh is 1 to 24 cycles as shown in the table above, and this period is time-monitored. Period C
is the final period of 62〓 ^s and has the highest priority. In other words, refreshments that were postponed during periods A and B are
Must be executed in period C. To do this, as shown in the table above, even if both NPW48 and NMA24 are 0, future memory access is forcibly prohibited.
After that, after 2 to 48 cycles, NPW48, NMA24
When both become 1, refresh is activated. As described above, according to the present invention, the degree of influence on the processor when refreshing is activated once is large, but the number of refresh operations is decreased, so that the overall negative effect is small. This is particularly effective in systems such as vector processors, which are likely to constantly access main memory. In addition, in vector processors, the number of interleaves is set to a large value in order to improve the throughput of access to the main memory, but according to the present invention, refresh is performed regardless of the number of interleaves, so there is no negative effect due to an increase in the number of interleaves. . In addition, as explained in FIGS. 2 and 3, the memory access state is detected, the refresh cycle is divided into three periods A, B, and C, and the access prohibition time is set according to the elapsed time and the memory access state. Since the refresh activation is controlled without using the refresh function, the time during which memory access is inhibited is shortened, and performance can be improved.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing one embodiment of the present invention, and FIG.
The figure is a block diagram of the time monitoring circuit, and FIG. 3 is an explanatory diagram showing the refresh activation algorithm. In the figure, MS is main memory and IL is interleave.

Claims (1)

[Scope of Claims] 1. In a main memory refresh control method of a system in which a main memory constituted by dynamic random access memory elements is divided into a plurality of interleaves and each interleave can be accessed independently, All interleaves are accessed simultaneously to refresh the cells in each memory element line by line, and the corresponding line is refreshed once within a certain refresh period assigned to each line, and further, a first time monitoring means for determining that a memory access requiring a predetermined first number of cycles has not been performed during the cycle; A second time monitoring means is provided for determining whether a required memory access has not been performed during the second cycle, the refresh cycle is divided into three periods, and the priority of the refresh with respect to the normal memory access is determined. A priority is set for each of the three divided periods, and in the first period of the three divided periods, priority is given to accessing the memory, and the first time monitoring means and the second time monitoring means are The time monitoring means performs a refresh when each determines that no access has been made, and the first time monitoring means or the second time monitoring means performs a refresh in the second period of the three divided periods. When one of them detects that no access is being made, access to the memory is prohibited, and thereafter the first time monitoring means and the second time monitoring means each determine that no access is made. The refresh is performed when it is determined, and in the third and final period of the three divided periods, both the first time monitoring means and the second time monitoring means are accessed in the second period. when the first time monitoring means and the second time monitoring means each determine that no access has been made, prohibit access to the memory, and refresh the memory when it is determined that no access has been made, A main memory refresh control method characterized in that the optimum refresh timing within the refresh cycle is determined by setting the priority of refresh over normal memory access low at the beginning of the refresh cycle and increasing toward the end.