SU792290A1

SU792290A1 - Device for control of regeneration of information in dynamic memory units

Info

Publication number: SU792290A1
Application number: SU782596728A
Authority: SU
Inventors: Игорь Сергеевич Колтыпин; Михаил Вячеславович Шацкий
Original assignee: Предприятие П/Я Г-4128
Priority date: 1978-03-30
Filing date: 1978-03-30
Publication date: 1980-12-30

Description

Изобретение относится к вычислительной технике и предназначено для использования в полупроводниковых запоминающих устройствах с динамическими запоминающими элементами.The invention relates to computer technology and is intended for use in semiconductor memory devices with dynamic memory elements.

Одно из известных устройств для управления регенерацией информации в динамической памяти использует., особенность этой памяти, заключающуюся в том, что все ячейки выбранной строки автоматически регенерируются при любом обращении к строке. 'One of the known devices for controlling the regeneration of information in dynamic memory uses., A feature of this memory, which is that all cells of the selected row are automatically regenerated upon any access to the row. ''

Устройство содержит селектор адресов строк, счетчик, индикатор регенерации и блок управления; пропускается очередная регенерация информации в строке в том случае, если перед запросом на регенерацию к этой строке было ’ обращение в течение интервала 7 - , гдеThe device contains a line address selector, counter, regeneration indicator and control unit; the next information regeneration in the line is skipped if, before the request for regeneration, this line was ’accessed during interval 7 -, where

Т_Хр — допустимый период хранения информации между очередными регенерациями; R — количество строк в памяти [1]. ;T _X p - the permissible period of storage of information between successive regenerations; R is the number of lines in memory [1]. ;

Наиболее близким по технической сущности к изобретению является устройство, в котором отменяется очередная регенерация, если зафикси2 ровано обращение к строке в течение интервала времени*Τ_χρ/2 Оно содержит селектор адреса строки, выходы которого подключены ко входам дешифратора адреса строки, выходы которого подсоединены ко входам установки в ”0” элементов памяти, выходы которых подключены к первым входам соответствующих элементов И и к элементу ИЛИ, выход которого подключен ко входу блока управления, и сигнализирует о наличии строк динамической памяти, подлежащих регенерации. Входы установки ”1” всех элементов памяти объединены и соединены с выходом ’’Сброс” блока управления [2].The closest in technical essence to the invention is a device in which the next regeneration is canceled if an access to the line is fixed during the time interval * Τ _χ ρ / 2 It contains a line address selector, the outputs of which are connected to the inputs of the line address decoder, the outputs of which are connected to the installation inputs to ”0” memory elements, the outputs of which are connected to the first inputs of the corresponding AND elements and to the OR element, the output of which is connected to the input of the control unit, and signals the presence of lines dynamic memory to be regenerated. The setting inputs “1” of all memory elements are combined and connected to the “Reset” output of the control unit [2].

Недостатки этого устройства, снижающие его быстродействие, следующие: период принудительной регенерации каждой строки равен З’кр/Й ,что приводит к избыточным циклам регенерации; обращения к ЗУ запрещаются во время опроса элементов памяти.The disadvantages of this device, reducing its performance, are as follows: the period of forced regeneration of each line is equal to Z'kr / Y, which leads to excessive regeneration cycles; access to the memory is prohibited during the interrogation of memory elements.

Целью изобретения является повышение бы стродействия устройства для управления регенерацией в динамической памяти.The aim of the invention is to increase the speed of the device for controlling regeneration in dynamic memory.

Поставленная цель достигается тем, что в устройстве для управления регенерацией информации в блоках динамической памяти, содержащем первый блок адреса строки, первый вход которого подключен к адресным $ шинам, а второй - к первому выходу блока управления, второй выход которого соединен с первыми входами элементов памяти, выходы которых подключены соответственно к первым входам первых элементов И, выходы которых ю через элемент ИЛИ соединены с входом блока управления, и дешифратор адреса строки, введены вторые элементы И, второй блок адреса строки и счетчик адреса строки, соединенный с блоком управления и третьими входами бло- 15 ков адреса строки, первый и второй входы второго блока адреса строки соединены соответственно с выходом первого блока адреса строки и третьим выходом блока управления, а выход через дешифратор адреса строки — со 20 вторыми входами первых и вторых элементов И, первые входы вторых элементов И подключены к четвертому выходу блока управления, выходы вторых элементов И соединены соответственно со вторыми входами элементов 25 памяти.This goal is achieved by the fact that in the device for controlling the regeneration of information in blocks of dynamic memory containing the first block of the line address, the first input of which is connected to the address bus, and the second to the first output of the control unit, the second output of which is connected to the first inputs of memory elements the outputs of which are connected respectively to the first inputs of the first AND elements, the outputs of which through the OR element are connected to the input of the control unit, and a line address decoder, the second AND elements are entered, the second block is the address and the line and the line address counter connected to the control unit and the third inputs of the line address block 15, the first and second inputs of the second line address block are connected respectively to the output of the first line address block and the third output of the control unit, and the output through the line address decoder is with 20 second inputs of the first and second elements AND, the first inputs of the second elements AND are connected to the fourth output of the control unit, the outputs of the second elements AND are connected respectively to the second inputs of the memory elements 25.

На чертеже представлена блок-схема устройства.The drawing shows a block diagram of a device.

Предлагаемое устройство содержит блок 1 управления, счетчик 2 адресов строк, первый 30 блок 3 адреса строки, второй блок 4 адреса строки, дешифратор 5 адреса строки, первые элементы И 6, элементы 7 памяти, вторые элементы И 8, элемент ИЛИ 9, шины 10 адреса. 35The proposed device contains a control unit 1, a counter 2 line addresses, a first 30 block 3 line addresses, a second block 4 line addresses, a decoder 5 line addresses, the first elements AND 6, memory elements 7, second elements AND 8, element OR 9, bus 10 addresses. 35

По способу организации логических связей элементы 7 памяти являются D-триггерами.By the method of organizing logical connections, memory elements 7 are D-triggers.

Устройство для управления регенерацией посылает в процессор сигналы требования на цикл регенерации и принимает сигналы вы- 40 полнения циклов обращения в ЗУ.The device for controlling the regeneration sends to the processor signals of the demand for the regeneration cycle and receives signals for completing circulation cycles in the memory.

При отсутствии обращений к ЗУ и когда нет сигналов запроса периодической регенерации, вырабатываемых блоком 1 управления с частотой 2R блок управления держит на 45 первых входах вторых элементов И 8 уровень ”0”, запрещая прием информации в элементы 7 памяти.In the absence of accesses to the memory and when there are no signals of the request for periodic regeneration generated by the control unit 1 with a frequency of 2R, the control unit holds at the first 45 inputs of the second elements AND the 8 level is “0”, prohibiting the reception of information in the memory elements 7.

При каждом обращении к ЗУ и отсутствии ₅θ сигналов запроса регенерации блок 1 управления устанавливает на управляющих входах блоков 3 и 4 логические уровни, подключающие шины 10 адреса к соответствующим адресным входам ЗУ и ко входам дешифратора 5. При этом код _5Jадреса подается через первый блок 3 адреса строки и через второй блок 4 адреса строки на входы дешифратора 5 адреса строки. На информационные входы элементов 7 памяти и на первые входы вторых элементов И 8 с соответствующих выходов блока управления подается ”1” и таким образом происходит запись ”1” в элемент 7 памяти, адрес которого соответствует выбранной строке.Each time the memory is accessed and there are no ₅ θ regeneration request signals, the control unit 1 sets the logic levels at the control inputs of blocks 3 and 4 that connect the address buses 10 to the corresponding address inputs of the memory and to the inputs of the decoder 5. In this case, the address code _5J is supplied through the first block 3 line addresses and through the second block 4 line addresses to the inputs of the decoder 5 line addresses. On the information inputs of the memory elements 7 and on the first inputs of the second elements And 8 from the corresponding outputs of the control unit is fed “1” and thus the record “1” in the memory element 7, the address of which corresponds to the selected line.

Состояние счетчика 2 адреса строк меняется с частотой по сигналам блока 1 управления. С этой же частотой в конце каждого интервала состояния счетчика 2 блок управ¹; ления вырабатывает сигнал запроса периодической регенерации, по которому на вторых входах вторых элементов И 8 устанавливается ”0”, запрещая прием информации в элементы 7 памяти, а на управляющем входе второго блока 4 адреса строки устанавливается логический уровень, коммутирующий адрес, содержащийся в счетчике 2, на входы дешифратора 5 адреса строки через второй блок 4 адреса строки. Если при этом из адресуемого элемента 7 памяти через соответствующий элемент Иби элемент ИЛИ 9 на вход блока 1 управления поступает ”1”, то блок управления не возбуждает требования регенерации, а проводит запись ”0” в тот же элемент памяти, для чего на первых входах вторых элементов И 8 устанавливается уровень ”1”, а на информационных входах элементов 7 памяти ”0”.The status of the counter 2 of the line address changes with frequency according to the signals of the control unit 1. With the same frequency, at the end of each interval of the status of counter 2, control unit ¹ ; the line generates a request signal for periodic regeneration, according to which on the second inputs of the second elements And 8 is set to “0”, prohibiting the reception of information in the elements 7 of the memory, and at the control input of the second block 4 of the line address is set to a logical level, the switching address contained in the counter 2, to the inputs of the decoder 5 addresses of the line through the second block 4 of the address of the line. If at the same time “1” is received from the addressed memory element 7 through the corresponding Ibi element OR 9 to the input of the control unit 1, the control unit does not initiate regeneration requirements, but writes “0” to the same memory element, for which purpose at the first inputs of the second elements And 8 the level is set to “1”, and at the information inputs of the elements 7 of the memory is “0”.

При выполнении обращений к памяти во время действия сигнала запроса регенерации кодовые шины JO адреса подключаются к соответствующим адресным входам ЗУ через, блок 3.When performing memory accesses during the operation of the regeneration request signal, the code bus JO addresses are connected to the corresponding address inputs of the memory through block 3.

Если же при запросе регенерации из адресуемого элемента 7 памяти на вход блока 1 управления поступает ”0”, то воздужается требование цикла регенерации, запрещающее обращение к ЗУ. В этом случае на выходы блоков 3 и 4 с выходов счетчика 2 коммутируется адрес строки, подлежащей принудительной регенерации, путем подачи соответствующих логических уровней из блока управления на управляющие входы этих селекторов. Одновременно с циклом регенерации проводится запись ”1” в адресуемый элемент 7 памяти таким же образом, как и при обычном обращении к ЗУ.If, when requesting regeneration, “0” is received from the addressable memory element 7 at the input of control unit 1, then the requirement of the regeneration cycle is forbidden, which prohibits access to the memory. In this case, at the outputs of blocks 3 and 4 from the outputs of counter 2, the address of the line to be forced regenerated is switched by supplying the corresponding logic levels from the control unit to the control inputs of these selectors. Simultaneously with the regeneration cycle, “1” is written to the addressable memory element 7 in the same way as during normal access to the memory.

После включения устройства, когда элементы 7 памяти могут находиться в произвольных состояниях, при работающем блоке управления во всех строках ЗУ будет проведена регенерация через Т_Хр.After the device is turned on, when the memory elements 7 can be in arbitrary states, when the control unit is working, regeneration will be carried out in all lines of the memory through T _X p.

Как видно из изложения принципа функционирования устройства, факт обращений к каждой строке фиксируется соответствующим элементом 7 памяти в течение интервала Т_Хр/2 между очередными запросами на регенерацию этой строки.As can be seen from the description of the principle of operation of the device, the fact of accesses to each row is fixed by the corresponding memory element 7 during the interval T _X p / 2 between successive requests for regeneration of this row.

Если обращения к данной строке отсутствуют в течение интервала Т_Хр^после принудитель-. ной регенерации этой строки, то при очередном запросе на регенерацию будет произведена запись ”0” в соответствующий элемент па- ₅мята без проведения цикла регенерации и только через два интервала т.е. с частотой 1/Т_Хр .будет производиться регенерация с установкой элемента памяти в ”1”.If access to this line is absent during the interval T _X p ^ after forced-. hydrochloric regeneration of this row, then the next request for regeneration be recorded is "0" in the corresponding element of _PA-5 mint without regeneration cycle and only after two intervals i.e. with a frequency of 1 / T _X r. regeneration will be carried out with the memory element set to “1”.

Таким образом, предлагаемое устройство име-ю ет следующие характеристики:Thus, the proposed device has the following characteristics:

период принудительной регенерации равен Т_хр; во время действия сигнала запроса на регенерацию выполнение очередного обращения к ЗУ не запрещается; 15 принуда гельная регенерация строки не производится, если к ней было обращение в течение Т_Хр/2 перед запросом на регенерацию.the period of forced regeneration is equal to T _x p; during the action of the signal of the request for regeneration, the next call to the memory is not prohibited; 15, gel gel regeneration of a row is not performed if it was accessed during T _X p / 2 before a request for regeneration.

В предлагаемом устройстве по сравнению с известным понижается частота циклов при- 20 нудительной регенерации и не запрещается выполнение циклов обращений к ЗУ во время действия сигналов запроса на регенерацию, в результате чего повышается быстродействие устройства. Из сравнения с характеристиками 25 известного устройства следует, что затраты времени на управление регенерацией информации с помощью данного устройства, даже без учета выполнения им запросов на регенерацию параллельно с обращениями процессора, зо вдвое меньше, чем в известном устройстве.In the proposed device, compared with the known one, the frequency of forced regeneration cycles is reduced and the cycles of accessing the memory during the action of the regeneration request signals are not prohibited, as a result of which the speed of the device is increased. From a comparison with the characteristics 25 of the known device, it follows that the time spent on managing the regeneration of information using this device, even without taking into account the fulfillment of requests for regeneration in parallel with the processor accesses, is half as much as in the known device.

Повышенное быстродействие предлагаемого устройства позволяет увеличить время доступности запоминающего устройства для процессора и, следовательно, производительность ЭВМ. ³⁵ The increased performance of the proposed device allows to increase the availability time of the storage device for the processor and, therefore, the performance of the computer. ³⁵

Claims

(54) DEVICE FOR CONTROL OF INFORMATION REGENERATION IN DYNAMIC COTS UNITS The invention relates to computer technology and is intended for use in semiconductor memory devices with dynamic storage elements. One of the known devices for controlling the regeneration of information in a dynamic memory uses., A feature of this memory, which consists in the fact that all cells of the selected row are automatically regenerated at any access to the row. The device contains a row address selector counter, a regeneration indicator and a control unit; the next regeneration of information in the row is skipped if, prior to the request for regeneration, this line was addressed during interval 1 -, where Txp is the allowable period of information storage between successive regenerations; R is the number of lines in the memory 1. The closest in technical essence to the invention is a device in which the next regeneration is canceled, if a row is recorded during a time interval Tj (p / 2 It contains the row address selector which outputs are connected to the inputs of the addressframer of the row whose outputs are connected to the inputs of the installation in memory elements O whose outputs are connected to the first inputs of the corresponding AND elements and to the OR element whose output is connected to the input of the control unit and the signal It detects the presence of dynamic memory strings to be regenerated. The installation inputs 1 of all memory elements are combined and connected to the output Reset of control unit 2. The disadvantages of this device, reducing its speed, are the following: the period of forced regeneration of each line is equal, which leads to redundant cycles regeneration; access to memory is prohibited during the interrogation of memory elements. The aim of the invention is to increase the responsiveness of the device to control the regeneration in the dynamic memory. The goal is achieved by the fact that in the device for controlling the regeneration of information in the blocks of dynamic memory containing the first block of the row address, the first input of which is connected to the address spikes, and the second to the first output of the control unit, the second output of which is connected to the first inputs of the memory elements These outputs, whose outputs are connected respectively to the first inputs of the first AND elements, whose outputs through the OR element are connected to the input of the control unit, and the address address decoder, entered the second AND elements, the second address block the row and row address counters connected to the control unit and the third inputs of the row address blocks, the first and second inputs of the second address block of the row are connected respectively to the output of the first address block of the line and the third output of the control unit, and the output via the row address decoder to the second inputs of the first and the second And elements, the first inputs of the second And elements are connected to the fourth output of the control unit, the outputs of the second And elements are connected respectively to the second inputs of the memory elements. The drawing shows the block diagram of the device. The proposed device contains a control unit 1, a row address address counter 2, a first row address block 3, a second row address block 4, a row address decoder 5, first AND elements 6, memory 7 elements, second AND elements 8, OR element 9, tires 10 addresses. According to the method of organizing logical connections, the memory elements 7 are D-triggers. The device for controlling the regeneration sends to the processor the signals of the request for the regeneration cycle and receives signals for the execution of Gain 1 cells in the memory. In the absence of calls to the memory and when there are no periodic regeneration request signals generated by the control unit 1 with a frequency of 2R, the control unit holds the first inputs of the second elements AND 8 level O, preventing the reception of information in the memory elements 7. With each call to the memory and no regeneration request signals, the control unit 1 sets the control levels of blocks 3 and 4 to logic levels connecting the address buses 10 to the corresponding memory address inputs and to the decoder inputs 5. In this case, the address code is fed through the first address block 3 line and through the second block 4 address line to the inputs of the decoder 5 address line. The information inputs of the memory elements 7 and 4 are fed to the first inputs of the second elements AND 8 from the corresponding outputs of the control unit 1, and thus writing 1 to the memory element 7 occurs, the address of which corresponds to the selected line. The state of the counter 2 row addresses varies with the frequency of the signals of block 1 control. With the same frequency, at the end of each interval of the state of the counter 2, the control unit generates a periodic regeneration request signal, according to which, at the second inputs of the second elements 8, O is set to prohibit reception of information into the memory elements 7, and at the control input of the second block 4 the address of the string is set; the logic level, the switching address contained in the counter 2, is sent to the inputs of the decoder 5 of the address of the string through the second block 4 of the address of the string. If at the same time from the addressed memory element 7 through the corresponding element AND 6 and the element OR 9, 1 arrives at the input of the control unit 1, the control unit does not raise the regeneration requirement, but writes O into the same memory element, for which the first inputs the second elements And 8 are set to level 1, and on the information inputs of the memory 7 elements O. When making memory accesses during the regeneration request signal, the code buses JO addresses are connected to the corresponding address inputs of the charger via block 3. If, when prompted, p If the regeneration from the addressable memory element 7 is sent to the input of the control unit 1, the regeneration cycle requirement is raised, prohibiting access to the memory. In this case, the outputs of blocks 3 and 4 from the outputs of counter 2 are switched to the address of the line to be forced regeneration, by applying the appropriate logic levels from the control unit to the control inputs of these selectors. Simultaneously with the regeneration cycle, recording 1 is performed in the addressable memory element 7 in the same manner as in the normal access to the memory. After turning on the device, when the memory elements 7 can be in arbitrary states, with the control unit running, all lines of the memory will be regenerated through Txp. As can be seen from the presentation of the principle of operation of the device, the fact that each line is accessed is recorded by the corresponding memory element 7 during the interval Txp / 2 between the successive requests for regeneration of this line. 57 ficjiH references to this line are absent during the interval Txp after the forced regeneration of this line, then the next request for regeneration will record O into the corresponding memory element without performing the regeneration cycle and only after two intervals with a frequency of 1 / Txp, the regeneration will be performed with the memory element set to 1. Thus, the proposed device has the following characteristics: the period of forced regeneration is equal to T during the effect of the regeneration request signal performed during the next access to the memory is not prohibited; Forced line regeneration is not performed if it was accessed within Txp / 2 before the request for regeneration. In the proposed device, as compared with the known, the frequency of the forced regeneration cycles decreases, and the execution of the memory access cycles during the action of the regeneration request signals is not prohibited, as a result of which the device speed increases. From a comparison with the characteristics of a known device, it follows that the time spent on managing the regeneration of rsformation using this device, even without taking into account the fulfillment of regeneration requests by it in parallel with the processor calls, is half the size of the known device. The increased speed of the proposed device allows to increase the availability time of the storage device for the processor and, consequently, the performance of the computer. The invention is a device for controlling information regeneration in dynamic memory blocks, containing a first block of a row address, the first input of which is connected to address buses, and the second is connected to the first output of a control unit, the second output of which is connected to the first inputs of memory elements whose outputs are connected respectively, to the first inputs of the first AND elements, the outputs of which through the OR element are connected to the input of the control unit, and the decoder of the row address, which is characterized by the fact that, in order to increase the speed of the device, It contains the second elements AND, the second block of the row address and the counter of the row address connected to the control unit and the third inputs of the block of the address line, the first and second inputs of the second block of the row address are connected to the output of the first block of the line address and the third output of the control block and the output through the descriptor of the row address is connected to the second inputs of the first and second elements AND, the first inputs of the second elements AND are connected to the fourth output of the control unit, the outputs of the second elements AND are connected respectively to the second inputs of memory elements. Sources of information taken into account in the examination 1. US patent number 3760379, cl. 340-173, 1973.

2. USSR author's certificate №514346, cl. Q And C 21/00, 1976 (prototype).

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