KR20230082529A - Memory device reducing power noise in refresh operation and Operating Method thereof - Google Patents

Abstract

A memory device reducing power noise in a refresh operation and an operating method thereof are disclosed. According to one aspect of the technical idea of the present disclosure, a method of operating a memory device performs a first normal refresh process of simultaneously refreshing N word lines among a plurality of word lines at a first refresh timing in response to reception of a first refresh command. and, at a second refresh timing in response to receiving the first refresh command, performing a first target refresh on a first weak word line adjacent to the largest active word line among the plurality of word lines. performing a second normal refresh for simultaneously refreshing the other N word lines among the plurality of word lines at a first refresh timing in response to reception of a second refresh command; and performing a second target refresh on a second weak word line adjacent to the maximum active word line at a second refresh timing in response to reception of a command.

Description

Memory device reducing power noise in refresh operation and operating method thereof

The technical idea of the present disclosure relates to a memory device and an operating method thereof, and more particularly, to a memory device reducing power noise in a refresh operation and an operating method thereof.

Memory devices widely used in high-performance electronic systems are increasing in density and speed. When the access frequency of specific memory cells increases in a memory device such as DRAM (Dynamic Random Access Memory), adjacent memory cells are stressed, and data retention characteristics of adjacent memory cells are deteriorated accordingly, resulting in deterioration in data reliability. it gets lower For example, when a specific word line is intensively active, data retrieval characteristics of memory cells connected to one or more word lines located adjacent to the specific word line may deteriorate. Target refresh may be performed for the word line to be refreshed.

However, as the degree of integration of the memory device increases, the number of word lines to be refreshed increases. There is a limit to the number of refresh execution timings within the refresh cycle required by the DRAM specification. Since it needs to be additionally performed, a large number of word lines may be simultaneously refreshed in a specific time period, and in this case, there is a problem in that power noise may increase.

An object to be solved by the technical idea of the present invention is to provide a memory device capable of reducing power noise by optimally performing normal refresh and target refresh for a plurality of word lines and an operating method thereof.

In order to achieve the above object, a method of operating a memory device according to an aspect of the present disclosure includes N words among a plurality of word lines at a first refresh timing in response to reception of a first refresh command. Performing a first normal refresh for simultaneously refreshing lines, and at a second refresh timing in response to reception of the first refresh command, a first normal refresh adjacent to a maximum active word line activated the most among the plurality of word lines. Performing a first target refresh on a weak word line, and performing a second normal refresh to simultaneously refresh other N word lines among the plurality of word lines at a first refresh timing in response to reception of a second refresh command. and performing a second target refresh on a second weak word line adjacent to the maximum active word line at a second refresh timing in response to receiving the second refresh command. .

Meanwhile, a memory device according to one aspect of the technical concept of the present disclosure controls a memory cell array including a plurality of word lines, a refresh operation for the plurality of word lines, and normal refresh of the plurality of word lines. a refresh controller that schedules an operation and a target refresh operation and a control logic that determines at least one weak word line on which the target refresh is to be performed based on counting the number of active times of the plurality of word lines; The controller performs scheduling so that the normal refresh operation and the target refresh operation are performed together during a refresh period defined in response to reception of one refresh command, and during the refresh period, word lines are simultaneously refreshed in the normal refresh operation. The number of s is greater than the number of word lines refreshed in the target refresh operation.

Meanwhile, a memory system according to one aspect of the technical concept of the present disclosure may include a memory cell array including a plurality of word lines; and a refresh controller that controls refresh operations for the plurality of word lines and schedules normal refresh operations for the plurality of word lines and target refresh operations for weak word lines, and commands for the memory device. and a memory controller controlling access to the memory device by providing an address, wherein the memory device performs the normal refresh operation and the The target refresh operation is performed simultaneously, and the number of word lines simultaneously refreshed in the normal refresh operation during the refresh interval is greater than the number of word lines refreshed in the target refresh operation.

According to the memory device and its operating method of the inventive concept, it is possible to reduce power noise that may occur when a large number of word lines are refreshed in a relatively short period of time.

In addition, according to the memory device and its operating method according to the technical idea of the present invention, since target refresh is performed on a weak word line with a high possibility of data loss, an effect of improving data reliability while minimizing an increase in power noise is obtained. there is.

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.
2 is a diagram illustrating an example of a weak word line on which target refresh is performed.
3 is a diagram schematically illustrating a 2 series refresh according to an exemplary embodiment of the present disclosure.
4 is a diagram illustrating an example of a refresh operation according to an exemplary embodiment of the present disclosure.
5 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present disclosure.
6 is a diagram illustrating an example of a refresh operation in any one bank (BANK) according to an exemplary embodiment of the present disclosure.
7 is a block diagram illustrating a specific implementation example of a memory device according to an exemplary embodiment of the present disclosure.
8 is a diagram illustrating an example of a refresh operation of a memory device according to various embodiments of the present disclosure.
9 is a diagram illustrating an example of a refresh operation of a memory device according to another exemplary embodiment of the present disclosure.
10 is a flowchart illustrating a method of operating a memory system including a memory device of the present disclosure.
11 is a block diagram illustrating a memory system of an exemplary embodiment of the present disclosure.
12 is a diagram illustrating an operation example of a memory device according to another exemplary embodiment of the present disclosure.
13 is a block diagram illustrating a data center including a system according to an exemplary embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , a memory system 10 may include a memory controller 100 and a memory device 200 . The memory device 200 may include a memory cell array 210 , a refresh controller 220 and a control logic 230 . In addition, according to an exemplary embodiment of the present disclosure, the control logic 230 may include a weak wordline determiner 231 . The control logic 230 may further include other components for controlling a memory operation in addition to the weak word line determiner 231 . That is, the control logic 230 may be defined as a concept including various types of elements within the memory device 200 .

The memory controller 100 provides various signals to the memory device 200 through an interface circuit (not shown) to control memory operations such as writing and reading. For example, the memory controller 100 may access the data DATA of the memory cell array 210 by providing the command CMD and the address ADD to the memory device 200 . The command CMD may include commands for normal memory operations such as writing and reading data. Also, when the memory device 200 includes dynamic random access memory (DRAM) cells, the command CMD may include various operations inherent to the DRAM, such as a refresh command for refreshing memory cells.

The memory controller 100 may access the memory device 200 according to a request from the host (HOST). The memory controller 100 may communicate with the host HOST using various protocols. The memory cell array 210 may include a plurality of memory cells. For example, the memory cell array 210 may include a plurality of word lines, and a plurality of memory cells may be connected to each word line. As an example, memory cells connected to one word line may be referred to as a row. That is, the memory cell array 210 may include a plurality of rows. In describing exemplary embodiments of the present disclosure, performing a refresh of a word line may mean performing a refresh of memory cells (or rows) connected to one word line, and accordingly, word Phrases such as refresh for lines and refresh for rows may be used interchangeably.

Meanwhile, according to an exemplary embodiment of the present disclosure, when one word line is intensively or frequently activated (or accessed), a word line (hereinafter referred to as a weak word) adjacent to the intensively activated word line Lines) are subjected to electromagnetic interference, and in particular, as the degree of integration of the memory device 200 increases, the degree of interference received by the weak word line may increase. Accordingly, the possibility of flipping the data of memory cells connected to the weak word line increases, and in order to ensure reliability of data in response to the above phenomenon, the weak word line A target refresh may be performed for

In addition, a plurality of word lines in the memory cell array 210 may have a structure in which they are arranged side by side, and two word lines located adjacent to both sides of the intensively accessed word line may correspond to the weak word line. can Alternatively, in an exemplary embodiment, as at least two word lines adjacent to one side of the intensively accessed word line correspond to the above-mentioned weak word line, three or more weak word lines are associated with the intensively accessed word line. This may be judged.

Meanwhile, the refresh controller 220 may refresh word lines (or rows) of the memory cell array 210 in response to a refresh command from the memory controller 100 . Alternatively, the refresh controller 220 may refresh the word lines of the memory cell array 210 without intervention of the memory controller 100 in the self refresh mode. Also, according to an embodiment, when a specific word line is intensively accessed, the refresh controller 220 may target one or more weak wordlines adjacent to the intensively accessed wordline based on control of the control logic 230. The refresh operation can be controlled.

In an exemplary embodiment, the weak word line determiner 231 may determine the most active word line for a predetermined period based on the result of determining the number of actives for a plurality of word lines, and may determine the most active word line. Positions of one or more weak word lines adjacent to the given word line may be determined. Also, information related to the determined weak word lines may be provided to the refresh controller 220 . However, embodiments of the present disclosure are not necessarily limited thereto, and components for determining a weak word line may be implemented in various ways within the memory device 200. For example, components for determining a weak word line may include control logic (230) may be implemented externally.

According to an exemplary embodiment of the present disclosure, the refresh controller 220 may control a normal refresh operation and a target refresh operation. For example, the command CMD from the memory controller 100 may include a refresh command, and the refresh controller 220 may selectively perform a normal refresh operation and a target refresh operation in response to the refresh command. For example, the refresh controller 220 may include a scheduler 221, and the scheduler 221 may perform scheduling of a normal refresh operation and a target refresh operation.

According to an exemplary embodiment of the present disclosure, the memory device 200 may perform at least two refresh operations in response to one refresh command from the memory controller 100 . For example, when each refresh operation is performed at N timings in response to one refresh command, this may be referred to as an N-series refresh. For example, a temporal interval (eg, a refresh interval) in which refresh is performed in response to one refresh command may be defined as a parameter tRFC, and N refresh operations may be sequentially performed within the refresh interval tRFC. In addition, all word lines of the memory device 200 need to be refreshed at least once within a predetermined refresh cycle, and an interval at which a refresh command is received from the memory controller 100 (eg, a refresh reception interval) is set to the parameter tREFI. can be defined

When multiple word lines are refreshed at the same time or when refresh operations on many word lines are concentrated during a short period of time, power noise may increase and this may cause data reliability to deteriorate. However, in an exemplary embodiment of the present disclosure, According to this, a scheduling operation can be performed so that the normal refresh operation and the target refresh operation can be performed at an appropriate timing, and thus power noise can be reduced. For example, when the memory device 200 performs N-series refresh, a normal refresh operation is performed at some refresh timings in response to one refresh command based on the above-described scheduling operation, and a target refresh operation is performed at other refresh timings. A refresh operation may be performed.

In order to improve data retention characteristics in the memory device 200, a refresh cycle having a predetermined time is set, and as the degree of integration of the memory device 200 increases, the number of word lines included in the memory cell array 210 increases. In this case, a plurality of word lines can be normally refreshed at the same time at one refresh timing. On the other hand, in the case of a target refresh operation, since refresh is selectively performed on one or two weak word lines adjacent to any one word line, one or a relatively small number of word lines can be refreshed at one refresh timing. . In the embodiment of the present disclosure, since normal refresh and target refresh are performed together during one refresh period (tRFC), as normal refresh operations are continuously performed during one refresh period (tRFC), a large number of The case where word lines are refreshed can be reduced or prevented, and thus power noise can be reduced.

Meanwhile, in the above-described embodiment, it has been described that the criterion for determining a weak word line includes an operation of determining a word line that is most active in a predetermined period, but embodiments of the present disclosure do not need to be limited thereto. A weak word line may be determined according to various criteria. As an example, a word line continuously active beyond a predetermined reference value is determined, and one or more word lines adjacent to the word line continuously active are determined as described above. It may be determined as a weak word line.

On the other hand, the refresh controller 220 includes a counter (not shown) generating an address (eg, normal address) for indicating a word line on which normal refresh is to be performed therein, and the scheduler 221 includes the normal address along with the counter. An address (eg, a target address) indicating a weak word line on which a target refresh is to be performed may be received from the control logic 230 . Also, based on the control of the control logic 230, the scheduler 221 may output a normal refresh at a timing at which a normal refresh is to be performed, and output a target refresh at a timing at which a target refresh is to be performed.

As the target refresh for the weak word line is performed, the number of normal refresh timings within one refresh period decreases, and accordingly, a large number of word lines are generated during a predetermined time interval (eg, short time interval). As normal refresh is performed, power noise may increase. According to the embodiment of the present disclosure as described above, it is possible to reduce the case where a large number of word lines are refreshed within a short time period, and to respond to power noise, data reliability can be effectively improved.

Meanwhile, the memory device 200 includes DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, RDRAM (Rambus Dynamic Random Access Memory), and the like. It may be a dynamic random access memory. However, the embodiments of the present disclosure need not be limited thereto, and as an example, nonvolatile memories such as MRAM (Magnetic RAM), FeRAM (Ferroelectric RAM), PRAM (Phase change RAM) and ReRAM (Resistive RAM), refresh Embodiments of the present disclosure may be applied to a memory device that performs a data retention operation corresponding to .

Meanwhile, the memory device 200 may be a single memory chip or a semiconductor package including two or more memory chips. Alternatively, the memory device 200 may be a memory module in which a plurality of memory chips are mounted on a module board. Alternatively, although the memory controller 100 and the memory device 200 are shown as separate configurations in FIG. 1 , the memory device 200 of the present disclosure has a memory control function and a memory cell array integrated into a single semiconductor package. It may be implemented as a memory system.

2 is a diagram illustrating an example of a weak word line on which target refresh is performed.

Referring to FIG. 2 , the memory cell array 210 includes a plurality of word lines WL1 to WLm, and among the plurality of word lines WL1 to WLm, the most active word line is selected according to a predetermined period. can be judged Assuming that the k th word line WLk is the most active word line, at least one word line adjacent to the k th word line may be greatly affected by electromagnetic interference, and accordingly, the at least one adjacent word line may correspond to a weak word line.

Weak word lines may be positioned on both sides of the k th word line WLk as a reference. For example, a weak word line positioned on one side of the k th word line WLk is a first weak word line (weak WL 1), and a weak word line positioned on the other side may be referred to as a second weak word line (weak WL 2 ). In an exemplary embodiment, one word line located on one side of the k th word line WLk may be determined as a weak word line. In this case, the first weak word line WL 1 is one weak word line. It may contain word lines. Alternatively, two or more word lines located on one side may be determined as a weak word line, and in this case, the first weak word line (weak WL 1) may include two or more word lines.

In an exemplary embodiment, target refresh may be performed for one word line at one refresh timing. Also, when N refreshes are performed in response to one refresh command from the memory controller (N is an integer greater than or equal to 2), some of the N refreshes may correspond to target refreshes. Accordingly, the case where normal refresh is continuously performed in response to one refresh command can be prevented or reduced, and power noise can be reduced by preventing a large number of word lines from being intensively refreshed for a short period of time. can

3 is a diagram schematically illustrating a 2 series refresh according to an exemplary embodiment of the present disclosure.

Referring to FIG. 3, a plurality of refresh commands may be provided from a memory controller to a memory device within one refresh cycle, and a refresh period (tRFC) as various parameters defined in the DRAM specification is a memory device in response to one refresh command. It may correspond to a time period in which refresh is performed in the device, and when two refresh operations are performed as there are two refresh timings during one refresh period (tRFC), the memory device performs a 2 series refresh operation. It can be referred to as doing. For example, whenever a refresh command is received from the memory controller, the memory device may determine two arbitrary times at which refresh is to be performed within a refresh interval (tRFC) defined as a predetermined parameter, and It may include components such as a counter circuit.

In an exemplary embodiment, the memory device of the present disclosure may simultaneously perform multiple types of refresh operations within one refresh period (tRFC). For example, the refresh operation may include a normal refresh operation sequentially performed on a plurality of word lines and a target refresh operation selectively performed on specific word lines. In addition, during a manufacturing process or a test process of a memory device, information on word lines having relatively low data retention characteristics may be pre-stored in a memory system, and the refresh operation may be performed to refresh word lines having low characteristics (eg, defective data retention characteristics). It may be referred to as care refresh for the word line) operation may be further included. For example, the memory device of the present disclosure may simultaneously perform at least two types of refresh operations among the various types of refresh operations described above within one refresh period tRFC.

In an exemplary embodiment, when a memory device performs a 2-series refresh operation, a normal refresh and a target refresh may be performed together in response to one refresh command from the memory controller. Alternatively, in an exemplary embodiment, the memory device may perform both normal refresh and care refresh in response to one refresh command from the memory controller. In addition, the memory device may perform other various types of refresh operations, and at least two types of refresh operations selected from among various types of refresh operations may be performed together in one refresh period tRFC.

4 is a diagram illustrating an example of a refresh operation according to an exemplary embodiment of the present disclosure.

The number of word lines included in the memory device may vary depending on the capacity of the memory device, and in the example of FIG. A case of having is exemplified. In one embodiment, a memory cell array of a DRAM chip includes a plurality of bank groups (BG), each bank group (BG) may include four banks (BA), and each bank of the DRAM chip A different number of word lines may be disposed for each memory capacity. As an example, when a DRAM chip has a capacity of 8 Gb, 32k word lines are disposed in one bank, when a DRAM chip has a capacity of 12 Gb, 48 k word lines are disposed, and when a DRAM chip has a capacity of 16 Gb, 64 k word lines are disposed. Word lines are arranged, and in the case of having a capacity of 24 Gb, 96k word lines may be arranged.

If it is assumed that the refresh cycle of the memory device is defined as 64 ms and that 8k refresh commands are provided from the memory controller to the memory device during the refresh cycle according to the refresh command reception interval tREFI at which the refresh commands are received, the memory device In the case of performing a 2-series refresh, 16k refresh operations may be performed during one refresh cycle. In this case, when 32k word lines are disposed in each bank as the memory capacity corresponds to 8 Gb, two word lines need to be simultaneously refreshed every refresh operation (eg, normal refresh operation).

Meanwhile, when the memory device performs target refresh according to the above-described embodiment, target refresh may be performed in some refresh operations among the 16k refresh operations described above. For example, when a normal refresh operation and a target refresh operation are performed at a ratio of 1:1, each of the normal refresh operation and the target refresh operation may be performed 8k times within one refresh cycle. In this case, in order to perform normal refresh operations on all 32k word lines, four word lines need to be simultaneously refreshed in each normal refresh operation.

4(b) shows an example of a refresh operation in a memory device having a capacity of 8 Gb, and shows an example of a refresh operation when the first to fourth refresh commands C_Ref 1 to C_Ref 4 are received. In addition, in the first row of FIG. 4(b), a case in which only the normal refresh operation N is performed without the target refresh operation T being performed is exemplified, and in the second row of FIG. 4(b), the present disclosure is illustrated. A case in which the target refresh operation (T) and the normal refresh operation (N) are performed in a case where the embodiment of is not applied is illustrated, and in the third row of FIG. 4 (b), the target refresh operation according to the embodiment of the present disclosure is illustrated. A case in which (T) and a normal refresh operation (N) are performed is exemplified. In the case of the second and third rows of FIG. 4(b), it is assumed that the target refresh operation (T) and the normal refresh operation (N) are performed at a ratio of 1:1.

As shown in the first row of (b) of FIG. 4, two refresh operations may be performed in response to each of the first to fourth refresh commands (C_Ref 1 to C_Ref 4), and according to the above-described embodiment Two word lines may be simultaneously refreshed in one refresh operation.

On the other hand, as shown in the second row of FIG. 4(b), only the same type of refresh operation is performed in response to each refresh command, and half of the plurality of refresh operations included in one refresh cycle As the target refresh is performed at the refresh operation timing corresponding to , refresh operations may be simultaneously performed on four word lines in one normal refresh operation (N). In addition, a time interval (2 * tREFI) at which two refresh commands are received may correspond to a unit for determining the most active word line, and two word lines adjacent to the most active word line on both sides are weak. It may be determined as a word line, and target refresh may be performed on two weak word lines during a period in which the most active word line is determined.

For example, two normal refresh operations may be performed in response to the first refresh command C_Ref 1, and four word lines may be simultaneously refreshed in each normal refresh operation. Thereafter, target refresh operations may be performed twice in response to the second refresh command C_Ref 2, and one weak word line may be refreshed in each target refresh operation. The normal refresh operation (N) and the target refresh operation (T) as described above may be alternately performed whenever a refresh command is received.

Meanwhile, according to the embodiment of the present disclosure shown in the third row of FIG. 4(b), a normal refresh operation N and a target refresh operation T may be performed together in response to one refresh command. For example, in response to the first refresh command (C_Ref 1), after four word lines are normally refreshed at the first refresh timing at the same time, a target refresh operation (T) is performed on one weak word line at the next refresh timing. It can be. Similarly, after four word lines are normally refreshed simultaneously in response to the second refresh command C_Ref 2, a target refresh operation T for one weak word line may be performed. Meanwhile, although a case where a normal refresh operation (N) is first performed in response to each refresh command and then a target refresh operation (T) is performed has been exemplified, in an exemplary embodiment of the present disclosure, the target refresh operation (T) is performed. After that, a normal refresh operation (N) may be performed.

According to the exemplary embodiment of the present disclosure as described above, the case where the number of word lines refreshed during a relatively short time period (eg, a refresh period) rapidly increases can be reduced. As an example, FIG. 4 (b) As shown in the third row of ), the total number of simultaneously refreshed word lines can be uniform, and through this, power noise can be reduced. In addition, in an exemplary embodiment of the present disclosure, when the capacity of the memory device is larger than a predetermined size, a large number of word lines corresponding to multiples of 4 may be normally refreshed at the same time at one refresh timing, but in a relatively short time period. Since it is possible to reduce the number of cases in which normal refresh is continuously performed in

5 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 5 , the memory device may periodically receive a refresh command from the memory controller and, for example, a first refresh command (S11). The memory device may perform N-series refresh in response to reception of each refresh command. For example, the memory device may perform N-series refresh in response to reception of the first refresh command, for example, to a plurality of first word lines at each of some of N refresh timings in response to reception of the first refresh command. A normal refresh may be performed for (S12). And, target refresh may be performed on the first target word line at each of the other partial timings among the N refresh timings (S13). As an example, the first target word line may include at least one word line. can

Thereafter, the memory device may receive a second refresh command from the memory controller (S14), and at each of some of the N refresh timings in response to the reception of the second refresh command, a plurality of second word lines are generated. A normal refresh may be performed (S15). In addition, target refresh may be performed on the second target word line at different timings among the N refresh timings (S16).

In an exemplary embodiment, a normal refresh operation may be performed based on a normal address sequentially indicating a plurality of word lines, and the normal address may be generated based on a counting operation. Also, the plurality of first word lines may include two or more word lines spaced apart from each other by a predetermined number of word lines in any one bank of the memory cell array. Accordingly, the plurality of second word lines may include word lines positioned adjacent to the first word lines.

6 is a diagram illustrating an example of a refresh operation in any one bank (BANK) according to an exemplary embodiment of the present disclosure. In FIG. 6 , a case in which the memory device performs a two-series refresh and also performs one normal refresh and one target refresh in response to each refresh command is exemplified.

First, as the first refresh command C_Ref 1 is received from the memory controller, the memory device may perform two refresh operations within the refresh period tRFC. As an example, a normal refresh operation may be performed at the first refresh timing. and a target refresh operation may be performed at the second refresh timing. Depending on the number of word lines included in the memory device, a plurality of word lines may be simultaneously refreshed in a normal refresh operation. As an example, a case in which four word lines are simultaneously refreshed at a first refresh timing is exemplified.

Meanwhile, the most active word line may be determined during a predetermined time period, and for example, a predetermined period before the first refresh command is received (for example, a time when two refresh commands are received from the memory controller). At least two weak word lines may be determined based on the most active word line determined during the period). Assuming that the most active word line is the k-th word line WL k, a first refresh timing adjacent to one side of the k-th word line WL k at a second refresh timing in response to a first refresh command. A target refresh may be performed for the weak word line (weak WL 1).

Meanwhile, the memory device may receive the second refresh command C_Ref 2 thereafter from the memory controller, and normal refresh may be performed at a first refresh timing in response to the second refresh command. As an example, as normal refresh proceeds sequentially for word lines based on address counting, four word lines adjacent to four word lines on which normal refresh has been performed are simultaneously refreshed in response to a previous first refresh command. It can be.

Meanwhile, a target refresh may be performed at a second refresh timing in response to the second refresh command C_Ref 2, and another day of the previously determined most activated word line (eg, k th word line WL k). Target refresh may be performed on the second weak word line (weak WL 2 ) adjacent to the second weak word line. As the above target refresh operation is added to the refresh cycle, some word lines may be refreshed at least twice within one refresh cycle.

7 is a block diagram illustrating a specific implementation example of a memory device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 7 , the memory device 300 may include a control logic 310 , a refresh controller 320 , a refresh logic 330 and a memory cell array 340 . The components shown in FIG. 7 are for one possible implementation, and some of the components in the refresh controller 320 shown in FIG. 7 can be described as being included in the control logic 310, or It may be described as being separately located outside the refresh controller 320 .

The control logic 310 may perform control related to the refresh operation according to the above-described embodiments, and as an example, a normal refresh address (or , the normal address ADD_N) may be provided to the refresh controller 320 . In addition, the refresh controller 320 includes a first address buffer 321, a second address buffer 322, an address selector 323, a maximum active address generator 324, an address converter 325, and a refresh scheduler 326. can include

The maximum active address generator 324 may include a counter circuit (not shown) therein, count the number of actives of each word line during a predetermined period, and based on the counting result, the most active word line. address can be created. In addition, the address converter 325 may perform an address conversion operation of generating an address of a weak word line adjacent to the most active word line, and for example, by adding 1 to the address of the most active word line. A target address ADD_T indicating a weak word line adjacent to one side of the most active word line may be generated, and by subtracting 1 from the address of the most active word line, the most active word line A target address (ADD_T) indicating a weak word line adjacent to the other side of may be generated. In addition, the normal address ADD_N is stored in the first address buffer 321, the target address ADD_T is stored in the second address buffer 322, and the normal address ADD_N and the target address ADD_T are stored in an address selector. It may be provided as an input of (323).

Meanwhile, the address selector 323 may selectively output the normal address ADD_N or the target address ADD_T in response to the refresh control signal Ctrl_R, and a 2 series refresh operation may be performed based on the embodiments of the present disclosure. As such, the address selector 323 may alternately output the normal address ADD_N and the target address ADD_T in any one refresh period. The normal address ADD_N or the target address ADD_T output from the address selector 323 may be provided to the refresh scheduler 326, and the refresh scheduler 326 may schedule refresh timing. For example, in a memory operation, a refresh operation may be performed ahead of or delayed by a predetermined time, and the refresh timing may be adjusted based on the control of the refresh scheduler 326 .

Meanwhile, the refresh logic 330 may perform an operation of controlling the memory cell array 340 so that an actual refresh is performed based on the control of the refresh scheduler 326. For example, the normal address ADD_N or the target address A control operation for activating a word line at a location indicated by (ADD_T) may be performed.

8 is a diagram illustrating an example of a refresh operation of a memory device according to various embodiments of the present disclosure. 8 illustrates an example of a refresh operation in adjacent first and second banks BA 1 and BA 2 . In addition, 2 series refresh is performed in response to each refresh command, the normal refresh operation (N) and the target refresh operation (T) may be performed at a ratio of 1:1, and in each normal refresh operation (N) A case in which four word lines are simultaneously refreshed is exemplified.

When the embodiment of the present disclosure is not applied, as shown in the first row of FIG. 8, a normal refresh operation (N ) may be performed, and as an example, four word lines per one bank may be simultaneously refreshed at each of the first and second refresh timings of one refresh period. In this case, at one refresh timing, eight word lines located in the first and second banks BA 1 and BA 2 adjacent to each other are simultaneously refreshed, and the first and second word lines corresponding to a relatively short time interval are refreshed simultaneously. At the second refresh timings, all 16 word lines can be refreshed.

Meanwhile, the target refresh operation T may be performed in each of the first and second banks BA 1 and BA 2 in response to the second refresh command C_Ref 2, and each refresh timing within one refresh period , a target refresh operation (T) for one word line in one bank may be performed. Similarly, a normal refresh operation N may be performed in each of the first and second banks BA 1 and BA 2 in response to the third refresh command C_Ref 3 , and the fourth refresh command C_Ref 4 ), a target refresh operation T may be performed in each of the first and second banks BA 1 and BA 2 .

According to the above operation example, in the refresh operation performed in response to each of the first refresh command C_Ref 1 and the third refresh command C_Ref 3, a very large number of word lines are refreshed in a concentrated manner during a relatively short period of time. Therefore, performance degradation may occur due to power noise.

Meanwhile, when the embodiment of the present disclosure is applied as shown in the second row of FIG. 8 , a normal refresh operation (N) and a target refresh operation (T) may be performed together in one refresh period. For example, four word lines can be normally refreshed simultaneously at one refresh timing in one refresh period, and one weak word line can be targeted refreshed at another refresh timing.

In an exemplary embodiment, different types of refresh may be performed on the first bank BA 1 and the second bank BA 2 at any one refresh timing. For example, at the first refresh timing in response to the first refresh command C_Ref 1, four word lines are simultaneously refreshed as the normal refresh operation N is performed on the first bank BA 1, while the second As the target refresh operation T is performed in the bank BA2 , one weak word line may be refreshed. In addition, at the second refresh timing in response to the first refresh command C_Ref 1, one weak word line is refreshed as the target refresh operation T is performed in the first bank BA 1, while the second As the normal refresh operation N is performed on the bank BA2 , four word lines can be normally refreshed at the same time.

Similarly, for each of the second refresh command (C_Ref 2) to the fourth refresh command (C_Ref 4), there may be two refresh timings in response to each refresh command, and first and second refresh timings may exist at each refresh timing. A normal refresh operation N may be performed on one of the banks BA 1 and BA 2 , while a target refresh operation T may be performed on the other bank.

According to the exemplary embodiment of the present disclosure as described above, as different types of refresh operations are applied to adjacent banks at the same refresh timing, the number of word lines simultaneously refreshed at each refresh timing is uniform, , through which power noise can be reduced. For example, when a normal refresh operation (N) in which a plurality of word lines are simultaneously refreshed is simultaneously applied to a plurality of adjacent banks, power noise may increase as a large number of word lines are simultaneously refreshed. According to an embodiment of the present disclosure, the number of word lines simultaneously refreshed at each refresh timing may be reduced.

9 is a diagram illustrating an example of a refresh operation of a memory device according to another exemplary embodiment of the present disclosure. In FIG. 9 , in an exemplary embodiment of the present disclosure, a case where 3 series refresh is performed in response to each refresh command is illustrated.

The first row of FIG. 9 shows a case where 2 series refresh is performed and the target refresh operation T is not performed without the embodiment of the present disclosure being applied, and the first refresh command (C_Ref 1) to the fourth refresh command There are two refresh timings corresponding to each (C_Ref 4), and a normal refresh operation (N) may be performed on four word lines at each refresh timing. Meanwhile, the second row of FIG. 9 shows a case in which a 2-series refresh is performed and a target refresh operation (T) is performed without the embodiment of the present disclosure being applied, and the first refresh command (C_Ref 1) to the fourth refresh There are two refresh timings in response to each command (C_Ref 4), and only a normal refresh operation (N) is performed in response to one refresh command, while a target refresh operation (T) is performed in response to the other refresh command. ) can only be performed. At this time, when the normal refresh operation (N) is performed, eight word lines may be refreshed simultaneously, and when the target refresh operation (T) is performed, target refresh may be performed on one weak word line. .

Meanwhile, when the embodiment of the present disclosure is applied as shown in the third row of FIG. 9, three refresh timings exist in one refresh period, and a normal refresh operation (N) is performed at some of the three refresh timings, A target refresh operation T may be performed in another part. For example, a case in which two normal refresh operations (N) are performed and one target refresh operation (T) is performed in response to one refresh command is exemplified.

The number of times the normal refresh operation (N) and the target refresh operation (T) are performed may be set to a predetermined ratio, and according to an exemplary embodiment, the number of times the normal refresh operation (N) and the target refresh operation (T) are performed is 2 : Can be set at a ratio of 1. In this case, in one operation example, four word lines can be simultaneously refreshed in each normal refresh operation (N) in response to one refresh command, whereas one weak word line is refreshed in the target refresh operation (T). can be refreshed. Also, in an exemplary embodiment, a normal refresh operation (N), a target refresh operation (T), and a normal refresh operation (N) may be sequentially performed in response to each refresh command.

According to the exemplary embodiment as described above, the number of word lines simultaneously refreshed at each refresh timing can be reduced, and the case where a plurality of word lines are refreshed consecutively can be reduced. As an example, the refresh command reception interval may be relatively long in terms of time compared to one refresh period (eg, tRFC), and accordingly, normal refresh performed at the third refresh timing in response to the first refresh command (C_Ref 1) Since the time interval between operation N and the normal refresh operation N performed at the first refresh timing in response to the second refresh command C_Ref 2 may be relatively long, a large number of word lines may be generated during a short period of time. The cases in which they are intensively refreshed can be reduced.

10 is a flowchart illustrating a method of operating a memory system including a memory device of the present disclosure.

Referring to FIG. 10 , as the memory system is initially driven, the memory device included in the memory system is initially driven (S21), and the mode register set included in the memory device is controlled by the memory controller. Various setting information for setting the operating environment of the may be stored. For example, a different number of word lines may be provided in the memory device according to the capacity of the memory device, and an operating environment according to the capacity of the memory device may be set by the initial driving based on control from a memory controller ( S22).

According to the operating environment setting as described above, the refresh operation of the memory device may be differently controlled depending on whether the capacity of the memory device is greater than or less than the reference value (S23). For example, when the capacity of the memory device is greater than a predetermined reference value, it may indicate that the number of word lines included in the memory device is relatively large. In this case, embodiments of the present disclosure may be applied to a refresh operation. That is, when the number of word lines is relatively large, the number of word lines refreshed at the same time may be relatively large, and accordingly, in response to one refresh command to reduce power noise, refresh is performed along with normal refresh and target refresh. Operation can be controlled (S25).

On the other hand, when the capacity of the memory device is smaller than a predetermined reference value, it may indicate that the number of word lines included in the memory device is relatively small, and in this case, it indicates that the number of word lines that are simultaneously refreshed is relatively small. can Accordingly, normal refresh and target refresh may be separately performed in response to one refresh command (S24). For example, a plurality of normal refreshes may be successively performed in response to one refresh command, and a plurality of target refreshes may be successively performed in response to another refresh command.

11 is a block diagram illustrating a memory system of an exemplary embodiment of the present disclosure. 11 illustrates data (DATA) access between an application processor 410 and a memory device 420, and the memory system 400 includes the application processor 410 and the memory device 420. Alternatively, the memory control module 411 in the application processor 410 and the memory device 420 may constitute the memory system 400 . According to the above-described embodiment, the memory device 420 may include a memory cell array 421 , a refresh controller 422 , and a control logic 424 .

The application processor 410 may be implemented as a System on Chip (SoC). A system on a chip (SoC) may include a system bus (not shown) to which a protocol having a predetermined standard bus specification is applied, and may include various intellectual properties (IPs) connected to the system bus. As a standard specification of a system bus, an Advanced Microcontroller Bus Architecture (AMBA) protocol of Advanced RISC Machine (ARM) may be applied. Bus types of the AMBA protocol may include an Advanced High-Performance Bus (AHB), an Advanced Peripheral Bus (APB), an Advanced eXtensible Interface (AXI), AXI4, and AXI Coherency Extensions (ACE). In addition, other types of protocols such as SONICs Inc.'s uNetwork, IBM's CoreConnect, and OCP-IP's Open Core Protocol may be applied.

In an exemplary embodiment, at least some control operations related to the refresh operation may be performed by the application processor 410, and as an example, the memory control module 411 may include a weak word line determiner 411_1. there is. The memory control module 411 may provide commands/addresses (CMD/ADD) to the memory device 420, and accordingly, determine whether word lines included in the memory device 420 are active, and determine the number of actives. A weak word line may be determined based on a counting result for .

The refresh controller 422 may include a scheduler 422_1, and may perform scheduling such that a normal refresh and a target refresh are simultaneously performed in one refresh interval according to the above-described embodiments. As an example of operation, the memory control module 411 may provide a target address ADD_T indicating at least one weak word line to the memory device 420 together with a refresh command, and the memory device 420 may control the memory. Target refresh may be performed based on the target address ADD_T from module 411 . For example, the memory device 420 may generate a normal address (not shown) on which a normal refresh is to be performed based on an internal counting operation, and perform the present disclosure through a scheduling operation using the normal address and the target address ADD_T. It will be possible to perform a refresh operation to which examples are applied.

12 is a diagram illustrating an operation example of a memory device according to another exemplary embodiment of the present disclosure. In FIG. 12 , a case in which target refresh is selectively performed based on the number of actives of word lines in which target refresh is activated the most according to embodiments of the present disclosure is exemplified.

If the number of activations of the most active word line within a predetermined period does not exceed the threshold Th, this may correspond to a case in which there is no word line that has received a large amount of electromagnetic interference. performance can be skipped. In this case, when two refresh operations are performed in the refresh interval tRFC in response to one refresh command, only the normal refresh operation N can be continuously performed.

On the other hand, if the active count of the most active word line within a predetermined period exceeds the threshold Th, it corresponds to a case in which one or more specific word lines are greatly subjected to electromagnetic interference, and thus target refresh is performed. can be performed In this case, when two refresh operations are performed in the refresh period tRFC in response to one refresh command, the normal refresh operation N and the target refresh operation T may be sequentially performed.

13 is a block diagram illustrating a data center 500 including a system according to an exemplary embodiment of the present disclosure. In some embodiments, the memory system described above with reference to the drawings may be included in an application server and/or a storage server of the data center 500 .

Referring to FIG. 13 , a data center 500 may collect various data and provide services, and may be referred to as a data storage center. For example, the data center 500 may be a system for operating a search engine and a database, or may be a computing system used by companies such as banks or government agencies. As shown in FIG. 13 , the data center 500 may include application servers 50_1 to 50_n and storage servers 60_1 to 60_m (m and n are integers greater than 1). The number n of application servers 50_1 to 50_n and the number m of storage servers 60_1 to 60_m may be variously selected according to embodiments, and the number n of application servers 50_1 to 50_n and the number of storage servers The number m of (60_1 to 60_m) may be different.

The application servers 50_1 to 50_n include at least one of processors 51_1 to 51_n, memory 52_1 to 52_n, switches 53_1 to 53_n, network interface controllers (NICs) 54_1 to 54_n, and storage devices 55_1 to 55_n. may contain one. The processors 52_1 to 51_n may control overall operations of the application servers 50_1 to 50_n, and may access the memories 52_1 to 52_n to provide instructions and/or data loaded into the memories 52_1 to 52_n. can run The memories 52_1 to 52_n include, but are not limited to, DDR SDRAM (Double Data Rate Synchronous DRAM), HBM (High Bandwidth Memory), HMC (Hybrid Memory Cube), DIMM (Dual In-line Memory Module), Optane DIMM, or NVMDIMM (Non-Volatile DIMM) may be included.

Depending on embodiments, the number of processors and memories included in the application servers 50_1 to 50_n may be variously selected. In some embodiments, the processors 51_1 to 51_n and the memories 52_1 to 52_n may provide a processor-memory pair. In some embodiments, the number of processors 51_1 to 51_n and memories 52_1 to 52_n may be different. The processors 51_1 to 51_n may include single-core processors or multi-core processors. In some embodiments, as shown by dotted lines in FIG. 13 , the storage devices 55_1 to 55_n may be omitted from the application servers 50_1 to 50_n. The number of storage devices 55_1 to 55_n included in the storage servers 50_1 to 50_n may be variously selected according to embodiments. Processors 51_1 to 51_n, memories 52_1 to 52_n, switches 53_1 to 53_n, NICs 54_1 to 54_n, and/or storage devices 55_1 to 55_n communicate with each other through the links described above with reference to the drawings. can do.

The storage servers 60_1 to 60_m may include at least one of processors 61_1 to 61_m, memory 62_1 to 62_m, switches 63_1 to 63_m, NICs 64_1 to 64_n, and storage devices 65_1 to 65_m. there is. The processors 61_1 to 61_m and the memories 62_1 to 62_m may operate similarly to the processors 51_1 to 51_n and the memories 52_1 to 52_n of the application servers 50_1 to 50_n described above.

The memories 52_1 to 52_n and 62_1 to 62_m included in the application servers 50_1 to 50_n and the storage servers 60_1 to 60_m may include memory devices according to the above-described embodiments. For example, the memories 52_1 to 52_n and 62_1 to 62_m may include a volatile memory device such as DRAM, and in performing a refresh operation on a plurality of word lines, the normal refresh operation according to the above-described embodiments and the target A refresh operation may be performed.

The application servers 50_1 to 50_n and the storage servers 60_1 to 60_m may communicate with each other through the network 70 . In some embodiments, network 70 may be implemented using Fiber Channel (FC) or Ethernet, or the like. FC may be a medium used for relatively high-speed data transmission, and an optical switch providing high performance/high availability may be used. According to the access method of the network 70, the storage servers 60_1 to 60_m may be provided as file storage, block storage, or object storage.

In some embodiments, network 70 may be a storage-only network, such as a storage area network (SAN). For example, the SAN may use an FC network and may be an FC-SAN implemented according to FC Protocol (FCP). Alternatively, the SAN may be an IP-SAN using a TCP/IP network and implemented according to the iSCSI (SCSI over TCP/IP or Internet SCSI) protocol. In some embodiments, network 70 may be a general network such as a TCP/IP network. For example, the network 70 may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabrics (NVMe-oF).

Hereinafter, the application server 50_1 and the storage server 60_1 are mainly described, but the description of the application server 50_1 can also be applied to other application servers (eg, 50_n), and the description of the storage server 60_1 It is noted that it can also be applied to other storage servers (eg, 60_m).

The application server 50_1 may store data requested by a user or client to be stored in one of the storage servers 60_1 to 60_m through the network 70 . In addition, the application server 50_1 may acquire data requested to be read by a user or client from one of the storage servers 60_1 to 60_m through the network 70 . For example, the application server 50_1 may be implemented as a web server or a database management system (DBMS).

The application server 50_1 may access the memory 52_n and/or the storage device 55_n included in another application server 50_n through the network 70, and/or the storage server through the network 70. The memories 62_1 to 62_m and/or the storage devices 65_1 to 65_m included in the fields 60_1 to 60_m may be accessed. Accordingly, the application server 50_1 may perform various operations on data stored in the application servers 50_1 to 50_n and/or the storage servers 60_1 to 60_m. For example, the application server 50_1 may execute a command for moving or copying data between the application servers 50_1 to 50_n and/or the storage servers 60_1 to 60_m. At this time, the data is transferred from the storage devices 65_1 to 65_m of the storage servers 60_1 to 60_m through the memories 62_1 to 62_m of the storage servers 60_1 to 60_m or directly to the application servers 50_1 to 50_n. ) can be moved to the memories 52_1 to 52_n. In some embodiments, data traveling through network 70 may be encrypted data for security or privacy.

In the storage server 60_1, the interface IF may provide a physical connection between the processor 61_1 and the controller CTRL and a physical connection between the NIC 64_1 and the controller CTRL. For example, the interface IF may be implemented in a Direct Attached Storage (DAS) method that directly connects the storage device 65_1 with a dedicated cable. Also, for example, interfaces (IF) include Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), and Peripheral SATA (PCI). Component Interconnection), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), It can be implemented in various interface methods such as UFS (Universal Flash Storage), eUFS (embedded Universal Flash Storage), CF (compact flash) card interface, and the like.

In the storage server 60_1, the switch 63_1 selectively connects the processor 61_1 and the storage device 65_1 or selectively connects the NIC 64_1 and the storage device 65_1 under the control of the processor 61_1. can be connected.

In some embodiments, NIC 64_1 may include a network interface card, network adapter, or the like. The NIC 54_1 may be connected to the network 70 through a wired interface, a wireless interface, a Bluetooth interface, an optical interface, or the like. The NIC 54_1 may include an internal memory, a DSP, a host bus interface, and the like, and may be connected to the processor 61_1 and/or the switch 63_1 through the host bus interface. In some embodiments, the NIC 64_1 may be integrated with at least one of the processor 61_1, the switch 63_1, and the storage device 65_1.

In the application server (50_1 to 50_n) or storage server (60_1 to 60_m), the processors (51_1 to 51_m, 61_1 to 61_n) are connected to the storage devices (55_1 to 55_n, 65_1 to 65_m) or memory (52_1 to 52_n, 62_1 to 62_m). You can program or read data by sending a command to . In this case, the data may be error-corrected data through an Error Correction Code (ECC) engine. The data is data subjected to data bus inversion (DBI) or data masking (DM) processing, and may include Cyclic Redundancy Code (CRC) information. The data may be encrypted data for security or privacy.

In response to read commands received from the processors 51_1 to 51_m and 61_1 to 61_n, the storage devices 55_1 to 55_n and 65_1 to 65_m transmit control signals and command/address signals to nonvolatile memory devices (eg, NAND flash memory devices, NVM). Accordingly, when data is read from the non-volatile memory device NVM, the read enable signal may be input as a data output control signal and output data to the DQ bus. A data strobe signal may be generated using the read enable signal. The command and address signals may be latched according to a rising edge or a falling edge of the write enable signal.

The controller CTRL may control the overall operation of the storage device 65_1. In one embodiment, the controller CTRL may include static random access memory (SRAM). The controller CTRL may write data into the nonvolatile memory device NVM in response to a write command, or may read data from the nonvolatile memory device NVM in response to a read command. For example, a write command and/or a read command may be applied to a host, for example, a processor 61_1 in a storage server 60_1, a processor 61_m in another storage server 60_m, or a processor 51_1 to 50_n in an application server 50_1 to 50_n. 51_n) may be generated based on a request provided. The buffer BUF may temporarily store (buffer) data to be written in the non-volatile memory device NVM or data read from the non-volatile memory device NVM. In some embodiments, the buffer BUF may include DRAM. Also, the buffer BUF may store meta data, and the meta data may refer to user data or data generated by the controller CTRL to manage the non-volatile memory device NVM. The storage device 65_1 may include a Secure Element (SE) for security or privacy.

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the embodiments have been described using specific terms in this specification, they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the claims. . Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (20)

A method of operating a memory device, wherein the memory device includes a plurality of word lines,
performing a first normal refresh of simultaneously refreshing N word lines among the plurality of word lines at a first refresh timing in response to reception of a first refresh command (where N is an integer greater than or equal to 2);
performing a first target refresh on a first weak word line adjacent to a most active maximum active word line among the plurality of word lines at a second refresh timing in response to reception of the first refresh command;
performing a second normal refresh to simultaneously refresh other N word lines among the plurality of word lines at a first refresh timing in response to reception of a second refresh command; and
and performing a second target refresh on a second weak word line adjacent to the maximum active word line at a second refresh timing in response to reception of the second refresh command. . According to claim 1,
The first weak word line is a word line most adjacent to the maximum active word line on one side, and the second weak word line is a word line closest to the maximum active word line on another side. method. According to claim 1,
The first weak word line includes at least two word lines on one side adjacent to the most active word line, and the second weak word line includes at least two word lines on one side adjacent to the most active word line. A method of operating a memory device, characterized in that. According to claim 1,
The maximum active word line corresponds to the most active word line during a time interval during which two refresh commands are received. According to claim 1,
The memory device includes a first bank and a second bank,
At the first refresh timing in response to reception of the first refresh command, N word lines of the first bank are simultaneously refreshed and target refresh is performed on any one weak word line of the second bank. A method of operating a memory device to be used. According to claim 5,
At the second refresh timing in response to reception of the first refresh command, a target refresh is performed on one weak word line of the first bank and N word lines of the second bank are simultaneously refreshed. A method of operating a memory device to be used. According to claim 1,
A refresh period (tRFC) corresponding to a time interval at which refresh is performed in response to receiving the first refresh command is defined,
The first normal refresh and the first target refresh are performed within the refresh period (tRFC). According to claim 1,
In response to reception of the first refresh command, the number of word lines simultaneously refreshed in the first normal refresh corresponds to a multiple of 4, and one weak word line is refreshed in the first target refresh. How to operate. In the memory device,
a memory cell array including a plurality of word lines;
a refresh controller that controls refresh operations of the plurality of word lines and schedules normal refresh operations and target refresh operations of the plurality of word lines; and
a control logic for determining at least one weak word line on which the target refresh is to be performed, based on the counting of active times of the plurality of word lines;
The refresh controller performs scheduling such that the normal refresh operation and the target refresh operation are performed together during a refresh period defined in response to reception of one refresh command;
The memory device of claim 1 , wherein the number of word lines simultaneously refreshed in the normal refresh operation is greater than the number of word lines refreshed in the target refresh operation during the refresh period. According to claim 9,
The memory device performs an N-series refresh including N refresh timings during the refresh interval in response to reception of the one refresh command (N is an integer of 2 or more);
The memory device of claim 1 , wherein the number of times the normal refresh operation is performed and the number of times the target refresh operation is performed are the same during the refresh period. According to claim 9,
In the target refresh operation of the refresh period, one weak word line adjacent to one side of a most active word line during a predetermined time period is refreshed. According to claim 11,
The memory device of claim 1 , wherein one weak word line adjacent to the other side of the most active word line is refreshed in a target refresh operation of a refresh period corresponding to a refresh command received next. According to claim 9,
The refresh controller,
generating a normal address indicating word lines to be refreshed in the normal refresh operation, and receiving a target address indicating the weak word line from the control logic;
The memory device of claim 1 , wherein the normal address is output at a timing at which the normal refresh is to be performed, and the target address is output at a timing at which the target refresh is to be performed. According to claim 9,
The memory cell array includes a first bank and a second bank;
The refresh period includes a first refresh timing and a second refresh timing,
At the first refresh timing, the normal refresh operation is performed on a plurality of word lines of the first bank, and the target refresh operation is performed on weak word lines of the second bank. . According to claim 14,
At the second refresh timing, the target refresh operation is performed on weak word lines of the first bank, and the normal refresh operation is performed on a plurality of word lines of the second bank. . According to claim 9,
The weak word line is a word line adjacent to a word line activated the most during a time interval during which two refresh commands are received. In the memory system,
a memory cell array including a plurality of word lines; and a refresh controller configured to control refresh operations of the plurality of word lines and to schedule normal refresh operations of the plurality of word lines and target refresh operations of weak word lines. and
a memory controller controlling access to the memory device by providing commands and addresses to the memory device;
The memory device performs scheduling such that the normal refresh operation and the target refresh operation are simultaneously performed during a refresh period defined in response to reception of one refresh command from the memory controller;
The memory device of claim 1 , wherein the number of word lines simultaneously refreshed in the normal refresh operation is greater than the number of word lines refreshed in the target refresh operation during the refresh period. According to claim 17,
The memory device of claim 1 , wherein the memory device performs the normal refresh operation and the target refresh operation once, respectively, during the refresh period in response to reception of the one refresh command. According to claim 18,
The weak word line includes a first weak word line and a second weak word line adjacent to both sides of the most active word line during a predetermined period;
A target refresh operation for the first weak word line is performed in the target refresh operation corresponding to reception of the one refresh command;
The memory device of claim 1 , wherein a target refresh operation for the second weak word line is performed in the target refresh operation corresponding to reception of a next refresh command. According to claim 18,
The memory controller,
Determining the weak word line based on counting active times of a plurality of word lines of the memory device;
and transmitting a target address indicating the weak word line to the memory device together with the refresh command.

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