CN117075795A

CN117075795A - Memory system and computing system including the same

Info

Publication number: CN117075795A
Application number: CN202310429947.3A
Authority: CN
Inventors: 吴起硕; 李宰旭; 金文敬; 李淙圣; 郑柱衍
Original assignee: Samsung Electronics Co Ltd; Industry Academic Cooperation Foundation of Yonsei University
Current assignee: Samsung Electronics Co Ltd; Industry Academic Cooperation Foundation of Yonsei University
Priority date: 2022-05-17
Filing date: 2023-04-20
Publication date: 2023-11-17

Abstract

A memory system and a computing system including the same are provided. The memory system includes a memory resource and an intelligent controller. The memory resource includes a semiconductor memory device, which is divided into a first semiconductor memory and a second semiconductor memory for each of a plurality of channels, the first semiconductor memory and the second semiconductor memory belonging to different blocks. The intelligent controller is connected to the plurality of semiconductor memory devices through channels, and controls the semiconductor memory devices by communicating with a plurality of hosts through a computing fast link (CXL) interface, each of the plurality of hosts driving at least one virtual machine. The intelligent controller controls a power mode of the memory resource by managing an empty memory region among a plurality of memory regions of the plurality of semiconductor memory devices at a block level without intervention of the plurality of hosts, the plurality of memory regions storing data.

Description

Memory system and computing system including the same

Cross Reference to Related Applications

The present application is based on and claims priority of korean patent application No.10-2022-0059913 filed in the Korean Intellectual Property Office (KIPO) at 5/17/2022 and korean patent application No.10-2022-0086052 filed in 7/13/2022, the disclosures of which are incorporated herein by reference in their entireties.

Technical Field

The present disclosure relates generally to memory devices, and more particularly, to memory systems capable of reducing power consumption and computing systems including the memory systems.

Background

Computing systems may provide various Information Technology (IT) services to users. As users are provided with various IT services, the amount of data processed by the computing system increases. Computing systems are evolving towards heterogeneous computing environments and mass storage systems to provide a variety of IT services. Various techniques are being developed today for reducing power consumption in mass memory systems.

Disclosure of Invention

According to one or more aspects of the present disclosure, a memory system capable of reducing power consumption is provided.

According to one or more aspects of the present disclosure, a computing system is provided that includes a memory system capable of reducing power consumption.

According to some aspects of the present disclosure, there is provided a memory system including a memory resource including a plurality of semiconductor memory devices coupled to each other through an internal bus, the plurality of semiconductor memory devices being divided into a first semiconductor memory and a second semiconductor memory for each of a plurality of channels, the first semiconductor memory and the second semiconductor memory belonging to different blocks, and a controller connected to the plurality of semiconductor memory devices through the plurality of channels, the controller configured to control the plurality of semiconductor memory devices based on communication with a plurality of hosts through a computing fast link (CXL) interface, each of the plurality of hosts configured to drive at least one virtual machine, wherein the controller is configured to: the power mode of the memory resource is controlled by managing free memory regions among a plurality of memory regions of the plurality of semiconductor memory devices at a block level without intervention of the plurality of hosts, the plurality of memory regions configured to store data.

According to further aspects of the present disclosure, there is provided a computing system comprising a plurality of hosts, each of the plurality of hosts configured to drive at least one virtual machine, and a memory system configured to process memory requests from the plurality of hosts based on communicating with the plurality of hosts through a computing express link (CXL) interface, wherein the memory system comprises a memory resource comprising a plurality of semiconductor memory devices coupled to each other through an internal bus, the plurality of semiconductor memory devices being divided into a first semiconductor memory and a second semiconductor memory for each of a plurality of channels, the first semiconductor memory and the second semiconductor memory belonging to different blocks, and a controller configured to control the plurality of semiconductor memory devices based on communicating with the plurality of hosts through the CXL interface, wherein the controller is configured to: controlling a power mode of the memory resource by managing, at a block level, a free memory region among a plurality of memory regions of the plurality of semiconductor memory devices, the plurality of memory regions configured to store data, without the plurality of host interventions, wherein the free memory region corresponds to a memory region among the plurality of memory regions that does not store the data, or a memory region having an access frequency less than a reference frequency during a reference time interval.

According to further aspects of the present disclosure, there is provided a memory system including a memory resource including a plurality of semiconductor memory devices coupled to each other through an internal bus, the plurality of semiconductor memory devices being divided into a first semiconductor memory and a second semiconductor memory for each of a plurality of channels, the first semiconductor memory and the second semiconductor memory belonging to different blocks, and a controller connected to the plurality of semiconductor memory devices through the plurality of channels, the controller configured to control the plurality of semiconductor memory devices based on communication with a plurality of hosts through a computing fast link (CXL) interface, each of the plurality of hosts configured to drive at least one virtual machine, wherein the controller is configured to: controlling a power mode of the memory resource by managing free memory regions among a plurality of memory regions of the plurality of semiconductor memory devices at a block level without the plurality of host interventions, the plurality of memory regions configured to store data, wherein the controller comprises a hot/cold page analyzer, wherein the hot/cold page analyzer is configured to: based on a total memory traffic requested from at least one host among the plurality of hosts being less than a first reference value, cold pages and hot pages among a plurality of pages of the plurality of semiconductor memory devices are monitored, the cold pages storing cold data having a data access frequency less than a reference frequency during a reference time interval, the hot pages storing hot data having the data access frequency equal to or greater than the reference frequency during the reference time interval, and data migration is performed to migrate one or more cold pages of a first block of a first channel among the plurality of channels to a second block of the first channel based on a result of the monitoring.

Accordingly, a controller in a memory system and a computing system according to various example embodiments allocates virtual machines to a plurality of semiconductor memory devices at a block level, enters a block to which a virtual machine is not allocated into a deep power down mode, divides memory regions of the plurality of semiconductor memory devices into hot pages and cold pages based on memory requests to the plurality of semiconductor memory devices, migrates cold data of the cold pages of one block to another block, and enters a cold block including the cold pages into a self-refresh mode, thereby controlling a power mode of memory resources at a block level.

Drawings

Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram illustrating a computing system according to an example embodiment.

FIG. 2 is a block diagram illustrating one of a plurality of hosts in the computing system of FIG. 1 according to an example embodiment.

Fig. 3 illustrates an example of multiple protocols for communication in the computing system of fig. 1.

FIG. 4 is a block diagram illustrating one of a plurality of hosts in the computing system of FIG. 1 according to an example embodiment.

Fig. 5 is a block diagram illustrating one example of a semiconductor memory device in the computing system of fig. 1 according to an example embodiment.

Fig. 6 illustrates an example of a first bank array (bank array) in the semiconductor memory device of fig. 5.

Fig. 7 illustrates an example of a memory cell array of the semiconductor memory device of fig. 5.

Fig. 8 illustrates an example state diagram of the semiconductor memory device of fig. 5 according to an example embodiment.

Fig. 9 is a block diagram illustrating an example of a hot/cold page analyzer in the intelligent controller of fig. 1 according to an example embodiment.

10A, 10B and 10C illustrate the allocation of virtual machines by a remapping engine in the intelligent controller of FIG. 1, respectively, according to an example embodiment.

FIG. 11 illustrates example operations of a hot/cold page analyzer in the intelligent controller of FIG. 1, according to example embodiments.

Fig. 12 is a block diagram illustrating an example of a remapping engine in the intelligent controller of fig. 1, according to an example embodiment.

FIG. 13 illustrates an example of a remap cache in the remap engine of FIG. 12 according to an example embodiment.

FIG. 14 illustrates an example of a host address table in the remapping engine of FIG. 12, according to an example embodiment.

FIG. 15 illustrates an example of a set of block address tables in the remapping engine of FIG. 12, according to an example embodiment.

Fig. 16 illustrates an example of a remapping table in the remapping engine in fig. 12, according to an example embodiment.

FIG. 17 illustrates an example of a channel utilization count table in the remapping engine of FIG. 12, according to an example embodiment.

FIG. 18 illustrates example operations of the computing system of FIG. 1 according to example embodiments.

Fig. 19 is a flowchart illustrating a method of operating a memory system according to an example embodiment.

FIG. 20 is a flowchart illustrating a method of operating a memory system according to an example embodiment.

FIG. 21 is an example of a computing system when a memory system according to an example embodiment corresponds to a Type3 (Type 3) memory system defined by the CXL protocol.

Fig. 22 is a block diagram illustrating a semiconductor memory device according to an example embodiment.

FIG. 23 is a block diagram illustrating a data center including a computing system according to an example embodiment.

Detailed Description

Various example embodiments will be described more fully with reference to the accompanying drawings, in which the embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout the present application.

Referring to fig. 1, computing system 10 may include a plurality of HOSTs HOST1 (100 a), HOST2 (100 b), HOST, and memory system 200, memory system 200 including a controller and memory resources. According to an example embodiment, the memory system 200 may include an intelligent controller 210 and a memory resource 400. Here, K and K are integers greater than 2, respectively.

The memory resource 400 may include a plurality of semiconductor memory devices DRAM 401a, 402a, 401b, 402b, 40tb. Here, t is an integer greater than 2. The plurality of semiconductor memory devices 401a, 402a, 40ta, and 401b, 402b, 40tb may be connected to each other through an internal bus IBUS.

The intelligent controller 210 may be referred to as a DRAM network (NoD) controller.

The intelligent controller 210 may be connected to the plurality of semiconductor memory devices 401a, 402a, 40ta and 401b, 402b, 40tb through a plurality of channels CHl, CH2, CHt. For each of the plurality of channels CH1, CH2, CHt, the plurality of semiconductor memory devices 401a, 402a, 40ta, and 401b, 402b, 40tb may be divided into a first semiconductor memory and a second semiconductor memory belonging to different blocks (ranks). The different blocks may include at least a first block and a second block. However, the present disclosure is not limited thereto, and thus, according to another example embodiment, the plurality of semiconductor memory devices 401a, 402a, 40ta, and 401b, 402b, 40tb may be divided into more than two groups. Furthermore, the different blocks may comprise more than two blocks. For example, the different blocks may also include a third block.

The intelligent controller 210 may be connected to a plurality of hosts 100a, 100b, 100k through a computing fast link (CXL) bus 50, and may control a plurality of semiconductor memory devices 401a, 402a, 40ta and 401b, 402b, 40tb by communicating with the plurality of hosts 100a, 100b, 100k through a CXL interface.

According to an example embodiment, CXL bus 50 may support multiple CXL protocols and messages and/or data may be transmitted over the multiple CXL protocols. For example, the plurality of CXL protocols can include a non-coherent (non-coherent) protocol, a coherent (coherent) protocol, and a memory access protocol. For example, the plurality of CXL protocols may include an I/O protocol CXL.io, a cache protocol CXL.cache, or a memory protocol CXL.memory. According to an example embodiment, CXL bus 50 may support protocols such as Peripheral Component Interconnect (PCI), PCI express (PCIe), universal Serial Bus (USB), and Serial Advanced Technology Attachment (SATA). The protocol supported by CXL bus 50 may be referred to as an interconnect protocol.

The intelligent controller 210 may control the power mode of the memory resource 400 by managing an idle memory region among a plurality of memory regions of the plurality of semiconductor memory devices 401a, 402a, & gt, 40ta and 401b, 402b, & gt, 40tb to store data at a block level without intervention of the plurality of hosts 100a, 100b, & gt, 100 k. According to example embodiments, a free memory region among a plurality of memory regions may be identified based on one or more criteria or characteristics. For example, the free memory region may correspond to a memory region that does not store data among a plurality of memory regions, or a memory region that is accessed for storing data during a reference time interval with an access frequency that is less than a reference frequency. However, the present disclosure is not limited thereto, and thus, according to another example embodiment, a free memory region among a plurality of memory regions may be identified based on another criterion.

Intelligent controller 210 may include power management engine 220, hot/cold page analyzer 270, and remapping engine 300.

According to an example embodiment, the hot/cold page analyzer 270 may monitor memory traffic (memory traffic) corresponding to each of the plurality of hosts 100a, 100b, 100 k. According to an example embodiment, the hot/cold page analyzer 270 may be activated based on at least one of the plurality of hosts 100a, 100b, 100a, 100k requesting less memory traffic than a first reference value during a reference time interval. For example, the hot/cold page analyzer 270 may monitor memory traffic requested by each of the plurality of hosts 100a, 100b, 100k, and may be activated in response to at least one of the plurality of hosts 100a, 100b, 100k requesting memory traffic during the reference time interval being less than a first reference value.

The hot/cold page analyzer 270 may periodically monitor cold and hot pages among the plurality of pages of the plurality of semiconductor memory devices 401a, 402a, 40ta and 401b, 402b, 40tb, and may perform data migration of migrating a cold page of a first block of a first channel among the plurality of channels CH1, CH2, CHt to a second block of the first channel based on the result of the monitoring. The cold page may store cold data having an access frequency less than a reference frequency during the reference time interval, and the hot page may store hot data having an access frequency equal to or greater than the reference frequency during the reference time interval.

According to an example embodiment, the remapping engine 300 may map a first physical address of a cold page of a first block of a first channel to a second physical address of a page of a second block of the first channel based on the data migration being performed. For example, in response to a data migration being performed, the remapping engine 300 may map a first physical address of a cold page of a first block of a first channel to a second physical address of a page of a second block of the first channel.

The power management engine 220 may control the power mode of the memory resource 400 based on whether data migration is performed.

For example, when data migration is performed because the available data storage capacity of the second block of the first channel is sufficient, data of the cold page of the first block of the first channel is migrated (or moved) to the page of the second block of the first channel, and the power management engine 220 may put the second block of the first channel into a self-refresh (self-refresh) mode. For another example, the power management engine 220 may cause the second block of the first channel to enter the self-refresh mode when data migration is not performed because the available data storage capacity of the second block of the first channel is less than the size of the cold page of the first block of the first channel.

For example, when data migration is performed, and when a cold page of a second block of a first channel is migrated to another block (e.g., when a cold page of a second block of a first channel is migrated to a free page of a third block), the power management engine 220 may put the second block of the first channel into a deep power-down (deep power-down) mode. The third block may be included in the first channel or may be included in another channel (e.g., the second channel).

For example, when data migration is performed, and when the cold pages of the second block of the first channel are not migrated to another block (third block) because the available data storage capacity of the third block is smaller than the size of the cold pages of the second block of the first channel, the power management engine 220 may cause the second block of the first channel to enter the self-refresh mode.

Each of the plurality of hosts 100a, 100b, 100k may drive at least one virtual machine. The remapping engine 300 may allocate at least one virtual machine running on each of the plurality of hosts 100a, 100b,..100 k to the same block of each of the plurality of channels CH1, CH2,.. CHt, and the power management engine 220 may enter the free memory area into a deep power down mode, or exit the free memory area from the deep power down mode, based on the allocation of additional virtual machines and the deallocation of the at least one virtual machine.

For example, when the remapping engine 300 allocates at least one virtual machine running on each of the plurality of hosts 100a, 100b,..100 k to a first block of each of the plurality of channels CHl, CH2,.. CHt, the power management engine 220 may enter a second block of each of the plurality of channels CH1, CH2,.. CHt into a deep power down mode.

The intelligent controller 210 may be directed to a plurality of hosts 100a, 100b, devices that provide functionality. According to an example embodiment, the intelligent controller 210 may be implemented by hardware, software, or a combination of hardware and software. According to example embodiments, the "parts," "modules," "engines," and/or other components in the intelligent controller 210 may be implemented in hardware, software, or a combination of hardware and software. For example, these components may be implemented by a processor or electronic circuitry. According to another example embodiment, these components may be software elements implemented by program code or instructions stored in a memory device that may be executed by a processor to perform one or more operations. According to example embodiments, the processor may be a dedicated processor (e.g., an embedded processor) for performing the respective one or more operations or a general-purpose processor (e.g., a Central Processing Unit (CPU) or an Application Processor (AP)) that performs the respective one or more operations by executing at least one software program stored in a storage device.

According to an example embodiment, based on the CXL specification 2.0, the intelligent controller 210 may be an accelerator that supports the CXL specification. For example, at least some computing operations and I/O operations performed in multiple hosts 100a, 100b, 100k may be offloaded to the intelligent controller 210. According to example embodiments, the plurality of hosts 100a, 100b, & 100k may each include any one or any combination of programmable components (e.g., graphics Processing Units (GPUs) and Neural Processing Units (NPUs)), components that provide fixed functionality (e.g., intellectual Property (IP) cores), and reconfigurable components (e.g., field Programmable Gate Arrays (FPGAs)). For example, the plurality of hosts 100a, 100b, 100k may each include at least one of a graphics processing unit, a neural processing unit, a field programmable gate array, a network interface card, or a peripheral device that communicates based on the CXL protocol.

In fig. 2, a configuration of a host 100a among a plurality of hosts 100a, 100b, & gt, 100k is shown. The configuration of each of hosts 100b, 100a may be substantially the same as the configuration of host 100 a.

Referring to fig. 2, a host 100a may include a processor 110 and a host memory 140.

The processor 110 may be a Central Processing Unit (CPU) of the host 100 a. According to an example embodiment, the processor 110 may be a CXL-based processor. As shown in fig. 2, the processor 110 may be connected to a host memory 140 and may include a physical layer 117, a multi-protocol multiplexer 116, interface circuitry 115, coherency/cache circuitry 113, bus circuitry 114, at least one core 111, and input/output (I/O) devices 112.

According to an example embodiment, the at least one core 111 may include one or more cores. According to an example embodiment, at least one core 111 may execute instructions and is connected to coherency/cache circuit 113. Coherency/cache circuit 113 may include a cache hierarchy and may be referred to as coherency/cache logic. As shown in FIG. 2, coherency/cache circuitry 113 may be in communication with at least one core 111 and interface circuitry 115. For example, the coherence/cache circuit 113 may enable communication via protocols including at least a coherence protocol and a memory access protocol. According to an example embodiment, coherency/cache circuit 113 may include Direct Memory Access (DMA) circuitry. I/O devices 112 may be used to communicate with bus circuit 114. For example, bus circuit 114 may be PCIe logic and I/O device 112 may be a PCIe I/O device.

Interface circuitry 115 may enable communication between components of processor 110 and memory system 200. For example, interface circuitry 115 may facilitate communication between coherency/cache circuitry 113, bus circuitry 114, and memory system 200. For example, interface circuitry 115 may facilitate communication between components of processor 110 and memory system 200 via CXL bus 50. According to an example embodiment, the interface circuit 115 may enable communication between components of the processor 110 and the memory system 200 according to multiple protocols (e.g., non-coherency protocols, and memory access protocols). According to an example embodiment, the interface circuit 115 may determine one of a plurality of protocols for communication between the components of the processor 110 and the memory system 200 based on the type of message and data to be transmitted.

The multiprotocol multiplexer 116 may include at least one protocol queue. Interface circuitry 115 may be coupled to at least one protocol queue and send and receive messages and/or data to and from memory system 200 via at least one protocol queue. According to an example embodiment, the interface circuit 115 and the multi-protocol multiplexer 116 may be integrally formed as one component. According to an example embodiment, the multi-protocol multiplexer 116 may include a plurality of protocol queues that respectively correspond to a plurality of protocols supported by the CXL bus 50. According to an example embodiment, the multi-protocol multiplexer 116 may arbitrate communications for different protocols and provide selected communications to the physical layer 117.

Referring to fig. 3, the processor 110 and the intelligent controller 210 may communicate with each other based on a plurality of protocols.

According to the CXL example described above, the plurality of protocols may include a memory protocol MEM, a coherency protocol CACHE, and a non-coherency protocol IO. The memory protocol MEM may define a transaction from the primary device or primary component to the secondary device or second component and a transaction from the secondary device or second component to the primary device or primary component. The coherency protocol CACHE may define interactions between intelligent controller 210 and processor 110. For example, the interface of the coherency protocol CACHE may include: three channels containing request, response and data. The non-coherent protocol IO may provide non-coherent loads/stores for I/O devices.

The intelligent controller 210 may be in communication with the memory resource 400 and the processor 110 may be in communication with the host memory 140.

In fig. 4, the configuration of the host 100ab corresponds to the configuration of the host 100a among the plurality of hosts 100a, 100 b. The configuration of each of hosts 100b, 100a, 100k may be substantially the same as the configuration of host 100 ab.

Referring to fig. 4, the host 100ab may include a first operating system OS1 133, a plurality of virtual machines VMa120 and VMb 125, a first switch SW1 131, and an interface controller 135. The first operating system 133 may be driven on the host 100ab and may control or manage the overall operation of the host 100 ab.

According to an example embodiment, the plurality of virtual machines including virtual machine 120 and virtual machine 125 may be virtual systems driven on first operating system 133. The multiple virtual machines may each drive an independent or separate operating system. For example, the virtual machine 120 may include a first virtual CPU vCPU1 121 and a first virtual memory vMEM1 122.

The first virtual CPU 121 may be configured to perform various operations driven by the first virtual machine 120. The first virtual memory 122 may be configured to store data used or generated at the virtual machine 120.

The structure of the virtual machine 125 may be similar to that of the virtual machine 120, and thus a detailed description of the virtual machine 125 will be omitted.

The first switch 131 may be configured to perform functions of arbitrating, switching, or routing various communication requests or various communication data packets. The first switch 131 may be a physical switch or a virtual switch. The first switch 131 may perform a function of arbitrating, switching, or routing various communications between various components (e.g., virtual machines) included in the host 100ab or communications between hosts.

Interface controller 135 may be an interface circuit configured to support a heterogeneous computing interface, such as a CXL interface. According to an example embodiment, the heterogeneous computing interface may be an interface following the CXL protocol, but the disclosure is not limited thereto. For example, the heterogeneous computing interface may be implemented based on at least one of various computing interfaces Gen-Z protocol, NVLink protocol, CCIX protocol, and Open CAPI protocol.

In fig. 5, a configuration of the semiconductor memory device 401a among the plurality of semiconductor memory devices 401a, 402a, 401b, 402b, 40ta, and 40tb is shown, and the configuration of each of the plurality of semiconductor memory devices 402a, 40ta, 401b, 402b, …, and 40tb may be substantially the same as the configuration of the semiconductor memory device 401 a.

Referring to fig. 5, a semiconductor memory device 401a may include a control logic circuit 410, an address register 420, a clock buffer 425, a bank control logic 430, a strobe signal generator 435, a refresh counter 445, a row address multiplexer (RA MUX) 440, a column address latch 450, a row decoder 460, a column decoder 470, a memory cell array 510, a sense amplifier unit 485, an I/O gating circuit 490, an Error Correction Code (ECC) engine 550, and a data I/O buffer 520.

For example, the semiconductor memory device 401a may be a volatile memory device based on a Synchronous Dynamic Random Access Memory (SDRAM) device.

The memory cell array 510 includes first to eighth bank arrays 510a to 510h. The row decoder 460 includes first to eighth bank row decoders 460a to 460h coupled to the first to eighth bank arrays 510a to 510h, respectively, the column decoder 470 includes first to eighth bank column decoders 470a to 470h coupled to the first to eighth bank arrays 510a to 510h, respectively, and the sense amplifier unit 485 includes first to eighth bank sense amplifiers 485a to 485h coupled to the first to eighth bank arrays 510a to 510h, respectively.

The first to eighth bank arrays 510a to 510h, the first to eighth bank row decoders 460a to 460h, the first to eighth bank column decoders 470a to 470h, and the first to eighth bank sense amplifiers 485a to 485h may form first to eighth banks. Each of the first to eighth bank arrays 510a to 510h may include a plurality of memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BTL.

The address register 420 may receive an address ADDR including a BANK address bank_addr, a ROW address row_addr, and a column address col_addr from the intelligent controller 210. Address register 420 may provide a received BANK address BANK ADDR to BANK control logic 430, a received ROW address ROW ADDR to ROW address multiplexer 440, and a received column address COL ADDR to column address latch 450.

The BANK control logic 430 may generate a BANK control signal in response to the BANK address BANK ADDR. One of the first to eighth BANK row decoders 460a to 460h corresponding to the BANK address bank_addr is activated in response to the BANK control signal, and one of the first to eighth BANK column decoders 470a to 470h corresponding to the BANK address bank_addr is activated in response to the BANK control signal.

The ROW address multiplexer 440 may receive the ROW address row_addr from the address register 420 and may receive the refresh ROW address ref_addr from the refresh counter 445. The ROW address multiplexer 440 may selectively output the ROW address row_addr or the refresh ROW address ref_addr as the ROW address RA. The row address RA output from the row address multiplexer 440 is applied to the first to eighth bank row decoders 460a to 460h.

The refresh counter 445 may sequentially increase or decrease the refresh row address ref_addr and may output the refresh row address ref_addr under the control of the control logic circuit 410.

One of the first to eighth bank row decoders 460a to 460h activated by the bank control logic 430 may decode the row address RA output from the row address multiplexer 440 and may activate a word line corresponding to the row address RA. For example, the activated bank row decoder applies a word line driving voltage to the word line corresponding to the row address.

The column address latch 450 may receive the column address col_addr from the address register 420 and may temporarily store the received column address col_addr. According to an example embodiment, in burst mode, column address latch 450 generates column address col_addr' that is incremented from received column address col_addr. The column address latch 450 may apply the temporarily stored column address col_addr or the generated column address col_addr' to the first to eighth bank column decoders 470a to 470h.

The activated one of the first to eighth BANK column decoders 470a to 470h may activate a sense amplifier corresponding to the BANK address bank_addr and the column address col_addr through the I/O gating circuit 490.

The I/O gating circuitry 490 may include circuitry for gating input/output data and further includes input data mask (mask) logic, read data latches for storing data output from the first to eighth bank arrays 510 a-510 h, and write drivers for writing data to the first to eighth bank arrays 510 a-510 h.

The codeword CW read from one of the first to eighth bank arrays 510a to 510h may be sensed by a sense amplifier coupled to one of the bank arrays from which data is to be read and may be stored in a read data latch. The codeword CW stored in the read data latch may be provided to the ECC engine 550, the ECC engine 550 may generate the data DTA by performing ECC decoding on the codeword CW to provide the data DTA to the data I/O buffer 520, the data I/O buffer 520 may convert the data DTA into the data signal DQ, and the data I/O buffer 520 may transmit the data signal DQ to the smart controller 210 together with the data strobe signal DQs.

The data signals DQ to be written to the selected one of the first through eighth bank arrays 510a through 510h may be supplied from the intelligent controller 210 to the data I/O buffer 520. The data I/O buffer 520 may convert the data signal DQ into data DTA and may provide the data DTA to the ECC engine 550. The ECC engine 550 may ECC-encode the data DTA to generate parity bits, and the ECC engine 550 may provide the codeword CW including the data DTA and the parity bits to the I/O gating circuit 490. The I/O gating circuitry 490 may write codeword CW into a sub-page of the selected bank array via a write driver.

The data I/O buffer 520 may provide the data signal DQ from the smart controller 210 to the ECC engine 550 by converting the data signal DQ into the data DTA in a write operation of the semiconductor memory device 401a, and may convert the data DTA from the ECC engine 550 into the data signal DQ and may transmit the data signal DQ and the data strobe signal DQs to the smart controller 210 in a read operation of the semiconductor memory device 401 a.

The ECC engine 550 may perform ECC encoding and ECC decoding on the DTA according to the control of the control logic circuit 410.

The clock buffer 425 may receive the clock signal CK, may generate an internal clock signal ICK by buffering the clock signal CK, and may provide the internal clock signal ICK to the circuit component processing the command CMD and the address ADDR.

The strobe signal generator 435 may receive the clock signal CK, may generate the data strobe signal DQS based on the clock signal CK, and may provide the data strobe signal DQS to the data I/O buffer 520.

The control logic circuit 410 may control the operation of the semiconductor memory device 401 a. For example, the control logic circuit 410 may generate a control signal for the semiconductor memory device 401a to perform a write operation or a read operation. The control logic circuit 410 may include a command decoder 411 that decodes a command CMD received from the smart controller 210 and a mode register 412 that sets an operation mode of the semiconductor memory device 401 a.

For example, the command decoder 411 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, or the like.

Fig. 6 illustrates an example of a first bank array in the semiconductor memory device of fig. 5.

Referring to fig. 6, the first bank array 510a may include a plurality of word lines WL0 to WLm-1 (where m is an even number equal to or greater than 2), a plurality of bit lines BTL0 to BTLn-1 (where n is an even number equal to or greater than 2), and a plurality of memory cells MC disposed at intersections between the word lines WL0 to WLm-1 and the bit lines BTL0 to BTLn-1.

Word lineCan extend in the first direction Dl, bit line +.>May extend in a second direction D2 intersecting the first direction Dl.

Each memory cell MC includes a memory cell coupled to a word lineOne sum bit line-> One of which is an access (cell) transistor and a storage (cell) capacitor coupled to the cell transistor. That is, each memory cell MC has a DRAM cell structure.

Further, the memory cells MC may have different arrangements depending on whether the memory cells MC are coupled to even word lines (e.g., WL0, WL2, WL4, etc.) or odd word lines (e.g., WL1, WL3, WL5, etc.). That is, bit lines coupled to adjacent memory cells may be different according to whether a word line selected by an access address is an even word line or an odd word line. However, the embodiment is not limited thereto. Memory cells MC coupled to even word lines (e.g., WL0, WL2, WL 4) and odd word lines (e.g., WL1, WL3, WL 5) may have the same arrangement.

Referring to fig. 7, the memory cell array 510 may be divided into a plurality of memory blocks (memory blocks) BLK1, BLK2, BLKM. Here, M is an integer greater than 2. Each of the plurality of memory blocks BLK1, BLK2, BLKM may be specified by a corresponding one of the base addresses bs_addr1, bs_addr2, bs_addrm. Each of the base addresses bs_addr1, bs_addr2, and the bs_addrm may correspond to a start address of a respective one of the plurality of memory blocks BLK1, BLK2, and BLKM. Each of the plurality of memory blocks BLK1, BLK2, BLKM may include two or more pages.

In fig. 8, a state diagram of the semiconductor memory device 401a is described as an example, and similar description can be applied to each of the plurality of semiconductor memory devices 402a, …, 40ta, and 401b, 402b, …, 40 tb.

Referring to fig. 8, a semiconductor memory device 401a may be in one of a plurality of operating mode states. For example, the semiconductor memory device 401a may have a total of six operating mode states including an idle state 231, an active mode state 232, a refresh mode state 233, a deep power down mode state 234, a self-refresh mode state 235, and a low power mode state 236. Although six operation mode states are shown in fig. 8, the present disclosure is not limited thereto, and thus, according to other example embodiments, the semiconductor memory device 401a may have various operation mode states depending on the operation of the semiconductor memory device 401 a.

According to an exemplary embodiment, the idle state 231 represents a state when the semiconductor memory device 401a is not operating. That is, when the semiconductor memory device 401a is not accessed. For example, the semiconductor memory device 401a may be in the idle state 231 when there is no command of the intelligent controller 210 (fig. 1), or when the intelligent controller 210 is in the sleep mode.

The active mode state 232 represents a state in which the semiconductor memory device 401a performs normal operations such as reading, writing, and other operations in response to the active command ACT. The active mode state 232 is a state in which the semiconductor memory device 401a exhibits maximum power consumption because all circuits in the semiconductor memory device 401a are enabled. When the normal operation in the active mode state 232 is completed, the semiconductor memory device 401a may automatically transition to the idle state 231.

The refresh mode state 233 represents an auto-refresh state in which the semiconductor memory device 401a refreshes the memory cell rows of the memory cell array 510 in response to the periodic refresh command REF applied by the smart controller 210. In the refresh mode state 233, all circuits may be enabled in consideration of the fact that the clock signal CK of the semiconductor memory device 401a is valid and that the command of the intelligent controller 210 may be issued to the semiconductor memory device 401 a. Accordingly, the power consumption in the refresh mode state 233 may be substantially the same as the power consumption in the active mode state 232. When the refresh operation in the refresh mode state 233 is completed, the semiconductor memory device 401a can automatically transition to the idle state 231.

The deep power down mode state 234 represents a deep power down state in which the semiconductor memory device 401a deactivates most of the circuits in the semiconductor memory device 401a in response to the deep power down command DPD. The deep power down mode state 234 is a state in which the semiconductor memory device 401a exhibits minimum power consumption. In response to the WAKE command WAKE-UP, the semiconductor memory device 401a may enable a circuit that is disabled in the deep power down mode state 234 and may transition to the idle state 231.

The self-refresh mode state 235 represents a self-refresh state in which the semiconductor memory device 401a refreshes a memory cell row of the memory cell array 510 in response to the self-refresh entry command SRE. When a certain period of time passes while the semiconductor memory device 401a is in the idle state 231, the intelligent controller 210 may issue a self-refresh entry command SRE to reduce power consumption of the semiconductor memory device 401 a.

In the self-refresh mode state 235, among the circuits in the semiconductor memory device 401a, circuits directly and indirectly related to the self-refresh operation may be enabled, and other circuits may be disabled. For example, in the self-refresh mode state 235, the clock buffer 425 receiving the clock signal CK from the intelligent controller 210 may be disabled. In the self-refresh mode state 235, a refresh operation may be performed by using an internal counter when the clock signal CK is disabled. Thus, the power consumption in the self-refresh mode state 235 is lower than the power consumption in the active mode state 232 and the refresh mode state 233 in which all circuits are enabled. The semiconductor memory device 401a may exit the self-refresh mode state 235 in response to a self-refresh exit command SRX issued by the smart controller 210.

The low power mode state 236 represents a low power down state in which the power consumption is lower than in the self-refresh mode state 235, although the memory cell rows of the memory cell array 510 are refreshed as in the self-refresh mode. The semiconductor memory device 401a may transition from the self-refresh mode state 235 to the low power mode state 236 in response to a low power state entry command (LPSE).

In the low power mode state 236, among the circuits in the semiconductor memory device 401a, only the circuit directly related to the self-refresh operation is enabled, and other circuits may be disabled. For example, in the low power mode state 236, only the circuitry associated with the internal counter among the circuitry enabled in the self-refresh mode state 235 may be enabled. Accordingly, power consumption in the low power mode state 236 may be further reduced than in the self-refresh mode state 235, as more circuitry is controlled to be disabled in the low power mode state 236 than in the self-refresh mode state 235.

When the self-refresh operation in the low power mode state 236 is completed, the semiconductor memory device 401a may automatically transition to the idle state 231. Here, the semiconductor memory device 401a may automatically exit the low power mode state 236 according to the low power mode exit latency set in the mode register 212 (in fig. 5). The low power mode exit delay time is set so as not to affect the normal operation or idle state of the semiconductor memory device 401a by controlling the semiconductor memory device 401a to exit from the low power mode state 236 early enough. The semiconductor memory device 401a can receive a valid command after the low power mode exit waiting time has elapsed by using an internal counter or a separate counter.

In fig. 8, solid arrows indicate command sequences, and broken arrows indicate automatic sequences.

With reference to figure 9 of the drawings, the hot/cold page analyzer 270 may include a first counter 271, a plurality of second counters 272a, 272b, a first comparator 274, a plurality of second comparators 275a, 275b, a first, 275g, a signal generator 276, a migration manager 280, and a timer 285. Here, g is an integer greater than 2.

The first counter 271 may generate the first count signal CV1 by counting memory requests req_t from at least one of the plurality of hosts 100a, 100b, & gt, 100k during a reference time interval.

The first comparator 274 may generate the first comparison signal CS1 by comparing the first count signal with the first reference value RTH 1. When the first count signal CV1 indicates that the memory request req_t is smaller than the first reference value RTH1, the first comparator 274 may generate the first comparison signal CS1 having a first logic level (logic low level). When the first count signal CV1 indicates that the memory request req_t is equal to or greater than the first reference value RTH1, the first comparator 274 may generate the first comparison signal CS1 having a second logic level (logic high level). According to an example embodiment, the memory request req_t may be the number of memory requests.

The plurality of second counters 272a, 272b, 272g may generate second count signals CV21, CV22, CV2g, respectively, by counting respective memory requests REQ11, REQ12, REQ1g of respective pages of the plurality of memory regions during a reference time interval.

The plurality of second comparators 275a, 275b, 275g may generate a plurality of second comparison signals CS21, CS22, CS2g by comparing the second count signals CV21, CV22, respectively.

When the second count signals CV21, CV22, and CV2g indicate that the memory requests REQ11, REQ12, and REQ1g are each less than the second reference value RTH2, the plurality of second comparators 275a, 275b, and 275g may generate the second comparison signals CS21, CS22, and CS2g having the first logic level. When the second count signals CV21, CV22, …, CV2g indicate that the memory requests REQ11, REQ12, …, REQ1g are each equal to or greater than the second reference value RTH2, the plurality of second comparators 275a, 275b, …, 275g may generate second comparison signals CS21, CS22,..cs 2g having a second logic level.

The signal generator 276 may generate a first enable signal EN1 that activates the plurality of second counters 272a, 272b, & gt, 272g based on the first comparison signal CS1, may provide the first enable signal EN1 to the plurality of second counters 272a, 272b, & gt, 272g, and may also generate the migration control signal MCS based on at least some of the plurality of second comparison signals CS21, CS22, & gt, CS2g having the first logic level.

The migration manager 280 may calculate available data storage capacity of a cold block (cold rank) in the first and second blocks of at least one of the plurality of channels CHl, CH2, CHt, and may selectively perform data migration based on the migration control signal MCS from the signal generator 276 and the available data storage capacity of the cold block. When the migration is performed, the migration manager 280 may provide the remapping engine 300 with the first physical address DPA1 of the cold page of the first block and the second physical address DPA2 of the page of the second block in the channel on which the migration is performed. The remapping engine 300 may map a first physical address DPA1 of a cold page of a first block to a second physical address DPA2 of a page of a second block.

The timer 285 may apply the second enable signal EN2 to the first counter 271 to periodically activate the first counter 271, and may reset the first counter 271 and the plurality of second counters 272a, 272b, 272g by applying a reset signal to the first counter 271 and the plurality of second counters 272a, 272b, 272g after the reference time interval has elapsed.

Thus, the hot/cold page analyzer 270 may periodically monitor hot and cold pages and may periodically perform data migration.

In fig. 10A, 10B, and 10C, the plurality of semiconductor memory devices 401a, 402a, 40ta, and 401B, 402B, 40tb may be allocated to the first block RNK and the second block RNK2 of each of the plurality of channels CH1, CH2, CHt, such that each of the plurality of semiconductor memory devices 401a, 402a, 40ta and a corresponding one of the plurality of semiconductor memory devices 401B, 402B, 40tb belong to different channels.

The semiconductor memory device 401a (first semiconductor memory device) among the semiconductor memory devices 401a and 401b connected to the channel CHl is allocated to the first block RNKl, and the semiconductor memory device 401b (second semiconductor memory device) among the semiconductor memory devices 401a and 401b connected to the channel CHl is allocated to the second block RNK. The semiconductor memory devices 402a among the semiconductor memory devices 402a and 402b connected to the channel CH2 are allocated to the first block RNK1, and the semiconductor memory devices 402b among the semiconductor memory devices 402a and 402b connected to the channel CH2 are allocated to the second block RNK. The semiconductor memory devices 40ta of the semiconductor memory devices 40ta and 40tb connected to the channel CHt are allocated to the first block RNK, and the semiconductor memory devices 40tb of the semiconductor memory devices 40ta and 40tb connected to the channel CHt are allocated to the second block RNK2.

Referring to fig. 10A, when virtual machines VM1, VM2, and VM3 are driven in a plurality of hosts 100A, 100b, & gt, 100k, a remapping engine 300 allocates virtual machines VM1, VM2, and VM3 to a plurality of channels CH1, CH2, & gt, a first tile RNK of CHt, and to a portion of a second tile RNK2 to dynamically use memory bandwidth and reduce power consumption.

Referring to fig. 10B, when a partial host among the plurality of hosts 100a, 100B, & gt, 100k requests to deallocate the virtual machine VM3, the remapping engine 300 deallocates the virtual machine VM3 from the second block RNK2, and the power management engine 220 enters the semiconductor storage devices 401B, 402B, & gt, 40tb belonging to the second block RNK2 into a deep power down mode.

Referring to fig. 10C, when a part of the plurality of hosts 100a, 100b,..100 k requests allocation of the virtual machine VM5, the remapping engine 300 allocates the virtual machine VM5 to a part of the second block RNK2, and the power management engine 220 causes the semiconductor storage devices 401b, 402b,..40 tb belonging to the second block RNK to exit the deep power down mode.

In fig. 11, the operation of the hot/cold page analyzer 270 is shown for the semiconductor memory device 401a connected to the channel CH1 and belonging to the first block RNK and the semiconductor memory device 401b connected to the channel CH1 and belonging to the second block RNK 2.

Referring to fig. 9 and 11, when a memory request req_t from at least one of the plurality of hosts 100a, 100b, & gt, 100k is less than a first reference value RTH1 during a reference time interval, the hot/cold page analyzer 270 performs monitoring of hot and cold pages of the semiconductor memory devices 401a in the first block RNK1 and 401b in the second block RNK, determines some pages of the semiconductor memory devices 401a as cold pages when respective memory requests for some pages of the semiconductor memory devices 401a are less than a second reference value RTH2, determines whether an available data storage capacity of the semiconductor memory devices 401b in the second block RNK is equal to or greater than a size of the cold pages of the semiconductor memory devices 401a, and performs data migration to migrate the available data storage capacity of the semiconductor memory devices 401b in the second block RNK to the cold pages of the semiconductor memory devices 401a as indicated by a blank data of the semiconductor memory devices 401 b.

After the data migration is completed, the power management engine 220 may put the semiconductor memory device 401b in the second block RNK into the self-refresh mode.

According to another example embodiment, when a cold page migrated to the semiconductor storage device 401b in the second block RNK is migrated to another block (e.g., a third block), the power management engine 220 may put the semiconductor storage device 401b of the second block RNK into a deep power down mode.

In fig. 12, memory resources 400 are shown together for ease of illustration.

Referring to fig. 12, the remapping engine 300 may include a control manager 310, a remapping cache 320, a host address table 330, a set of block address tables 340, a remapping table 360, a bandwidth analyzer 370, and a channel utilization count table 380.

The remapping cache 320 may store a part of the mapping relationship among the total mapping relationship between the host physical addresses of the plurality of hosts 100a, 100b,..and 100k and the memory blocks of the plurality of semiconductor memory devices 401a, 402a,..40 ta and 401b, 402b,..40 tb.

The host address table 330 may store a host block table for a plurality of hosts 100a, 100b, 100 k. The block address table group 340 may store block base addresses, each corresponding to a start address of a corresponding storage block in the plurality of semiconductor memory devices 401a, 402a,..40 ta and 401b, 402b,..40 tb, and the block base addresses are respectively referenced by the host block table. Remap table 360 may store device physical addresses specified by block base addresses.

The bandwidth analyzer 370 may monitor the utilization of the memory blocks of the semiconductor memory devices 401a, 402a, 40ta and 401b, 402b, 40tb for each channel accessed through the device physical address DPA of the remapping table 360, and may record the monitoring result for each channel in the channel utilization count table 380.

In response to the occurrence of a cache miss in a first host among the plurality of hosts 100a, 100b, the first host, 100k, the remapping engine 300 may receive a host physical address HPA including a host identifier HID for identifying the first host and a device logical address DLA for accessing one of the plurality of semiconductor memory devices 401a, 402a, the first host, 40ta and 401b, 402b, the first host, 40tb, and may access a memory block of one of the plurality of semiconductor memory devices 401a, 402a, the first host, 40ta and 401b, 402b, the first host, 40tb based on the host identifier HID and the device logical address DLA.

The control manager 310 may search the physical address of the target memory block specified by the device logical address DLA by referencing the remapping cache 320, the host address table 330, the set of block address tables 340, and the remapping table 360.

For example, when a cache miss occurs in a first host among the plurality of hosts 100a, 100b,..100 k, the control manager 310 may search for a physical address of the target memory block corresponding to the host identifier HID by referring to the remapping cache 320, and may access the memory resource 400 based on the searched physical address in response to the occurrence of the cache hit in the remapping cache 320, as indicated by reference numeral 573.

In response to a cache miss occurring in remapping cache 320, control manager 310 may search host-block table 330 of the first host based on host identifier HID of the first host, as represented by reference numeral 575, may search block-address table set 340 for a block-base address of the target storage block based on the host-block table of the first host, as represented by reference numeral 581, and may obtain physical address DPA of the target storage block in remapping table 360 based on the block-base address of the target storage block, as represented by reference numeral 583.

Referring to fig. 13, the remapping cache 320 may include a first column 321 and a second column 323. The first column 321 may store host physical addresses HPA1, HPA2, …, HPAr of some of the plurality of hosts 100a, 100b, …, 100k, and the second column 323 may store device physical addresses DPA1, DPA2, DPAr corresponding to the host physical addresses HPA1, HPA2, HPAr. Here, r is an integer greater than 2.

Referring to fig. 14, the HOST address TABLE 330 may include a plurality of rows 331, 332, 33K, and each of the plurality of rows 331, 332, 33K may store a corresponding HOST BLOCK TABLE of the HOST BLOCK TABLEs HOST1BLOCK TABLE, HOST2 BLOCK TABLE, HOST, HOSTK BLOCK TABLE, which may be specified by the HOST identifier HID, of the plurality of HOSTs 100a, 100 b.

Referring to fig. 15, the BLOCK address TABLE group 340 may include a plurality of BLOCK address TABLEs 340a, 340b, 340k corresponding to HOST BLOCK TABLEs HOST1BLOCK TABLE, HOST2 BLOCK TABLE, HOSTK BLOCK TABLE in fig. 14.

Each of the plurality of BLOCK address TABLEs 340a, 340b, 340k may include a plurality of rows 341, 342, 34M, and each of the plurality of rows 341, 342, 34M may store a respective BLOCK base address of the BLOCK base addresses blk1_bs_addr, blk2_bs_addr, blkm_bs_addr, each corresponding to a start address of a corresponding memory BLOCK of the plurality of semiconductor memory devices 401a, 402a, 40ta, and 401b, 402b, blk2_bs_addr, blkm_bs_addr, respectively, referenced by HOST BLOCK TABLEs HOST1BLOCK TABLE, HOST2 BLOCK TABLE, HOSTK BLOCK TABLE.

Referring to fig. 16, the remapping cache 360 may store device physical addresses DPA11, DPA12, DPA21, DPA22, as specified by block base addresses blk1_bs_addr, blk2_bs_addr. Device physical addresses DPA11 and DPA12 may correspond to HOST block HOST1_blk1, and device physical addresses DPA21 and DPA22 may correspond to HOST block HOST2_blk2.

Referring to fig. 17, a channel utilization count table 380 may include a plurality of columns 381, 382, 383.

Column 381 may store host identifiers HID1, HID2, HIDK for identifying multiple hosts 100a, 100b, respectively.

The columns 382, 383, …, 38t may store channel utilization count values for each of the channels CHl, CH2, …, CHt for the plurality of hosts 100a, 100b, …, 100 k.

Column 382 may store channel utilization count values UT11, UT21, UTK1 for multiple hosts 100a, 100b, 100 k. Column 383 may store channel utilization count values UT12, UT22, UTK2 for multiple hosts 100a, 100b, 100 k. Column 38t may store lane utilization count values UT1t, UT2t, for multiple hosts 100a, 100b,..100 k of lanes CHt.

In fig. 18, it is assumed that a cache miss occurs in the host 100b among the plurality of hosts 100a, 100b,..100 k.

Referring to fig. 1 and 2-18, when a cache miss occurs in host 100b, host 100b may provide host physical address HPA2, including host identifier HID2 and device logical address DLA2 of host 100b, to remapping engine 300 via CXL bus 50.

The control manager 310 may search for the physical address of the target memory block corresponding to the host identifier HID2 by referring to the remapping cache 320 and may access the memory resource 400 based on the searched physical address in response to a cache hit occurring in the remapping cache 320. For example, as shown by reference numeral 573a, control manager 310 can access memory resource 400 based on a searched physical address in response to a cache hit occurring in remap cache 320.

In response to a cache miss occurring in remapping cache 320, control manager 310 may search HOST BLOCK TABLE HOST2 BLOCK of HOST 100b in HOST address TABLE 330 based on HOST identifier HID2 of HOST 100b, as indicated by reference numeral 575 a; the BLOCK base address blk2_bs_addr of the target memory BLOCK may be searched in the BLOCK address TABLE BAT2 in the BLOCK address TABLE group 340 based on the HOST BLOCK TABLE HOST2 BLOCK TABLE of the HOST 100b, as indicated by reference numeral 581 a; the physical address DPA22 of the target memory block may be obtained in the remap table 360 based on the block base address blk2_bs_addr of the target memory block, as indicated by reference numeral 583a, and the memory resource 400 may be accessed based on the physical address DPA22, as indicated by reference numeral 585 a.

Referring to fig. 1, 10A, 10B, 10C, and 19, a method of operating a memory system 200 including an intelligent controller 210 and a memory resource 400 is provided. The memory resource 400 includes a plurality of semiconductor memory devices DRAM 401a, 402a, 40ta and 401b, 402b, 40tb, which are connected to each other through an internal bus IBUS. The intelligent controller 210 may be connected to the plurality of semiconductor memory devices 401a, 402a, 40ta and 401b, 402b, 40tb through a plurality of channels CH1, CH2, CHt. For each of the plurality of channels CH1, CH2, CHt, the plurality of semiconductor memory devices 401a, 402a, 40ta, and 401b, 402b, 40tb are divided into a first semiconductor memory and a second semiconductor memory device belonging to different blocks. The smart controller 210 may be connected to the plurality of hosts 100a, 100b, & gt, 100k through the CXL bus 50, and control the plurality of semiconductor memory devices 401a, 402a, & gt, 40ta and 401b, 402b, & gt, 40tb by communicating with the plurality of hosts 100a, 100b, & gt, 100k driving at least one virtual machine, respectively, through the CXL interface.

According to the method, the remapping engine 300 in the intelligent controller 210 assigns the virtual machines VM1, VM2, and VM3 to the same tile for each of the plurality of channels CH1, CH2, CHt (operation S110).

The power management engine 220 in the intelligent controller 210 may control the power mode of the memory resource 400 at a block level based on allocation of the additional virtual machine and de-allocation of at least one of the virtual machines VM1, VM2, and VM3 (operation S130).

Referring to fig. 1, 8, 9, 11, and 20, a method of operating a memory system 200 including an intelligent controller 210 and a memory resource 400 is provided. The memory resource 400 includes a plurality of semiconductor memory devices DRAM 401a, 402a, 40ta and 401b, 402b, 40tb, which are connected to each other through an internal bus IBUS. The intelligent controller 210 may be connected to the plurality of semiconductor memory devices 401a, 402a, 40ta and 401b, 402b, 40tb through a plurality of channels CH1, CH2, CHt. For each of the plurality of channels CH1, CH2, CHt, the plurality of semiconductor memory devices 401a, 402a, 40ta, and 401b, 402b, 40tb are divided into a first semiconductor memory and a second semiconductor memory device belonging to different blocks. The smart controller 210 may be connected to the plurality of hosts 100a, 100b, & gt, 100k through the CXL bus 50, and control the plurality of semiconductor memory devices 401a, 402a, & gt, 40ta and 401b, 402b, & gt, 40tb by communicating with the plurality of hosts 100a, 100b, & gt, 100k driving at least one virtual machine, respectively, through the CXL interface.

According to an example embodiment, the method includes determining whether a memory request req_t from at least one of the plurality of hosts 100a, 100b, 100k during a reference time interval is less than a first reference value RTH1 (operation S210). According to an example embodiment, the hot/cold page analyzer 270 in the intelligent controller 210 may determine whether a memory request req_t from at least one of the plurality of hosts 100a, 100b, 100k during a reference time interval is less than a first reference value RTH1 (operation S210).

In operation (S220), when the memory request req_t from at least one host is equal to or greater than the first reference value RTHl (no in operation S210), the hot/cold page analyzer 270 stops hot/cold page monitoring.

In operation (S230), when the memory request req_t from at least one host is less than the first reference value RTHl (yes in operation S210), the hot/cold page analyzer 270 enables hot/cold page monitoring.

In operation (S240), the hot/cold page analyzer 270 performs hot/cold page monitoring on the memory regions of the plurality of semiconductor memory devices 401a, 402 a..40 ta and 401b, 402b,..40 tb, by using the plurality of second counters 272a, 272b,..272 g and the plurality of second comparators 275a, 275b,..275 g.

In operation (S250), the migration manager 280 in the hot/cold page analyzer 270 collects cold pages into one block (cold block) in each of the plurality of channels CHl, CH2, CHt based on the result of the hot/cold page monitoring.

In operation (S260), the power management engine 220 in the intelligent controller 210 sets the cold block to the self-refresh mode at run-time.

As described above, the intelligent controller in the memory system and the computing system according to the example embodiments allocates virtual machines to the plurality of semiconductor memory devices 401a, 402a, the..40 ta and 401b, 402b, the..40 tb at a block level, causes a block to which no virtual machine is allocated to enter a deep power down mode, divides the memory areas of the plurality of semiconductor memory devices 401a, 402a, the..40 ta and 401b, 402b, the..40 tb into a hot page or a cold page based on a memory request to the plurality of semiconductor memory devices 401a, 402a, the..40 ta and 401b, 402b, the..40 tb, migrates cold data of a cold page of one block to another block, causes a cold block including the cold page to enter a self-refresh mode, and thereby controls a power mode of the memory resource 400 at a block level.

FIG. 21 is an example of a computing system when the memory system according to an example embodiment corresponds to a Type 3 (Type 3) memory system defined by the CXL protocol.

Referring to FIG. 21, computing system 600 may include a root complex 610, a CXL memory extender 620 connected to root complex 610, and memory resources 630.

Root complex 610 may include a home agent 611 and an I/O bridge 613, and home agent 610 may communicate with CXL memory expander 620 based on a coherence protocol cxl.mem, and I/O bridge 613 may communicate with CXL memory expander 620 based on a non-coherence protocol (i.e., I/O protocol cxl.io). In the CXL protocol base, the home agent 610 may correspond to a host-side agent that is arranged to address the overall consistency of the computing system 600 for a given address.

The CXL memory expander 620 can include a smart controller 621, and the smart controller 621 can employ the smart controller 210 of fig. 1.

Furthermore, CXL memory extender 620 may output data to root complex 610 via I/O bridge 613 based on the I/O protocol CXL.io or PCIe.

The memory resource 630 may include a plurality of memory regions MR1, MR2, MRt, and each of the plurality of memory regions MR1, MR2, MRt may be implemented as various units of memory.

Referring to fig. 22, a semiconductor memory device 700 may include at least one buffer die 710 and a plurality of memory dies 720-1 through 720-p (p is a natural number equal to or greater than 3) in a stacked chip structure that provides soft error analysis and correction functions.

Multiple memory dies 720-1 through 720-p are stacked on buffer die 710 and data is transferred through multiple Through Silicon Via (TSV) lines.

Each memory die 720-1 through 720-p may include a unit core 721 to store data and a unit core ECC engine 723 to generate transmission parity bits (i.e., transmission parity data) based on the transmission data to be sent to the at least one buffer die 710. The cell core 721 may include a plurality of memory cells having a DRAM cell structure.

The buffer die 710 may include a pass-through ECC engine 712, which ECC engine 712 uses the transmission parity bits to correct transmission errors and generates error-corrected data when a transmission error is detected from the transmission data received over the TSV line.

The buffer die 711 may also include a receiver 713 and a transmitter 714.

The semiconductor memory device 700 may be a stacked chip type memory device or a stacked memory device that transmits data and control signals through TSV lines. The TSV lines may also be referred to as "through electrodes".

The unit core ECC engine 723 may perform error correction on the data output from the memory die 720-p before the transmission data is sent.

Transmission errors occurring at the transmitted data may be due to noise occurring at the TSV line. Data failures due to noise occurring at the TSV lines can be distinguished from data failures due to erroneous operation of the memory die, and thus can be considered soft data failures (or soft errors). Soft data failures may occur due to transmission failures on the transmission path and may be detected and corrected by ECC operations.

Through the above description, the data TSV wire group 732 formed at one memory die 720-p may include TSV wires Ll and L2 through Lp, and the parity TSV wire group 734 may include TSV wires Ll0 through Lq.

The TSV lines Ll and L2 through Lp in the data TSV line group 732 and the parity TSV lines Ll0 through Lq in the parity TSV line group 734 may be connected to micro bumps MCB that are respectively formed between the memory dies 720-1 through 720-p.

At least one of the memory dies 720-1 through 720-p can include DRAM cells, each DRAM cell including at least one access transistor and one storage capacitor.

The semiconductor memory device 700 may have a three-dimensional (3D) chip structure or a 2.5D chip structure in communication with a host through the data bus B10. The buffer die 710 may be connected to a memory controller through a data bus B10.

The unit core ECC engine 723 may output transmission parity bits and transmission data through the parity TSV line group 734 and the data TSV line group 732, respectively. The output transmission data may be data error-corrected by the unit core ECC engine 723.

The lane ECC engine 712 may determine whether a transmission error occurred at the transmission data received through the data TSV line set 732 based on the transmission parity bits received through the parity TSV line set 734. When a transmission error is detected, the lane ECC engine 712 may correct the transmission error of the transmission data using the transmission parity bits. When the transmission error is uncorrectable, the lane ECC engine 712 may output information indicating that an uncorrectable data error occurred.

The semiconductor memory device 700 is a high data storage capacity memory, and each of the plurality of semiconductor memory devices 401a, 402a, 40ta, and 401b, 402b, 40tb may include the semiconductor memory device 700 of fig. 22.

Referring to fig. 23, a data center 2000 may be a facility that collects various types of data and provides various services, and may be referred to as a data storage center. The data center 2000 may be a system for operating search engines and databases, or may be a computing system used by an enterprise such as a bank or government agency. The data center 2000 may include application servers 2100_1 to 2100_u and storage servers 2200_1 to 2200_v. The number of application servers 2100_1 to 2100_u and the number of storage servers 2200_1 to 2200_v may be selected differently according to example embodiments, and the number of application servers 2100_1 to 2100_u and the number of storage servers 2200_1 to 2200_v may be different from each other.

Next, for convenience of description, an example of the storage server 2200_1 will be described.

The storage server 2200_1 may include a processor 2210_1, a memory 2220_1, a switch 2230_1, a Network Interface Controller (NIC) 2240_1, a storage device 2250_1, and a CXL interface 2260_1. The storage server 2200_v may include a processor 2210_v, a memory 2220_v, a switch 2230_v, a NIC 2240_v, a storage device 2250_v, and a CXL interface 2260_v.

The processor 2210_1 may control the overall operation of the storage server 2200_1. The memory 2220_1 may store various instructions or data under the control of the processor 2210_1. The processor 2210_1 may be configured to access the memory 2220_1 to execute various instructions or process data. In an embodiment, the memory 2220_1 may include at least one of various memory devices such as: dual data rate synchronization DRAM (DDR SDRAM), high Bandwidth Memory (HBM), hybrid Memory Cube (HMC), dual Inline Memory Module (DIMM), optane DIMM, or nonvolatile DIMM.

In an embodiment, the number of processors 2210_1 included in the storage server 2200_1 and the number of memories 2220_1 included in the storage server 2200_1 may be variously changed or modified. In an embodiment, the processor 2210_1 and the memory 2220_1 included in the storage server 2200_1 may constitute a processor-memory pair, and the number of processor-memory pairs included in the storage server 2200_1 may be variously changed or modified. In an embodiment, the number of processors 2210_1 included in the storage server 2200_1 may be different from the number of memories 2220_1 included in the storage server 2200_1. The processor 2210_1 may include a single core processor and a multi-core processor.

Under the control of processor 2210_1, switch 2230_1 may selectively connect processor 2210_1 with storage device 2250_1, or may selectively connect NIC 2240_1, storage device 2250_1, and CXL interface 2260_1.

The NIC 2240_1 may connect the storage server 2220_1 with the network NT. NIC 2240_1 may include a network interface card, a network adapter, and the like. NIC 2240_1 may be connected to network NT through a wired interface, a wireless interface, a bluetooth interface, or an optical interface. NIC 2240_1 may include an internal memory, a Digital Signal Processor (DSP), a host bus interface, etc., and may be connected with processor 2210_1 or switch 2230_1 through the host bus interface. The host bus interface may include at least one of various interface schemes such as: advanced Technology Attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small Computer System Interface (SCSI), serial Attached SCSI (SAS), peripheral Component Interconnect (PCI), PCI express (PCIe), NVMe, computing express link (Compute Express Link) (CXL), IEEE 1394, universal Serial Bus (USB), secure Digital (SD) card interface, multimedia card (MMC) interface, embedded MMC (eMMC) interface, universal Flash (UFS) interface, embedded UFS (UFS) interface, compact Flash (CF) card interface, and the like. In an embodiment, NIC 2240_1 may be integrated with at least one of processor 2210_1, switch 2230_1, and storage device 2250_1.

The storage device 2250_1 may store data or may output the stored data under the control of the processor 2210_1. The memory device 2250_1 may include a controller CTRL 2251_1, a nonvolatile memory NAND 2252_1, a DRAM 2253_1, and an interface I/F2254_1. In an embodiment, the storage device 2250_1 may further comprise a security element SE for security or privacy. The memory device 2250_v may include a controller CTRL 2251_v, a nonvolatile memory NAND 2252_v, a DRAM 2253_v, and an interface I/F2254_v. In an embodiment, the storage device 2250—v may further comprise a security element SE for security or privacy.

The controller 2251_1 may control the overall operation of the memory device 2250_1. The controller 2251_1 may include SRAM. In response to a signal received through the interface 2254_1, the controller 2251_1 may store data in the nonvolatile memory 2252_1 or may output data stored in the nonvolatile memory 2252_1. The controller 2251_1 may be configured to control the nonvolatile memory 2252_1 based on a Toggle interface or ONFI.

The DRAM 2253_1 may be configured to temporarily store data to be stored in the nonvolatile memory 2252_1 or data read from the nonvolatile memory 2252_1. The DRAM 2253_1 may be configured to store various data (e.g., metadata and mapping data) necessary for the operation of the controller 2251_1. The interface 2254_1 may provide a physical connection between the controller 2251_1 and the processor 2210_1, the switch 2230_1, or the NIC 2240_1. The interface 2254_1 may be implemented to support a direct connection storage (DAS) approach that allows direct connection of the storage device 2250_1 through a dedicated cable. The interface 2254_1 may be implemented by a host interface bus based on at least one of the above-described various interfaces.

The above-described components of the storage server 2200_1 are provided as examples only, and the present disclosure is not limited thereto. The above-described components of the storage server 2200_1 may be applied to each of the other storage servers or each of the application servers 2100_1 to 2100_u. In each of the application servers 2100_1 through 2100_u, the storage device 2150_1 may be selectively omitted.

The application server 2100_1 can include a processor 2110_1, a memory 2120_1, a switch 2130_1, a NIC 2140_1, and a CXL interface 2160_1. The application server 2100_u can include a processor 2110_u, a memory 2120_u, a switch 2130_u, a NIC 2140_u, and a CXL interface 2160_u.

The application servers 2100_1 through 2100_u and the storage servers 2200_u through 2200_v may communicate with each other through the network NT. The network NT may be implemented using a Fibre Channel (FC) or an ethernet. FC may be a medium for relatively high-speed data transmission and may use an optical switch that provides high performance and/or high availability. The storage servers 2200_1 to 2200_v may be set as file storage, block storage, or object storage according to an access scheme of the network 3300.

In some example embodiments, the network NT may be a storage-only network or a storage-specific network, such as a Storage Area Network (SAN). For example, the SAN may be a FC-SAN using a FC network and implemented according to the FC protocol (FCP). As another example, the SAN may be an IP-SAN implemented using a Transmission control protocol/Internet protocol (TCP/IP) network and according to SCSI over iSCSI (SCSI over TCP/IP) or Internet SCSI protocol. In another example embodiment, the network NT may be a general purpose network such as a TCP/IP network. For example, the network NT may be implemented according to at least one oF protocols such as FC over ethernet (FCoE), network Attached Storage (NAS), fast nonvolatile storage over fabric (NVMe) (NVMe-orf), and the like. .

In example embodiments, at least one of the plurality of application servers 2100_1 to 2100_u may be configured to access at least one of the remaining application servers or at least one of the storage servers 2200_1 to 2200_v via the network NT.

For example, the application server 2100_1 may store data requested by a user or client in at least one of the storage servers 2200_1 to 2200_v via the network NT. Alternatively, the application server 2100_1 may obtain data requested by a user or client in at least one of the storage servers 2200_1 to 2200_v via the network NT. In this case, the application server 2100_1 may be implemented with a web server, a database management system (DBMS), or the like.

The application server 2100_1 can access the memory 2120_1 or the storage 2150_1 of the application server 2100_1 or the storage 2250_1 of the storage server 2200_1 via the network NT. In this way, the application server 2100_1 can perform various operations on data stored in the application servers 2100_1 to 2100_u and/or the storage servers 2200_1 to 2200_v. For example, the application server 2100_1 may execute commands for moving or copying data between the application servers 2100_1 through 2100_u and/or the storage servers 2200_1 through 2200_v. The data may be transferred from the storage devices 2250_1 to 2250_v of the storage servers 2200_1 to 2200_v directly to the memories 2120_1 to 2120_u of the application servers 2100_1 to 2100_u, or transferred to the memories 2120_1 to 2120_u of the application servers 2100_1 to 2100_u through the memories 2220_1 to 2220_v of the storage servers 2200_1 to 2200_v. For example, the data transmitted through the network NT may be data encrypted for security or privacy.

The storage servers 2200_1 to 2200_v and the application servers 2100_1 to 2100_u can be connected to the memory extender 2300 through CXL interfaces 2260_1 to 2260_v and 2160_1 to 2160_u. The memory extender 2300 may be used as an extended memory of each of the storage servers 2200_1 to 2200_v and the application servers 2100_1 to 2100_u, or virtualized components included in the memory extender 2300 may communicate with the memory extender 2300 through the CXL interfaces 2260_1 to 2260_v and 2160_1 to 2160_u.

The present disclosure may be applied to a variety of electronic devices and systems including high storage capacity storage devices. For example, the present disclosure may be applied to systems such as: personal Computers (PCs), server computers, data centers, workstations, cell phones, smartphones, tablet computers, laptops, personal Digital Assistants (PDAs), portable Multimedia Players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, internet of things (IoT) devices, internet of everything (IoE) devices, electronic book readers, virtual Reality (VR) devices, augmented Reality (AR) devices, robotic devices, drones, and the like.

The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the claims.

Claims

1. A memory system, comprising:

a memory resource including a plurality of semiconductor memory devices coupled to each other through an internal bus, the plurality of semiconductor memory devices being divided into a first semiconductor memory and a second semiconductor memory for each of a plurality of channels, the first semiconductor memory and the second semiconductor memory belonging to different blocks; and

a controller connected to the plurality of semiconductor memory devices through the plurality of channels, the controller configured to control the plurality of semiconductor memory devices based on communicating with a plurality of hosts through a CXL interface, each of the plurality of hosts configured to drive at least one virtual machine, wherein the CXL is a computational fast link,

Wherein the controller is configured to: the power mode of the memory resource is controlled by managing free memory regions among a plurality of memory regions of the plurality of semiconductor memory devices at a block level without intervention of the plurality of hosts, the plurality of memory regions configured to store data.

2. The memory system of claim 1, wherein the free memory region corresponds to a memory region of the plurality of memory regions that does not store the data or a memory region having a data access frequency less than a reference frequency during a reference time interval.

3. The memory system of claim 1, wherein the controller comprises:

a hot/cold page analyzer configured to: based on the total memory traffic requested from at least one host among the plurality of hosts being less than a first reference value,

monitoring a cold page and a hot page among a plurality of pages of the plurality of semiconductor memory devices, the cold page storing cold data having a data access frequency less than a reference frequency during a reference time interval, the hot page storing hot data having the data access frequency equal to or greater than the reference frequency during the reference time interval, and

Performing data migration based on a result of the monitoring to migrate one or more cold pages of a first block of a first channel among the plurality of channels to a second block of the first channel;

a power management engine configured to control the power mode of the memory resource based on whether the data migration is performed; and

a remapping engine configured to: in response to the data migration being performed, mapping a first physical address of the one or more cold pages of the first block of the first channel to a second physical address of a page in the second block of the first channel.

4. The memory system of claim 3, wherein the power management engine is further configured to: the second block of the first channel is put into a deep power down mode when the data migration is performed and when one or more cold pages of the second block of the first channel are migrated to a third block.

5. The memory system of claim 3, wherein the power management engine is further configured to: the second block of the first channel is caused to enter a self-refresh mode when the data migration is performed and when one or more cold pages of the second block of the first channel are not migrated to a third block.

6. The memory system of claim 3, wherein the power management engine is further configured to: the second block of the first channel is put into a self-refresh mode when the data migration is not performed because the available data storage capacity of the second block of the first channel is less than the size of a cold page of the first block of the first channel.

7. The memory system of claim 3, wherein the hot/cold page analyzer comprises:

a first counter configured to: generating a first count signal by counting a number of memory requests from the at least one host during the reference time interval;

a first comparator configured to: generating a first comparison signal by comparing the first count signal with the first reference value;

a plurality of second counters configured to: generating second count signals by counting respective memory requests of pages of the plurality of memory regions during the reference time interval, respectively;

a plurality of second comparators configured to: generating a plurality of second comparison signals by comparing the second count signals with second reference values, respectively;

A signal generator configured to:

generating a first enable signal activating the plurality of second counters based on the first comparison signal, and

generating a migration control signal based on the plurality of second comparison signals; and

a migration manager configured to:

calculating the available data storage capacity of the cold block of the first block and the second block for at least one of the plurality of channels, and

the data migration is selectively performed based on the migration control signal and the available data storage capacity of the cold block.

8. The memory system of claim 7, wherein the migration manager is further configured to: the data migration is not performed based on the available data storage capacity of the second block being less than a size of the one or more cold pages of the first block of the first channel.

9. The memory system of claim 7, wherein the migration manager is further configured to: the data migration is performed based on an available data storage capacity of the second block being equal to or greater than a size of the one or more cold pages of the first block of the first channel.

10. The memory system of claim 7, wherein the hot/cold page analyzer further comprises a timer configured to:

periodically applying a second enable signal to the first counter to activate the first counter, and

after the reference time interval has elapsed, the first counter and the plurality of second counters are reset by applying a reset signal to the first counter and the plurality of second counters.

11. The memory system of claim 3, wherein the remapping engine is further configured to: assigning the at least one virtual machine running on each of the plurality of hosts to the same block of each of the plurality of channels,

wherein the power management engine is further configured to: based on the allocation of additional virtual machines and the deallocation of the at least one virtual machine, causing the free memory region to enter a deep power down mode or causing the free memory region to exit the deep power down mode,

wherein the hot/cold page analyzer is further configured to periodically monitor the hot page and the cold page.

12. The memory system of claim 11, wherein the different blocks comprise a first block and a second block,

Wherein the power management engine is further configured to: the second block of each of the plurality of channels is brought into the deep power down mode based on the remapping engine assigning the at least one virtual machine running on each of the plurality of hosts to the first block of each of the plurality of channels.

13. The memory system of claim 3, wherein the remapping engine is configured to: based on a cache miss occurring in a first host among the plurality of hosts,

receiving a host physical address, the host physical address including a host identifier for identifying the first host and a device logical address for accessing one of the plurality of semiconductor memory devices; and is also provided with

Based on the host identifier and the device logical address, a memory block of one of the plurality of semiconductor memory devices is accessed.

14. The memory system of claim 13, wherein the remapping engine comprises:

a remapping cache, the remapping cache configured to: storing a part of mapping relations among the total mapping relations between host physical addresses of the plurality of hosts and memory blocks of the plurality of semiconductor memory devices;

A host address table configured to store host block tables of the plurality of hosts;

a block address table group configured to store block base addresses, each block base address corresponding to a start address of a corresponding one of the memory blocks of the plurality of semiconductor memory devices, the block base addresses being referenced by the host block table, respectively;

a remapping table, the remapping table configured to: storing a device physical address specified by the block base address; and

a control manager configured to: searching a physical address of a target memory block specified by the device logical address by referencing the remapping cache, the host address table, the set of block address tables, and the remapping table.

15. The memory system of claim 14, wherein the control manager is further configured to: searching the physical address of the target memory block by referencing the remap cache and configured to: in response to a cache hit occurring in the remap cache, the memory resource is accessed based on the physical address searched.

16. The memory system of claim 14, wherein the control manager is further configured to:

searching the physical address of the target memory block corresponding to the host identifier of the first host by referencing the remap cache, and

based on a cache miss occurring in the remap cache:

searching a host block table of the first host in the host address table based on the host identifier of the first host;

searching the block base address of the target storage block in the block address table group based on the host block table of the first host; and

the physical address of the target memory block is obtained in the remapping table based on the block base address of the target memory block.

17. The memory system of claim 1, wherein the memory system comprises a type 3 memory system defined by a CXL protocol.

18. A computing system, comprising:

a plurality of hosts, each host of the plurality of hosts configured to drive at least one virtual machine; and

a memory system configured to process memory requests from the plurality of hosts based on communicating with the plurality of hosts through a CXL interface, wherein the CXL is a computational fast link,

Wherein the memory system comprises:

a controller connected to the plurality of semiconductor memory devices through the plurality of channels, the controller configured to control the plurality of semiconductor memory devices based on communication with the plurality of hosts through the CXL interface,

wherein the controller is configured to: controlling a power mode of the memory resource by managing free memory regions among a plurality of memory regions of the plurality of semiconductor memory devices at a block level, the plurality of memory regions configured to store data,

wherein the free memory area corresponds to a memory area of the plurality of memory areas that does not store the data, or a memory area having an access frequency less than a reference frequency during a reference time interval.

19. The computing system of claim 18, wherein the plurality of hosts each comprise at least one of a graphics processing unit, a neural processing unit, a field programmable gate array, a network interface card, or a peripheral device that communicates based on a CXL protocol.

20. A memory system, comprising:

Wherein the controller includes a hot/cold page analyzer,

wherein the hot/cold page analyzer is configured to: based on the total memory traffic requested from at least one host among the plurality of hosts being less than a first reference value,

data migration is performed based on a result of the monitoring to migrate one or more cold pages of a first block of a first channel among the plurality of channels to a second block of the first channel.