JPH0785357B2 - DRAM refresh controller - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (dynamic random access memory) used as a shared memory by a multi-processing apparatus having a plurality of processing elements in which a processor and a cache memory are mounted, for a certain period of time. The present invention relates to a DRAM refresh control device which guarantees a predetermined number of refresh operations.

[0002]

2. Description of the Related Art A DRAM (Dynamic Random Access Memory) is a memory element that stores information depending on the amount of charge stored in a capacitance element in a memory cell. Even when not accessed, information is stored at regular intervals. A refresh operation is required to read and rewrite. D
As a method for controlling the refresh to the RAM,
The following (1), (2) and (3) are known.

(1) A refresh operation is performed on all the memory cells of the DRAM at one time, and the access to the DRAM of the processing device is stopped during the refresh operation.

(2) All the memory cells in the DRAM are refreshed by performing a plurality of refresh operations at regular intervals within a fixed period, and only when the refresh operation and the access to the DRAM conflict with each other. A method of stopping the processing device that issued the access request.

(3) Dynamic RAM Dynamic refresh method. This dynamic RAM dynamic refresh method will be briefly described later, but for details, refer to the following reference 1.

Reference 1: "Application of Dynamic RAM Dynamic Refresh Method" Shogo Matsui, Computer Architecture Research Group, Information Processing Society of Japan 90-ARC-80-14

[0007]

By the way, it is necessary to surely perform the refresh operation within a certain period, and when the refresh operation and the access from the processing device to the DRAM conflict with each other, the refresh operation is usually performed. Need to be prioritized. Therefore, when contention occurs, access to the DRAM of the processing device is made to wait, and depending on the probability of contention, the access waiting time becomes the entire refresh operation period in the worst case, resulting in system throughput. May be significantly reduced.

In any of the above methods (1) and (2),
The refresh operation periods required to refresh all the memory cells of a DRAM are equal. However, the refresh operation and the access from the processing device to the DRAM have different probabilities of conflict, which causes a difference in the stop period of the processing device. However, in any case, the decrease in throughput due to the access waiting due to the contention cannot be ignored, and improvement is desired.

On the other hand, the method (3) effectively utilizes the access from the processing device as a refresh operation, and the D accessed from the processing device is used.
By storing the RAM address and omitting unnecessary refresh operations, the number of original refresh operations is reduced and the occurrence of conflict is further reduced, so that the throughput can be improved. There is a problem that the cost increases.

The present invention has been made in view of the above circumstances, and a DRAM used as a shared memory from a multi-processing device having a plurality of processing elements in which a processor and a cache memory are mounted is used within a certain period. A refresh controller for a DRAM which guarantees a predetermined number of refresh operations, and a DRA from the refresh element and the processing element.
To provide a DRAM refresh control device capable of improving the system throughput by further reducing the probability of occurrence of contention with access to M, and also keeping the hardware cost relatively low. With the goal.

[0011]

A refresh control device for a DRAM according to the present invention relates to a DRAM used as a shared memory from a multi-processing device having a plurality of processing elements in which a processor and a cache memory are mounted. , Guaranteeing a predetermined number of refresh operations within a fixed period.

[0012] Specifically, the DRAM depends on the access status of the processing element to the DRAM.
A refresh controller for controlling the execution of the refresh operation.

The refresh control device includes
Access status detection function that detects the period when the processing element does not access the DRAM, and remaining time detection function that detects whether the remaining time of the refresh period is longer than the time required to repeat the refresh operation the required number of times. Is provided to accelerate the refresh operation during the period when the processing element does not access the DRAM, and when there is access to the DRAM from the processing element, the remaining refresh period requires the refresh operation. Prioritize access from the processing element over the refresh operation until it matches the time it takes to repeat.

[0014]

In the DRAM refresh control device according to the present invention, the refresh operation is promoted while the DRAM is not accessed.
The probability of contention with access to M can be suppressed to a low level, and thus the throughput in the multi-processing system can be improved. Moreover,
Compared with the dynamic RAM dynamic refresh method described in the conventional example, complicated address management and the like are unnecessary, so that the hardware cost can be kept low.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, it is premised that the processing device for accessing the DRAM is a multi-processing device.
It is assumed that the device is composed of a plurality of processing elements, and each processing element has a processor and a cache memory mounted thereon, which are connected by a shared bus. Generally, in the case of such a device, for example, by monitoring the operation status of the multi-processing device and detecting the arbitration period of the shared bus, the cache hit period, the period in which the processor does not perform memory access, etc. , It is possible to know the period during which there is no access to the DRAM used as the shared memory from each processing element of the multi-processing device.

The present invention detects a period in which the processing element does not access the DRAM, and effectively uses this period for digesting the refresh operation, thereby preventing a decrease in throughput due to competition between the refresh operation and the access. At the same time, the hardware cost is reduced.

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram of a multi-processing system utilizing an embodiment of the present invention. This multi-processing system is a multi-processing device 1
And the memory device 2. The multi-processing device 1 is composed of a plurality of processing elements P1, P2, ... Pn and a shared bus 3 connecting them.

Each processing element P1, P
2, ... Pn is a processor p and a cache memory c
m and. The memory device 2 includes a refresh control device 4 according to an embodiment of the present invention and a DRAM (dynamic random access memory) 5 used as a shared memory by the processing elements P1, P2, ... Pn described above. It is configured.

In other words, the DRAM refresh control device of this embodiment ensures that the refresh control device 4 performs a predetermined number of refresh operations on the DRAM 5 within a fixed period.

FIG. 2 is a detailed view of the refresh control device 4. The refresh control device 4 includes first and second register memories 6 and 7, a comparator 8 that compares the contents of these two register memories 6 and 7 and outputs an output according to a comparison result, and this comparator. It has a priority judging device 11 for deciding whether or not to execute the refresh operation with priority based on the output 9 of 8 and the information 10 indicating the access status to the DRAM 5 of the multi-processing apparatus 1 described above.

The information 10 indicating the access status is information indicating a period during which the multi-processing device 1 does not use the DRAM 5 or an access time, and a period during which the multi-processing device 1 does not use the DRAM 5 is:
As described above, the operation status of the multi-processing apparatus 1 is monitored and estimated from the arbitration period of the shared bus, the cache hit period, the period during which the processor does not access the memory, and the like.

The DRAM refresh control device of this embodiment refreshes all the memory cells in the DRAM 5 by performing a predetermined number of refresh operations within a fixed period. The above-mentioned fixed period that requires the memory is called a refresh period, and the time required for one refresh operation is called a memory cycle time.

To facilitate understanding, a specific example will be described. When the device "MSM511001A" manufactured by Oki Electric Industry Co., Ltd. is used as the DRAM, the memory cycle time becomes 400 nanoseconds. The refresh period is 8 milliseconds. And
It is necessary to perform 512 refresh operations within this refresh period.

The register memory 6 will be described.
This register memory 6 holds the remaining number of refresh operations that must be executed during the refresh period. As the DRAM 5, the above-mentioned "MSM51100"
When 1A ″ is used, the value 512 is set at the start of the refresh period, and the held value is
The number is decremented by 1 each time the refresh operation is performed once. When the value of this register becomes 0, it means that all refresh operations in the refresh period have been completed.

The register memory 7 will be described.
The register memory 7 holds a value obtained by dividing the remaining time of the refresh period by the memory cycle time. And
The held value is decremented by 1 each time the time corresponding to the memory cycle time has elapsed. When the above-mentioned "MSM511001A" is used as the DRAM 5,
The value 20000 is set at the start of the refresh period. This value is 8 milliseconds divided by 400 nanoseconds. When the value of the register memory 7 becomes 0, one refresh period has ended, and the next refresh period is started.

The comparator 8 compares the value held in the register memory 6 with the value held in the register memory 7, and when they match, the comparison result is 0.
Is output, otherwise 1 is output.

The priority determining unit 11 detects the period of no access to the DRAM 5 based on the information 10 indicating the access state, and the output 9 of the comparator 8 to determine the refresh period. A remaining time detecting function for detecting whether or not the remaining time is longer than the time required to repeat the refresh operation a required number of times,
Refresh operation is actively performed during the period when there is no access to the memory, and DR from the processing element
When there is access to the AM, the access from the processing element is prioritized over the refresh operation until the remaining refresh period matches the time required to repeat the refresh operation the required number of times.

Specifically, while the output 9 of the comparator 8 is 1, if there is an access request, it is prioritized, and if there is no access, the refresh operation is continued. And the comparator 8
When the output 9 becomes 0, even if there is an access request to the DRAM 5, it is kept waiting, and the refresh operation is preferentially continued until the output 9 of the multi-processing device 8 becomes 1.

The fact that the output 9 becomes 0 means that the entire remaining time of the refresh period has to be used for the refresh operation.
The above-described control of the priority determiner 11 ensures that the refresh operation is executed a predetermined number of times within the refresh period.

The effect of the above-described embodiment will be described with a concrete example. For example, the multi-processing device 1 is composed of eight processing elements. When the machine cycle of each processor p is 100 nanoseconds and the frequency of memory access instructions is 25%, 160000 memory accesses are performed in 8 milliseconds. The instruction is executed. Assuming that the hit rate of the cache memory cm is 90% (generally considered to be higher), if the memory cycle time of the DRAM 5 is 400 nanoseconds, the operation time of the memory device is 6.4 milliseconds. Therefore, even if the hit rate of the cache memory is about 90%, there is no conflict with the refresh operation and the access.

Therefore, compared with the case of using the conventional method, the throughput of the multi-processing system can be greatly improved, and moreover, compared with the case of the dynamic RAM dynamic refresh method described in the conventional example, Since complicated address management and the like are unnecessary, the hardware cost can be kept low.

[0033]

As is apparent from the above description, in the DRAM refresh control device according to the present invention, the DRAM
On the other hand, since the refresh operation is promoted during the period when there is no access, the probability of conflict between the refresh operation and the access to the DRAM can be suppressed to a low level, and the throughput in the multi-processing system can be improved. Moreover, as compared with the case of the dynamic RAM dynamic refresh method described in the conventional example, complicated address management and the like are unnecessary, so that the hardware cost can be kept low.

[Brief description of drawings]

FIG. 1 is a block diagram of a multi-processing system utilizing the present invention.

FIG. 2 is an explanatory diagram of a refresh control device that is a main part of one embodiment of the present invention.

[Explanation of symbols]

 1 Multi-Processing Device 2 Memory Device 3 Shared Bus 4 Refresh Control Device 5 DRAM 6, 7 Register Memory 8 Comparator 9 Output of Comparator 10 Information indicating Access Status 11 Priority Judgment Device

Claims (1)

[Claims] 1. A D used as a shared memory by a multi-processing device having a plurality of processing elements in which a processor and a cache memory are mounted.
A refresh control device for a DRAM, which guarantees a predetermined number of refresh operations to a RAM within a certain period, and has a function of controlling execution of the refresh operation of the DRAM according to an access status of the processing element to the DRAM. The refresh control device has an access status detection function for detecting a period in which the processing element does not access the DRAM, and whether the remaining refresh period is longer than the time required to repeat the refresh operation a required number of times. It is equipped with a remaining time detection function to detect whether or not the refresh operation is promoted during the period when the processing element does not access the DRAM.
In addition, when the processing element accesses the DRAM, access from the processing element is performed rather than the refresh operation until the remaining refresh period matches the time required to repeat the refresh operation the required number of times. To prioritize
DRA characterized by including priority determination means for determination
M refresh controller .