JP2001135079A - Memory control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease updating burst length as much as possible by optimizing the setting of burst length for the request of access of arbitrary burst length for a SRAM. SOLUTION: It is checked whether the change of a row address is performed or not during access processing of arbitrary burst length, when the change is already performed, processing is performed by dividing burst length before and after the change. Also, occurrence frequency of each burst length is obtained, burst length is automatically changed to the burst length of the maximum occurrence frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device for controlling access to a synchronous DRAM capable of high-speed access with a set burst length, and to access of an arbitrary number of words from an arbitrary address. To a control device that enables

[0002]

2. Description of the Related Art Synchronous DRAMs can operate at high speed, and can access very consecutive addresses at a very high speed. However, it is difficult to perform high-speed access when discontinuous addresses or continuous addresses are interrupted in a short cycle. Conventionally, in the case of accessing non-consecutive addresses, a technique has been adopted in which banks are switched to increase the speed. For accesses with different burst lengths, the order of accesses is rearranged for each burst length to reduce the settings in the mode register and the like, thereby achieving higher speed. However, these methods are not effective for processing in which accesses within the same bank are concentrated.

Japanese Patent Application Laid-Open No. H11-140773 describes that a plurality of sequencers are provided for a plurality of banks and the burst length and the start address are managed for each bank. There is no effect when different accesses are mixed. JP-A-08-
055060, JP 08-179983, JP 08
179994 and JP-A-08-202614,
Although the access of a word number smaller than the fixed burst length is described, the access is prohibited (stopped) in the middle. Even if the burst stop function of the SDRAM is used, the burst length is limited to a full page. Useless cycles occur after issuing the stop command. In JP-A-11-224221, an instruction (access) having a high data transfer efficiency by judging a transfer burst length is described.
The transfer efficiency can be increased by performing a control of changing the order so that execution is performed from the beginning.However, in the case where requests from a plurality of circuits are given priority in the request, the efficiency of the efficiency is increased. It cannot be overturned in priority. In the present invention, it is assumed that accesses having different burst lengths are randomly concentrated in the same bank, and even in such a case, a decrease in access capability can be reduced.

[0004]

SUMMARY OF THE INVENTION Synchronous DRAM
Can operate at high speed, but it is difficult to perform high-speed access when discontinuous addresses or continuous addresses are interrupted in a short cycle as described above. There are several causes, one of which is that the row address to be accessed must be activated each time, and that if the burst length to be accessed changes, the burst length must be set by the mode register. . When access requests to RAMs having different burst lengths coexist, a mode register must be set every time the access burst length changes, which hinders speeding up. An object of the present invention is to increase the access speed by reducing the change in the burst length by the mode register in consideration of the case where accesses to the same bank are concentrated.

[0005]

According to the present invention, there is provided a memory control device for processing an access request of an arbitrary burst length to a synchronous DRAM.
Detecting means for predicting whether or not a row address changes during burst access when performing a burst access with an arbitrary burst length; detecting a change in row address when the detecting means predicts a change in row address; Calculating means for dividing the burst access before and after, calculating the burst length of each divided burst access, and setting the burst length determined based on the greatest common divisor of the burst length of each divided burst access in the synchronous DRAM Length setting means, means for generating a start address for each set burst length, and issuing a read / write command based on the start address generated for each set burst length to continuously access data. .

A memory control device according to the present invention includes a plurality of counters for counting a burst length for which an access request is made for each burst length, and a burst having a maximum count value of the plurality of counters as a maximum frequency burst length. The apparatus further comprises a long count comparator means and a timer means, and when there is no next access request until a predetermined time set in the timer means has elapsed after the end of one access process, the maximum frequency burst length is synchronized. The burst length of the eggplant DRAM is automatically updated.

[0007] The detecting means may detect the start address of the address requested to be accessed by the column address of the column address.
And the burst length requested for access,
When the burst length is larger than the two's complement of the column address, the row address is predicted to change during the burst access.

A memory control device for processing an access request of an arbitrary burst length to a synchronous DRAM, comprising a plurality of counters for counting a burst length for which an access request has been made for each burst length; Comparing means for setting the maximum value of the count value to the maximum frequency burst length; timer means for setting a predetermined time after the access processing is completed; and synchronizing when there is no next access request within the predetermined time. Eggplant DRAM
Automatic updating means for updating the burst length set to the maximum frequency burst length.

[0009]

(Embodiment 1) Embodiment 1
In FIG. 1, a RAM access arbitration circuit 8 is provided at a stage preceding the SDRAM command generation circuit 4 and the address generation circuit 6 provided for the synchronous DRAM 2. The RAM access arbitration circuit 8 arbitrates an access request from the refresh control circuit 10 and an access request to the SDRAM 2 from a plurality of blocks (not specifically shown) in accordance with a given priority, and will be described in detail below. Thus, the necessary burst length is set. That is,
Access requests of various burst lengths are randomly generated from a plurality of blocks, and the RAM access arbitration circuit 8 generates an access order according to a predetermined priority, and gives an access right to one block according to the order. . The RAM access arbitration circuit 8 receives an access request signal, an address signal, and the number of words (burst length) from the block to which the access right has been given as inputs, and
An access request signal, a burst length determined by a method described in detail below, and the number of consecutive words are output to the command generation circuit 4, and the address generation circuit 6
, The address, the burst length, and the number of continuous words are output.

[0010] The SDRAM command generation circuit 4 has a RAS
(Row address signal) signal, CAS (column address signal) signal, chip select signal (CS), write enable signal (WES) and data mask signal
Output to M2. The address generation circuit 6 receives an address signal, a burst length, and a continuous word length output from the RAM access arbitration circuit 8, and generates an address (including the burst length as information) to be output to the SDRAM 2.
The SDRAM 2 sets a burst length in a built-in mode register (not shown) based on the address information input from the address generation circuit 6, and inputs the input address and the RA input from the SDRAM command generation circuit 4.
Data is read from and written to the data buffer 12 according to commands such as S, CAS, CS, and WE.

When the RAM access arbitration circuit 8 receives an access request from the refresh control circuit 10, the RAM access arbitration circuit 8
A refresh operation is performed on the SDRAM 2. The RAM access arbitration circuit 8 according to the present invention determines whether or not the row address changes during the burst access in the access processing to be processed, and sets the burst length.

FIG. 2 shows an example of R for setting the burst length.
4 shows a flowchart of a control program executed by the AM access arbitration circuit 8. In step S101, when an access request is input, the presence or absence of another access request is checked in step S103. If there is another access request, in step S105, based on the priority of the predetermined access request, Select an access request with a higher priority. In step S107, the access request given the access right is accepted, and the start address and the burst length (the number of words) are read. In step S109, it is determined whether or not the row address changes during the burst access for the received access request.

The determination method is as follows. 1. Calculate the two's complement of the start column address. 2. The complement and the input burst length are compared. 3. As a result of the comparison, if the input burst length> complement, it means that the row address changes in the middle of the burst access. Therefore, the access is divided before and after the change of the row address. 4. The number of consecutive words in the access before the change of the row address is determined from the two's complement of the column address, and the number of consecutive words in the access after the change is a value obtained by subtracting the number of continuous words in the access before the change from the burst length. You can ask. 5. As described above, when the row address changes during the burst access, the burst length is set to "1". 6. If there is no change in the row address during the burst access, that is, if the input burst length ≦ complement, the burst length is not changed.

Next, in step S111, the burst length and the continuous word length calculated in step S109 are represented by S
Output to the DRAM command generation circuit 4 and the address generation circuit 6. Then, the SDRAM command generation circuit 4 outputs various commands to the SDRAM 2, and the address generation circuit 6 stores the address information (including the set burst length) in the SDRAM 2.
Output to DRAM2.

FIG. 3 shows an example of the operation timing for the above access. In this example, it is assumed that the width of the data bus is 16 bits, and that an access request of 8 words (input burst length) is made, and one row address accesses a RAM of 256 words. Now, the row address of the first word is 1, and the column address is 251 (FB
If h), the row address of the sixth word is 2 and the column address is 0. That is, the row address changes in the middle of the burst access, and before and after the change, the access is divided into two accesses: a continuous word number 5 access and a continuous word number 3 access.

As described above, in this case, the RAM access arbitration circuit 8 outputs the output burst length "1", the number of continuous words "5", and "3" to the SDRAM command generation circuit 4 and the address generation circuit 6. . The SDRAM command generation circuit 6 outputs low active signals CSB, RASB, CASB, and WEB according to the clock signal. On the other hand, SDRAM 2 sets the burst length of the mode register to "1" in accordance with the MRS (signal representing the burst length) included in the input address information (MO
DE BL = 1).

At the timing when a row address (ROW) is input, an active command ACT is generated in the SDRAM 2 and then when a read command is continuously generated five times, a continuous command is generated according to the input column address FB-FF. A five-word data access is executed.
The last (fifth) read command is a read A command READA (A means auto precharge). In this case, the burst length is set to "1",
In the read and write commands, access with a burst length of 1 is performed five times consecutively under the same row address.

Next, when the row address (ROW + 1) is changed, the active command ACT is output again,
When the read A command is generated, data access is performed continuously three times in total while the burst length is 1, and as a result, data access of 8 words is completed.

As described above, when the row address changes, the access can be performed continuously without changing the burst length setting. Therefore, the burst length need only be set once for any access, and the high-speed access can be performed accordingly. Can be realized.
In the above embodiment, the burst length set in the SDRAM 2 is set to the maximum burst length “1”. However, if the burst length before and after the row address changes is, for example, “6” and “2”, the burst length is set. The burst length may be set to “2”. In other words, the greatest common divisor of the preceding and following burst lengths may be set as the set burst length.

(Embodiment 2) FIG. 4 shows a circuit configuration according to Embodiment 2 of the present invention. As is clear from comparison with the circuit configuration of FIG. 1, in the second embodiment, a burst length counter / comparator 14 is provided in addition to the circuit configuration of FIG. This burst length counter / comparator 14
For all burst lengths that can be set in the mode register of AM2, a separate counter is provided for each burst length, and when there is an access request, the burst length is counted by the corresponding counter, so that the number of access requests for each burst length can be reduced. Count. The comparator compares a plurality of count values counted for each burst length, and constantly selects a burst length with the highest access frequency.

The circuit configuration of the second embodiment has a burst length setting function which is most frequently generated when there is no access request for a predetermined time, in addition to the burst length setting function executed by the circuit configuration of the first embodiment. It is automatically updated to the burst length. Therefore, the circuit configuration of FIG. 4 is basically the same as the circuit configuration of FIG. 1 except for the added burst length counter / comparator 14, and corresponding components are denoted by the same reference numerals, and redundant description is omitted. I do.

FIG. 5 is a flowchart of a burst length automatic update routine executed in the second embodiment. When one access request process is completed in step S201, a timer in which a predetermined time is set in advance is set in step S203. Next, step S2
At 05, the presence or absence of a new access request is checked. If there is a new access request within the timer time,
The access request is processed.

On the other hand, if there is no access request until the timer expires (step S207), the SDR
The request of the AM command generation circuit 4 (RAS, CAS, C
In accordance with the combination of commands such as S and WE, the burst length counter / comparator 14 outputs the most frequently occurring burst length to the SDRAM command generation circuit 4 at that time, and the SDRAM command generation circuit 4 outputs the address generation circuit 6 To indicate the burst length. Address generation circuit 6
Outputs the instructed burst length to SDRAM2,
The DRAM 2 sets the value in an internal mode register.

FIG. 6 shows an example of actual operation timing. In this example, it is assumed that the most frequently occurring burst length is "4", and an access with a burst length of "2" is performed first. As shown in FIG. 6, when an access request of the first burst length “2” is accepted, the commands CSB, RASB, CASB and WEB go low at the same time, and at that timing, the address generation circuit 6
A signal (MRS) indicating that the burst length is "2" is output to the RAM 2, and the mode register is set to "2" (MODE BL = 2). Next, the row address (RO
When the active command (ACT) of W) is issued,
At the next timing, column address read A (READ)
A) A command is issued to access two data.

After the access request processing is completed, until the set timer times out, if there is no subsequent access request, the SDRAM commands CSB, RASB,
CASB and WEB go low at the same time, and at this time, the value of the mode register is set to “4” corresponding to the burst length WRS (in this example, the burst length of the maximum occurrence frequency is “4”) output from the address generation circuit 6. "To set the burst length to" 4 ".

Next, if there is an access request and the burst length of the access request is "4", the burst length is automatically updated to "4" at this point, so the burst length is reset. There is no need to issue a row address (ROW) active command (ACT), and then read A (READ) for the column address.
A) A command is issued to execute 4-word data access.

As described above, when there is no access request for a fixed period, the burst length is automatically updated to the burst length having the highest frequency of occurrence, and the burst length of the next access request is reduced to the updated burst length. If they do, the data can be accessed immediately without updating the burst length.
In the second embodiment, an automatic update function of the burst length is further added to the function of the first embodiment. However, this automatic update function is sufficiently effective even if implemented alone.

[0028]

According to the memory control device of the present invention, when processing an access request of an arbitrary burst length from an arbitrary address, even if the row address changes during the burst access, one burst operation is performed. An access request can be processed by setting the length, and the number of cycles required for access can be reduced. In the memory control device according to the second aspect, when there is no access request for a certain period of time, the data is automatically updated to the maximum frequency burst length.
The probability that the burst length of the next access request matches the maximum frequency burst length is high. In that case, the access request processing can be executed immediately, and the processing can be speeded up. According to the memory control device of the third aspect, it is possible to determine whether or not the row address changes during the burst access by a simple calculation. According to the memory control device of the fourth aspect, when there is no next access request for a certain time or more, the burst length is automatically updated to the burst frequency of the highest frequency, so that the probability of coincidence with the burst length of the next access request increases. If they match, the access request can be processed immediately without updating the burst length, and the speed can be increased accordingly.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a memory control device according to a first embodiment of the present invention.

FIG. 2 is a flowchart of a control program executed by the memory control device of FIG. 1;

FIG. 3 is a timing chart of a burst access process in the memory control device of FIG. 1;

FIG. 4 is a block circuit diagram of a memory control device according to a second embodiment of the present invention;

FIG. 5 is a flowchart of a control program executed by the memory control device of FIG. 4;

FIG. 6 is a timing chart of a burst access process in the memory control device of FIG. 4;

[Explanation of symbols]

 2 SDRAM 4 SDRAM command 6 Address generation circuit 8 RAM access arbitration circuit 10 Refresh control circuit 12 Data buffer 14 Burst length counter / comparator

Claims (4)

[Claims] 1. A memory control device for processing an access request of an arbitrary burst length to a synchronous DRAM, wherein whether a row address changes during a burst access when performing a burst access with the arbitrary burst length. Detecting means for predicting a change in row address, dividing the burst access before and after the change in row address, and calculating the burst length of each of the divided burst accesses; Burst length setting means for setting a burst length determined based on the greatest common divisor of the burst length of each burst access set in the synchronous DRAM, means for generating a start address for each set burst length,
A memory control device for continuously accessing data by issuing a read / write command based on a start address generated for each set burst length. 2. A plurality of counters for counting a burst length for which an access request has been made for each burst length, a burst length count comparing means for setting the maximum count value of the plurality of counters to a maximum frequency burst length, and a timer means. When there is no next access request until a predetermined time set in the timer means has elapsed after one access processing, the burst length of the synchronous DRAM is automatically updated to the maximum frequency burst length. 2. The memory control device according to claim 1, wherein: 3. The detecting means compares the two's complement of the column address of the start address of the address requested for access with the burst length of the requested access, and determines that the burst length is greater than the two's complement of the column address. 3. The memory control device according to claim 1, wherein when large, the row address is predicted to change during burst access. 4. A memory control device for processing an access request of an arbitrary burst length to a synchronous DRAM, comprising: a plurality of counters for counting a burst length for which an access request has been made for each burst length; Comparing means for setting the maximum value of the count value to the maximum frequency burst length; timer means for setting a predetermined time after the access processing is completed; and synchronizing when there is no next access request within the predetermined time. A memory control device comprising: automatic updating means for updating the burst length set in the eggplant DRAM to the maximum frequency burst length.