JP2007323113A - Memory control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control circuit capable of speeding up a continuous access extending over different pages. <P>SOLUTION: A port control part 11A outputs a matching detection signal showing whether or not an address to be accessed is the same as the page under current access. A bus arbitration part 12A designates a port control part 11A for permitting the next access by a second selection signal, and applies the matching detection signal of the port control part 11A from a selector 14 to a pre-charge control part 17. When it is shown that the address of the next access is different from a page under current access, the pre-charge control part 17 applies a pre-charge command to a memory in a predetermined timing before the end of current access. Thus, it is possible to achieve pre-charge to the next page during the access of the current page, and to achieve the high speed operation of continuous access by shortening an apparent pre-charge time. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory control circuit of a dynamic memory.

FIG. 2 is a configuration diagram of a conventional memory control circuit.
The memory control circuit 10 is a multi-port type that receives access from a bus master i (where i = 1 to n) such as a plurality of CPUs (central processing units) directly by a memory control circuit without using a common bus. The memory control circuit in the connection form has ports Pi corresponding to these bus masters i. Each port Pi has the same configuration, and is composed of ADRi indicating the address of the access destination, W / Ri indicating whether the access is write or read, RDTi indicating read data, and RDYi indicating a response signal from a slave such as a memory. .

Each port Pi is provided with a corresponding port controller 11 _i so that an access received at the port Pi is converted into an address signal MADi and a command signal CMDi that are signals for performing an actual memory access. . In the port controller 11 _i for the DRAM (Dynamic Random Access Memory) 20, the address signal ADRi from the bus master i is decomposed into an upper bit row address RA and a lower bit column address CA to generate an address signal. Output as MADi. The command signal CMDi includes an ACT command for validating the row address RA, an R command for validating the read cycle and the column address CA, and a PRE command for instructing a precharge that is an operation necessary before switching the row address RA. Etc.

Further, each port control unit 11 _i outputs a request signal REQi for transmitting an access request from the bus master i and also receives a grant signal GRNi for permitting access. This grant signal GRNi Is provided, the DRAM 20 can be accessed.

The request signal REQi of each port control unit 11 _i is given to the bus arbitration unit 12, and the grant signal GRNi is output from the bus arbitration unit 12 to each port control unit 11 _i . The bus arbitration unit 12 permits access in a predetermined priority order when access requests from a plurality of bus masters i to the DRAM 20 compete. A selection signal SEL for the selector 13 is output from the bus arbitration unit 12.

The selector 13 selects the address signal MADi and the command signal CMDi output from each port control unit 11 _i according to the selection signal SEL provided from the bus arbitration unit 12 and supplies the selected signal to the DRAM 20. On the other hand, the data MDT read from the DRAM 20 is provided in common to each port control unit 11 _i .

FIG. 3 is a timing chart showing the operation (1) of FIG.
At time T2 of FIG. 3, when the port P1 access address A0, A1 are input, the port control unit 11 ₁ outputs the request signal REQ1 to bus arbitration unit 12.

  At time T3, the bus arbitration unit 12 outputs a grant signal GRN1 in response to the request signal REQ1, and grants access permission to the DRAM 20 to the port P1.

Port controller 11 ₁ to obtain a permission, a time T4, to enable the row address RA and outputs the ACT command. At this time, the address A0 is broken down into a row address RA and a column address CA.

Port control unit 11 _1, the time T6 from the output of the ACT command is after 2 clock as sufficient time, and outputs the R command indicating a column address CA and read access.

The DRAM 20 that has received the R command returns the data DA0 read from time T7. Port controller 11 ₁ that has received the data DA0 is the time T8, and outputs the response signal RDY1 to the bus master 1, and outputs it as data RDTi read data DA0.

Similarly, responses are returned to the bus master 1 at times T9 and T10. Since there is no access from the port P1 at time T9, the port controller 11 ₁ stops outputting the request signal REQ1.

On the other hand, at time T4, the address B accesses the row address RA from the port P2 is input, the port control unit 11 ₂ outputs a request signal REQ2 to the bus arbitration unit 12. At this point, the bus arbitration unit 12, since already output a grant signal GRN1 the port controller 11 _1, the output of the grant signal GRN2 for this request signal REQ2 is suspended. Then, when there is no request from the port P1 at time T9, the grant signal GRN2 is output to the port P2 at time T10, and access permission to the DRAM 20 is given.

Port controller 11 ₂ to obtain a grant signal GRN2, when access from bus master 2 is determined the same as the previous row address RA, without outputting the ACT command, and outputs the R command and a column address CB, from DRAM20 Read data DB is obtained at time T12. At time T13, the response signal RDY2 for the bus master 2 is output, and the data DB is returned as read data RDT2.

FIG. 4 is a timing chart showing the operation (2) of FIG.
This operation is performed when an access from the port P2 to the row address RB different from the RA occurs during the access in the row address RA from the port P1.

In this case, the same operation as in FIG. 3 is performed until time T10.
At time T11, the port control unit 11 _2, the row address RB is determines that differs from the current row address RA, for the precharge operation of the row address RA, and outputs the PRE command. Thereafter, the completion of precharge of the DRAM 20 is waited, and at time T13, an ACT command and a row address RB are output in order to newly set a row address. After a sufficient time has elapsed from the ACT command, the R command and the column address CB are output at time T15, and the read data DB is obtained at time T16. At time T17, the response signal RDY2 for the bus master 2 is output and the data DB is returned as read data RDT2. Comparing FIG. 4 and FIG. 3, it can be seen that, in FIG. 4, the reading of the data DB is delayed by 4 clocks required for the PRE command and the ACT command because the row address is different.

  On the other hand, apart from the speedup method by page hit (sequential access to the same row address) used in the memory control circuit 10 of FIG. Apparently there is a speeding-up method that shortens.

  The method of performing precharge by overlapping with this data transfer is the case of SDRAM or the like capable of precharge and data transfer overlap, and when the data length to be transferred is known in advance, the last few bytes before The precharge command is output at the timing. As a result, compared to the case where the precharge command is output after the data transfer is completed, the next data transfer can be started earlier by the overlapping amount. However, when precharging is performed, it is necessary to output an ACT command in order to validate the row address at the next access.

  In Patent Document 1 below, it is predicted whether precharge is necessary in the next process based on the determination result of the access type and access mode, and the next process is performed with or without precharge. A DRAM access method for determining whether to proceed to processing is described.

Japanese Patent Laid-Open No. 11-282746

  However, the memory control circuit 10 of FIG. 2 does not perform precharge overlapping data transfer in order to obtain the effect of page hit. Therefore, in the case of a page miss (access to different row addresses), there is a problem that access is delayed by the time required for the PRE command and the ACT command. On the other hand, in the method in which the precharge and the data transfer are overlapped, the ACT command is always required for the next access, so that the benefit of shortening the time from the ACT command to the column address input in the case of page hit cannot be obtained. There was a problem. Also. In the DRAM access method of Patent Document 1, when precharging is performed, there is a problem that the time cannot be reduced because the precharging is performed after the previous access is completed.

  An object of the present invention is to provide a memory control circuit capable of increasing the speed of continuous access across different pages.

  The memory control circuit of the present invention is provided corresponding to a plurality of bus masters, converts an access signal for a common memory given from the corresponding bus master into an address and a control command corresponding to the memory, and an access request signal and the A plurality of port control units that output a match detection signal indicating whether the address is the same as the currently accessed page of the memory, and one access request signal output from the plurality of port control units. From the plurality of port control units, a bus arbitration unit that outputs a first selection signal for permitting access to the port control unit and outputs a second selection signal for designating a port control unit for which access is permitted next. A first selector that selects an output address and a control command according to the first selection signal and gives the selected command to the memory; A second selector that selects and outputs the coincidence detection signals output from the plurality of port control units in accordance with the second selection signal, and a current detection signal selected in accordance with the coincidence detection signal selected by the second selector. And a precharge control unit for giving a precharge command to the memory at a predetermined timing before the access is completed.

  In the present invention, the port control unit provided corresponding to the bus master outputs a coincidence detection signal as a result of determining whether or not the address requesting access is the same as the currently accessed page, and bus arbitration. A second selection signal for designating a port control unit to which access is permitted next. Further, the coincidence detection signal output from each port control unit is selected by the second selection signal and is supplied to the precharge control unit. As a result, when the precharge control unit indicates that the address of the next access does not match the currently accessed page, the precharge control unit pre-loads the memory at a predetermined timing before the current access is completed. It becomes possible to give a charge command. Accordingly, since the next page can be precharged while the current page is being accessed, the apparent precharge time is shortened, and the speed of continuous access can be increased.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

  FIG. 1 is a configuration diagram of a memory control circuit showing a first embodiment of the present invention. Elements common to those in FIG. 2 are denoted by common reference numerals.

  The memory control circuit 10A is a multi-port type memory control circuit similar to that in FIG. 2, and has ports Pi corresponding to a plurality of bus masters i (where i = 1 to n). Each port Pi has the same configuration, and is composed of ADRi indicating the access destination address, W / Ri indicating whether the access is writing or reading, RDTi indicating the read data, and RDYi indicating the response signal from the slave.

Each port Pi is provided with a corresponding port control unit 11A _i so that an access received at the port Pi is converted into an address signal MADi and a command signal CMDi, which are signals for actual memory access. . In each port control unit 11 _i , the address signal ADRi from the bus master i is decomposed into the upper bit row address RA and the lower bit column address CA and output as the address signal MADi. The command signal CMDi includes an ACT command for validating the row address RA, an R command for validating the read cycle and the column address CA, and the like.

Each port control unit 11 _i outputs a request signal REQi for transmitting an access request from the bus master i and also receives a grant signal GRNi for permitting access. The grant signal GRNi Is provided, the DRAM 20 can be accessed.

Further, each port controller 11 _i is provided with a precharge detection signal PDET indicating whether or not the DRAM 20 has been precharged and current page information CPAGE indicating the currently selected page (row address). In response to this, a precharge request signal PRQi indicating whether or not precharge is necessary is output. That is, when there is an access request from the bus master i, each port control unit 11 _i determines whether or not the row address specified in the access request is the same as the currently selected page. If so, a precharge request signal PRQi is output in order to perform precharge, which is a necessary operation before switching pages.

Request signal REQi of each port controller 11A _i is supplied to the bus arbitration unit 12A, to each port controller 11A _i from the bus arbitration unit 12A, grant signal GRNi indicating whether the access is to be outputted . The bus arbitration unit 12A permits access in a predetermined priority order when access requests from a plurality of bus masters i to the DRAM 20 compete. A selection signal SEL1 for the selector 13 and a selection signal SEL2 for the selector 14 are output from the bus arbitration unit 12A. The selection signal SEL1 designates the bus master i that is currently permitted to access, and the selection signal SEL2 designates the bus master that is permitted to access next.

The selector 13 is to provide an address signal MADi and command signals CMDi output from each port controller 11A _i, the DRAM20 selected according to a selection signal SEL1 provided from the bus arbitration unit 12A.

Selector 14, a precharge request signal PRQi output from each port controller 11A _i, selected according to a selection signal SEL2 provided from the bus arbitration unit 12A, the pre-charge detecting section 15 as a precharge request signal PRQ, current page registers 16 and the precharge control unit 17.

  The precharge detector 15 holds the precharge request signal PRQ selected by the selector 14 and outputs it as a precharge detection signal PDET. The current page register 16 holds the row address in the address signal MAD selected by the selector 13 based on the precharge request signal PRQ and outputs it as current page information CPAGE. When the precharge request signal PRQ output from the selector 14 indicates that precharge is necessary at the next access, the precharge control unit 17 overlaps the current data transfer at a predetermined timing. Thus, a PRE command for instructing the precharge to the DRAM 20 is output.

On the other hand, data MDT read from DRAM20 is adapted to be applied commonly to each port controller 11A _i.

  FIG. 5 is a timing chart showing the operation of FIG. The operation of FIG. 1 will be described below with reference to FIG.

At time t2 in FIG. 1, when the port P1 access address A0 are input, the port control unit 11A ₁ outputs the request signal REQ1 to a bus arbitration unit 12A.

  At time t3, the bus arbitration unit 12A outputs a grant signal GRN1 with respect to the request signal REQ1, and grants access permission of the DRAM 20 to the port P1. At the same time, the bus arbitration unit 12A selects the port P1 by the selection signal SEL1, and the port P1 is selected by the selector 13.

Port controller 11A ₁ to give a permission, at time t4, to enable the row address RA and outputs the ACT command. At this time, the address A0 is broken down into a row address RA and a column address CA. At time t5, the row address RA is stored in the current page register 16, and at the same time, the precharge detection signal PDET is reset to “0”.

Port controller 11A ₁ is the time t6, and outputs the R command indicating a column address CA and a read access, during the period from time t7 to time t10, the obtained sequentially DA0, DA1, DA2, DA3 data MDT from DRAM 20. Port controller 11A ₁ as data RDT1 reads these data MDT, the period from time t8 to time t11, the output to the bus master 1 with a response signal RDY1 set to "1". The above operation is the same as the conventional one.

Assume that access at a row address RB different from the current row address is input to the port P2 at time t4. In this case, it is necessary to perform a precharge operation before accessing the row address RB. The port control unit 11A _2, the current row address RA is the content of the current page information CPAGE provided from the current page registers 16, compares the row address RB specified by the access request, the precharge operation is required Determination is made and a precharge request signal PRQ2 is output.

  On the other hand, in the bus arbitration unit 12A, when the request signal REQ1 of the port P1 is stopped at time t9, the next selected port is P2, the precharge request signal PRQ2 is “1”, and the currently selected port Since the request signal REQ1 of P1 is “0”, the port P2 that is allowed to be accessed next is set by the selection signal SEL2. As a result, the precharge request signal PRQ output from the selector 14 becomes “1”, and the precharge detection signal PDET output from the precharge detector 15 becomes “1”. Further, the precharge control unit 17 outputs a PRE command to the DRAM 20 in accordance with the precharge request signal PRQ.

After the selection signal SEL2 is output, the bus arbitration unit 12A does not give the grant signal GRN, which is a memory use permission, to any port at time t10 as the precharge operation completion wait time. Then, in anticipation that the precharge operation is completed at time t12, the on time t11, the outputs a grant signal GRN2 to the port controller 11A _2.

The port control unit 11A _2, when the grant signal GRN2 permitted for use granted DRAN20 is obtained, since become precharge detection signal PDET is "1", the precharge operation is determined to be unnecessary, time At t12, the ACT command and the row address RB are output.

Further, the port control unit 11A ₂ outputs the column address CB to the time t14, at time t15, obtain data DB. At time t16, the response signal RDY2 is set to “1” and the data DB is output as the read data RDT2 to respond to the requested access to the port P2.

  As described above, the memory control circuit according to the first embodiment determines the next port to permit access based on the access request given from the plurality of ports P0 to Pn, and outputs the selection signal SEL2 at a predetermined timing. The bus arbitration unit 12A, the selector 14 for selecting a corresponding one of the precharge request signals PRQ1 to PRQn output from the ports P0 to Pn according to the selection signal SEL2, and the pre-output output from the selector 14 The precharge control unit 17 outputs a PRE command for the DRAM 20 in accordance with the charge request signal PRQ. This makes it possible to precharge the next page while accessing the current page even when accessing addresses that span different pages. This reduces the apparent precharge time and speeds up continuous access. There is an advantage that it becomes possible.

  FIG. 6 is a configuration diagram of a memory control circuit showing Embodiment 2 of the present invention. In FIG. 6, read / write data signals are omitted.

  The memory control circuit 30 includes a command generation unit 31 that generates various commands CMD for the DRAM 20 based on an access control signal CRT or the like given from a CPU or the like (not shown) via a system bus. In addition to the control signal CRL, the command generation unit 31 is provided with a page hit signal HIT indicating whether or not an address to be accessed next is in the same page and a row address request signal RRQ for requesting output of a row address. The response signal RDY for the CPU or the like is output. The command CMD generated by the command generation unit 31 is supplied to the ACT detection unit 32 and the command detection unit 33 in addition to the DRAM 20.

  The ACT detection unit 32 detects that an ACT command in the command CMD has been generated, and outputs an update signal UPDT at the detected timing. The command detection unit 33 outputs a restart signal RST to the timer 34 every time a command CMD is generated regardless of the type of command. The timer 34 is configured to restart timing from the beginning by the restart signal RST, and outputs the row address request signal RRQ when a certain time is measured. That is, the command detection unit 33 and the timer 34 detect that the command CMD for the DRAM 20 has been interrupted for a certain period of time.

  Further, the memory control circuit 30 has an address holding unit 35 that temporarily holds an address signal ADR given through the system bus, and a comparison unit 36 that inputs a row address RA in the address signal ADR. ing. The comparison unit 36 compares the row address RA given from the CPU or the like with the current page information PAGE, and outputs a page hit signal HIT when they match, and the page hit signal HIT is sent to the command generation unit 31 described above. Is given. Of the address signal ADR held in the address holding unit 35, the row address RA is given to the selector 37, and the column address CA is given to the selector 38, respectively.

  The selector 37 selects either the row address RA held in the address holding unit 35 or a prediction page described later in accordance with the row address request signal RRQ, and gives it to the selector 38 and the current page holding unit 39. is there. The selector 38 selects either the column address CA held in the address holding unit 35 or the row address selected by the selector 37 according to the update signal UPDT output from the ACT detection unit 32, and serves as an address MAD for the DRAM 20. Output.

  The current page holding unit 39 holds the row address RA output from the selector 37 at the timing of the update signal UPDT, and gives it to the comparison unit 36 and the previous page holding unit 40 as current page information PAGE. The previous page holding unit 40 is composed of n stages of shift registers, and shifts and holds the current page information PAGE of the current page holding unit 39 at the timing of the update signal UPDT, so that the past n items accessed so far It keeps the history of the page.

  The page information PAGE1 to PAGEEn held in the registers of each stage of the previous page holding unit 40 is given to the next page prediction unit 41 and the selector 42. The next page predicting unit 41 predicts a page that has been accessed the most frequently among the pages accessed n times in the past as a page to be accessed next, and a page register that stores the predicted page Are output as the selection signal SEL3. For example, the next page prediction unit 41 includes a comparator for comparing with the contents of other page registers for each page register of each stage, and calculates the number of coincidence by adding the detection results of these comparators with an adder. The access frequency is stored in the frequency register corresponding to each page register. Then, the maximum register determination unit determines the number of the frequency register having the maximum number of held frequencies, and outputs the register number as the selection signal SEL3.

  The selector 42 selects the page information that is the content of the corresponding page register of the previous page holding unit 40 in accordance with the selection signal SEL3, and outputs it to the selector 37 as the next page information NPAGE.

  FIG. 7 is a timing chart showing the operation of FIG. FIG. 5 shows the access from the system bus and the operation of the current page information PAGE of the current page holding unit 39 and the command CMD to the DRAM 20 and the timer 34 which change correspondingly.

First, an access request to the row address RA = page0 is given from the system bus, and an ACT command and a CAS command corresponding to the DRAM 20 are issued (a).
When the ACT command is issued, the ACT detection unit 32 outputs the update signal UPDT, and the current page information PAGE of the current page holding unit 39 is updated to page0. In the previous page holding unit 40, the previous access row address held in the current page holding unit 39 until then is stored as previous page information PAGE1. Following the access in (a), when an access with the row address = page 0 is requested twice from the system bus, the comparison unit 36 sets the current page information PAGE of the current page holding unit 39 to the row address of the access request. Since this is done, the page hit signal HIT is output. In the command generation unit 31, since the page hit signal HIT is given, the ACT command is not issued and only the CAS command is issued.

  Next, when an access request to the row address RA = page1 is given from the system bus, since the current page information PAGE of the current page holding unit 39 is different from the row address of the access request in the comparison unit 36, the page hit signal HIT Stop output. As a result, the command generation unit 31 issues an ACT command and a CAS command (b). When the ACT command for page1 is issued, the update signal UPDT is output from the ACT detection unit 32, and the current page information PAGE in the current page holding unit 39 is updated to page1. Furthermore, the previous page storage unit 40 newly stores the row address (page 0) stored in the current page storage unit 39 until then. In four accesses of the same row address (= page1) following the access in (b), the ACT command is not issued as in the access in (a), and only the CAS command is issued.

  Next, an access request to page 14, page 0, and page 2 is given as a row address from the system bus, and the current page information PAGE of the current page holding unit 39 is updated in the order of page 14 → page 0 → page 2. In the previous page holding unit 40, the shift operation is sequentially performed at the timing when the ACT command for each page is issued. Thus, the contents of the page registers of the previous page holding unit 40 at the time when the last access (c) in page 2 is performed are page 0, page 14, page 1, page 0 in order from the latest one.

  Furthermore, if the access request from the system bus is interrupted for a while after the last access (c) of page2, a timeout occurs in the timer 34 after a certain time, and the row address request signal RRQ is output (d ). At this time, the next page prediction unit 41 determines the register number corresponding to the page having the highest access frequency among the page registers of the previous page holding unit 40, and outputs the selection signal SEL3. Thus, the row address having the highest access frequency in the past by the selector 42 is output as the next page information NPAGE. In this case, page0 is selected twice and the others are set once or zero, so page0 is selected. The page 0 of the next page information NPAGE is selected by the selector 37 and is output to the selector 38 and is given to the current page holding unit 39 and held therein. The row address request signal RRQ is also supplied to the command generation unit 31, whereby an ACT command is issued for the row address = page 0, and the current page information PAGE in the current page holding unit 39 is updated to page 0. .

  At this point, since there is no access request from the system bus, no actual access to the DRAM 20 is performed. Thereafter, when an access request from the system bus is generated, if it is for the row address = page 0 (e), the page hit signal HIT is output from the comparison unit 36. A CAS command is issued immediately without issuing. If the prediction is wrong and the access request is for another page, the page hit signal HIT from the comparison unit 36 is not output, so the command generation unit 31 issues an ACT command.

  As described above, the memory control circuit according to the second embodiment includes the next page predicting unit 41 that predicts the page with the highest access frequency as the next access page based on the history of pages accessed in the past, and the constant. A command detection unit 33 and a timer 34 for rewriting the predicted next page information NPAGE as the current page information PAGE when the time access is interrupted. This increases the possibility that the number of ACT commands issued can be reduced, and there is an advantage that the speed of continuous access across different pages can be increased.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) Although the write data signal is omitted in FIG. 1 and the read / write data signal is omitted in FIG. 6, both can be similarly applied to the read / write data signal.
(B) The configuration of the next page prediction unit 41 in FIG. 6 is an example, and can be changed to a configuration having the same function.

1 is a configuration diagram of a memory control circuit showing Embodiment 1 of the present invention. FIG. It is a block diagram of the conventional memory control circuit. It is a timing chart which shows operation (1) of Drawing 2. It is a timing chart which shows operation (2) of Drawing 2. It is a timing chart which shows the operation | movement of FIG. It is a block diagram of the memory control circuit which shows Example 2 of this invention. 7 is a timing chart showing the operation of FIG. 6.

Explanation of symbols

1 to n Bus master 10A, 30 Memory control circuit 11A Port control unit 12A Bus arbitration unit 13, 14, 37, 38, 42 Selector 15 Precharge detection unit 16 Current page register 17 Precharge control unit 31 Command generation unit 32 ACT detection unit 33 Command detection unit 34 Timer 35 Address holding unit 36 Comparison unit 39 Current page holding unit 40 Previous page holding unit 41 Next page prediction unit

Claims (2)

Provided corresponding to a plurality of bus masters, converts an access signal for a common memory given by the corresponding bus master into an address and a control command corresponding to the memory, and the access request signal and the address are currently being accessed by the memory. A plurality of port control units for outputting a coincidence detection signal indicating whether or not the same page as
In accordance with an access request signal output from the plurality of port control units, a first selection signal for permitting access to one port control unit is output, and a second port control unit for permitting access next is specified. A bus arbitration unit that outputs a selection signal;
A first selector that selects an address and a control command output from the plurality of port control units according to the first selection signal and supplies the selected command to the memory;
A second selector for selecting and outputting a coincidence detection signal output from the plurality of port control units according to the second selection signal;
A precharge control unit that gives a precharge command to the memory at a predetermined timing before the end of the current access in accordance with the coincidence detection signal selected by the second selector;
A memory control circuit comprising: A control command corresponding to the memory to be accessed is generated based on the access control signal given from the bus master, and when the coincidence detection signal is not given, the generated control command is output, and the coincidence detection signal is given. Command generation means for stopping the output of the command to enable the page to be accessed when
Current page holding means for holding page information in which access is set to be valid among the pages of the memory;
Comparing means for comparing whether or not the address to be accessed of the memory given from the bus master corresponds to a page held in the current page holding means, and outputs a match detection signal when they match.
A next page predicting means for predicting a page to be accessed next based on the frequency of pages held in the current page holding means in the past and outputting next page information;
Storage means for storing next page information output from the next page predicting means as the page information in the current page holding means when a command output from the command generating means is interrupted for a certain period of time;
A memory control circuit comprising:

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