JPS60119695A - Dynamic ram - Google Patents

Abstract

PURPOSE:To set a refresh time to a required minimum value by detecting one circulation of a refresh address to complete the refresh operation, therby omitting useless (2nd times) refresh cycle. CONSTITUTION:When a refresh control signal -REF goes to a low level, a detection circuit LOG is reset, an output signal goes to a high level, an output signal phi1 of a NOR gate G1 rises to a high level so as to start a timer circuit TM. A refresh address counter CONT proceeds advancing operation by a pulse signal phi2, a word line is selected by address signals a0-a8 so as to attain refresh operation. When the detection circuit LOG detects one circulation of the counter CONT, an output signal goes to a low level, and the timer circuit TM is reset forcibly, and then the advance pulse is not formed. A memory system controller brings the signal -REF to high level by the low level of the busy signal BUSY so as to complete the refresh cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Background Art] The present invention relates to a dynamic RAM (random access memory), and, for example, to a technique effective for a dynamic RAM with a built-in automatic refresh circuit.

[Technical background]

A memory cell in a dynamic RAM is composed of a storage capacitor that stores information in the form of charges and a MOSFET for address selection. In a memory cell formed on a semiconductor substrate, the charge accumulated in the capacitor decreases over time due to leakage current or the like. Therefore, in order to always store accurate information in memory cells, it is necessary to read out the information stored in memory cells before the information is lost.
It is necessary to amplify this and write it into the same memory cell again, a so-called refresh operation.
``Electronic Technology J Magazine (DVo
12-3, NO3 (DflP30 to 33) are known automatic refresh circuits. That is, a dynamic RAM is provided with an external terminal for refresh control, and a refresh control signal of a predetermined level is sent to this external terminal. By applying qREF, dynamic RA
An auto-refresh function in which multiple memory cells in M are automatically refreshed, and the above-mentioned refresh signal RE
A self-refresh function is provided which operates a built-in timer circuit by keeping F at a predetermined level and performs the above-mentioned refresh operation at regular intervals.

The inventor's research has revealed that such an automatic refresh circuit has the following problems. That is, in the above automatic refresh method, the timer circuit is activated by keeping the refresh control signal R-EF at a low level for a certain period of time (for example, for about 2M when there are 128 word lines). By doing so, all the word lines are successively selected and the refresh of all memory cells is completed. However, the frequency of the address increment pulse generated by the timer circuit varies depending on manufacturing conditions, temperature dependence, and the like. For this reason, a certain margin is set for the time during which the lower level of the refresh control signal 11 is kept at a low level, taking into account the worst conditions. Therefore, in reality, 128 or more refresh cycles are performed, resulting in a disadvantage that some wasted refresh cycles occur.

[Purpose of the invention]

An object of the present invention is to provide a dynamic RAM in which the refresh time can be set to the minimum necessary.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief summary of typical inventions disclosed in this application is as follows.

In other words, by detecting one round of the refresh address,
By terminating the refresh operation and sending the signal to the outside, a wasteful (second) refresh cycle is omitted.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention.

In the example circuit shown in the figure, O3FE between n channels
I G F E T (I naula
ted(fate Field Effect Tra
This will be explained using ``nsistor'' as an example.

A 1-bit memory cell MC, as shown as a representative, has an information storage capacitor Cs and an address selection M
03FETQm, and the information of logic "1" and "θ" is stored in the form of a capacitor Cs, whether or not a charge is generated.

To read information, turn on the MO5FETQm, connect the capacitor c3 to the common data line DL, and sense how the potential of the data line DL changes depending on the amount of charge accumulated in the capacitor Cs. carried out by.

Memory cells MC are formed small and common data II
Since many memory cells are connected to the IADL to form a highly integrated and large capacity memory matrix, the capacitor C
The relationship between s and the stray capacitance Co (not shown) of the common data line DL is that the ratio of Cs/Co is a very small value.Therefore, the amount of charge accumulated in the capacitor Cs increases the capacitance of the data line DL. The potential change is a very small signal.

A dummy cell DC is provided as a reference for detecting such a minute signal. This dummy cell DC is
The capacity fiklli of the capacitor Cd is the memory cell MC.
It is made under the same manufacturing conditions and the same design constants as the memory cell MC, except that it is approximately half the size of the capacitor Cs of the memory cell MC. Capacitor Cd is connected to MO before addressing.
It is charged to ground potential by 3FETQd'.

As described above, since the capacitor Cd is set to have a capacitance value that is approximately half that of the capacitor Ca, it forms a reference voltage that is approximately half the value of the read signal from the memory cell MC.

In the figure, SA is a sense amplifier that expands the difference in potential change caused by the above-mentioned addressing into a sensing period determined by a timing signal (sense amplifier control signal) φpal+φpa2 (its operation will be described later).
, its input/output nodes are coupled to a pair of parallelly arranged complementary data MADL, DL. Complementary data line DL
, DL are made equal in order to increase detection accuracy, and one dummy cell is coupled to each of DL and DL. In addition, each memory cell M
C is coupled between one word line WL and one of the complementary pair of data lines. Since each word line WL intersects both data line pairs, even if a noise component generated on the word line WL is transferred to the data line due to capacitive coupling, the noise component crosses both data line pairs DL.

It appears equally at DL and is canceled by the differential sense amplifier SA.

In the above addressing, complementary data line pair DL, D
When a memory cell MC coupled to one of the data lines L is selected, one of the pair of dummy word lines DWL, DWL is selected so that the dummy cell DC is always coupled to the other data line.

The sense amplifier SA has a pair of cross-wired MO3
It has FETQI and Q2, and due to their positive feedback,
A minute signal appearing on complementary data lines DL, DL is differentially amplified. This positive feedback operation is performed in two stages, and the MO3FE has relatively low conductance characteristics.
It starts at the same time that TQ7 starts to conduct by a relatively early timing signal φp'al, and based on the potential difference given to complementary data 1jlDL and DL by addressing, the higher data line potential is at a slow speed, and the lower one is at a faster speed. As the difference widens, the difference continues to decline.
At this time, at the timing when the voltage difference becomes large to a certain extent, the MO3FE which has a relatively large conductance characteristic
Since TQ8 is made conductive by the timing signal φpa2, the lower data line potential rapidly drops. By operating the sense amplifier SA in two stages in this manner, the drop in the higher potential is prevented.

In this way, when the lower potential drops below the threshold voltage of the cross-coupled MO3FET, the positive feedback operation ends, and the higher potential drops lower than the power supply voltage Vcc and remains at a potential higher than the threshold voltage. , the lower potential eventually reaches the ground potential (Ov).

During the above-mentioned addressing, the stored information in the memory cell MC, which is about to be destroyed, is recovered by directly receiving the high-level or low-level potential obtained by this sensing operation. However, as described above, if the high level drops by more than a certain level with respect to the power supply voltage Vcc, a malfunction that is read as logic 109 occurs while reading and rewriting are repeated several times. An active restore circuit AR is provided to prevent this malfunction. This active restore circuit AR has the function of selectively bootstrapping only high level signals to the potential of power supply voltage Vcc without having any effect on low level signals.

A data line pair DL, which is shown as a representative in the figure,
DL is MO3FETQ that constitutes column switch CW
3. Ecommon complementary data line pair CDL, CDL via Q4
connected to. Similar MO3FETQ5. It is connected to the common complementary data line pair CDL, CDL via Q6. The common complementary data line pair CDL, CDL is connected to an input terminal of a data output buffer DOJ including an output amplifier and an output terminal of a data input buffer sofa DIR.

The row decoder and column decoder RC-DCR receives the internal complementary address signal formed by the address padzer ADB, forms one word line, a dummy word line, and a column switch selection signal to address memory cells and dummy cells. In other words, the external address signals AXO to AXi are taken into the address buffer ADH in synchronization with the timing signal φar generated by the row address strobe signal RAS, and the external address signals AXO to AXi are taken into the address buffer ADH.
CR and word line selection timing signal φ
A predetermined word line and dummy word line selection operation is performed by X. Then, external address signals AYO to AYi are taken into address buffer ADB in synchronization with timing signal φac generated by column address strobe signal CAS, and transmitted to column decoder C-DCR.
A data line selection operation is performed using a data line selection timing signal φy.

The timing control circuit TC receives address strobe signals RAS, CAS and a write enable signal WE supplied from the outside, and forms various timing signals in addition to the representative timing signals shown above.

The refresh control circuit REFC includes, but is not particularly limited to, a timer circuit and an internal row address signal axO-ax.
It includes a counter circuit that forms a counter circuit i, and a detection circuit that detects one round of this counter circuit and stops the refresh operation, and is activated by a refresh signal REF supplied from an external terminal. Further, the output signal BUSY of the detection circuit is sent out from an external terminal.

FIG. 2 shows a circuit diagram of an embodiment of the refresh control circuit REFC.

Denoted by the circuit symbol TM is a timer circuit that monitors the level of the refresh control signal REF to identify the operating mode of auto or self-refresh operation. A refresh address counter is designated by the circuit symbol C0NT and forms internal complementary address signals 10-18 for refresh. These timer circuit TM and refresh address counter C0NT are controlled by the following logic gate circuit.

A refresh control signal REV supplied from an external terminal is supplied to one input of a NOR gate circuit G1. The output signal φ3 of the timer circuit TM is supplied to the other input of the NOR gate circuit G1. The output signal φ1 of this NOR gate circuit G1 is supplied on the one hand as a starting signal to the timer circuit TM,
On the other hand, the signal is inverted and delayed through the delay circuit DL and the inverter circuit IV. This inverted delay signal and the output signal φ1 are input to an AND gate circuit G2. As a result, a pulse φ2 is synchronized with the rise of the signal φ1 and has a pulse width of the time set by the delay circuit DL.
is formed. This pulse φ2 is input to the refresh address counter C0NT and used for its refresh address increment operation.

In this embodiment, the number of stitches in one revolution is detected by the detection circuit LOG which identifies the level of the address signal generated by the refresh address counter C0NT, although this is not particularly limited. This detection circuit LOG
On the one hand, the detection signal of the above-mentioned timer circuit TM is used as the cent signal R, although it is not particularly limited.
On the other hand, it is sent out as a busy signal BUSY from the external terminal. Note that the detection circuit LOG is reset by a refresh control signal REF.

The operation of the refresh control circuit REFC of this embodiment will be explained according to the timing diagram of FIG.

When the refresh control signal REF supplied from the external terminal changes to low level (logic "0°"), the detection circuit LOG is reset and its output signal becomes high level.This allows the busy state to be notified externally. Furthermore, as will be described later, since the timer circuit TM is not activated, its output signal φ3 is at a low level, so the output signal φ1 of the NOR gate circuit G1 is at a high level (! !i logic “1”)
stand up. This output signal φ1 activates the timer circuit TM on the one hand. As a result, the timer circuit TM is activated and performs a timing operation for the set time. On the other hand, the output signal φ1 is converted into a pulse signal φ2 having a pulse width set by the delay circuit DL. That is, the rise of the pulse signal φ2 is synchronized with the rise of the signal φ1, and the fall thereof is defined by the delay time of the delay circuit DL. This pulse signal φ2 causes the refresh address counter C0NT to perform its increment operation. Also,
Due to the change of the signal φ1 to high level, the first
The multiplexer MPX in the figure is switched to the refresh address counter C0NT side.

Therefore, the refresh address counter C0N
Address signals 10 to 1 changed by stepping operation of T
8, a word line selection operation is performed and a refresh operation is performed.

If the refresh control signal REF remains at the low level, the timer circuit TM sets its output signal φ3 to the H/f level after a certain period of time has elapsed. This allows N OR
The output of the gate circuit G1 (M signal φ1 becomes low level).

As a result, the timer circuit TM is once reset. Therefore, the output signal φ3 of timer circuit TM changes to low level again due to the rising operation of timer circuit TM. As a result, the output signal φ1 of the NOR gate circuit G1 becomes high level, and the same operation as described above is repeated. The above operation is repeated until the detection circuit LOG completes one cycle (the completion of the refresh operation for all memory cells) while the refresh control signal REF continues to be at a low level. That is, the detection circuit LOG is the refresh address counter c.

This is because when one rotation of NT is detected, the output signal is set to a low level and the timer circuit '1' M is forcibly reset, so that the above-mentioned step pulse is no longer generated.

Further, since the busy signal BUSY is sent at a low level, the memory system control device (not shown) sets the refresh control signal REF to a high level in response to the low level of the busy signal BUSY, and ends the refresh cycle of the dynamic RAM. .

Note that if the low level period of the refresh control signal 101 is shortened to less than the set time of the timer circuit TM, the pulse signal φ2 is generated in synchronization with the low level of the refresh control signal nEF, so that this refresh control An auto-refresh operation is performed on the signal according to the period of 〒F. In this case, the detection circuit LO
Since G is reset, the detection circuit LOG does not perform the above operation.

[Rino Ka]

(1) In the self-refresh operation performed by keeping the refresh control signal REF at a low level, all memory actually performed is detected by detecting one rotation of the refresh address counter regardless of °C, manufacturing conditions, or temperature changes. When the cell refresh operation is completed, the operation can be stopped. This has the effect of omitting unnecessary fresh cycles.

(2) According to (11) above, the time required for the refresh operation can be minimized, so that the time required for writing or reading can be increased accordingly.

(3) According to the above (1), unnecessary fresh cycles can be omitted, so that an effect can be obtained that power consumption can be reduced accordingly.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the detection circuit LOG may be constituted by a counter circuit that detects one cycle of the refresher address, and its detection output may utilize the overflow signal. Further, in the embodiment of FIG. 2, the detection output formed by the detection circuit LOG may stop the refresh operation by closing the OR gate circuit G1 or the AND gate circuit G2. The pulse for incrementing the refresh address may be generated by a transmitting circuit.

[Application field]

The present invention can be widely used in dynamic RAMs that do not require refresh operations.

[Brief explanation of the drawing]

FIG. 1 shows a dynamic type R showing an embodiment of the present invention.
A block diagram of AM. FIG. 2 is a circuit diagram showing an embodiment of the refresh control circuit in FIG. 1. FIG. 3 is a timing chart showing an example of the operation of the embodiment circuit in FIG.

Claims (1)

[Scope of Claims] 1. A timer circuit that is activated in response to a fresh control signal supplied from an external terminal, continues to be supplied for a certain period of time, or identifies a fresh control signal, and a refresh address according to the output signal of this timer circuit. automatic refresh control that includes an address counter that increments the address counter, and a detection circuit that detects one rotation of the address counter, and that terminates the refresh operation based on the detection signal of the detection circuit, and sends out the refresh end signal from an external terminal. A dynamic RAM characterized by comprising a circuit. 2. The dynamic RAM according to claim 1, wherein the address counter increments the refresh address each time the refresh address is supplied within the certain period of time or every time a refresh control signal arrives.