JPS61170993A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To give the same function as that of a static RAM by providing an amplifier circuit reading an electric charge stored in an information storage capacitor and applying rewrite to a refresh exclusive circuit. CONSTITUTION:One end of a refresh MOSFET Qm' is connected to a connecting point between an information storage capacitor Cs and an address selection MOSFET Qm constituting a memory cell. The other end of the refresh MOSFET Qm' is connected to data DL', -DL' for refresh corresponding to the said memory cell. The refresh data lines DL', -DL' are connected to the input/output of an amplifier circuit comprising MOSFETs Q1', Q2' smilar to a sense amplifier SA. Thus, a refresh MOSFET is added to the dynamic memory cell comprising two elements of a capacitor and an MOSFET to constitute the memory cell with a comparatively less number of elements, three elements.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is effective for use in dynamic RAM (random access memory).

[Background technology]

A memory cell in a dynamic RAM is composed of a storage capacitor that stores information in the form of charges and a MOS FET for address selection. As a result, dynamic RAM can achieve a large storage capacity, but on the other hand, the charge accumulated in the capacitor of the memory cell formed on the semiconductor substrate decreases over time due to leakage current, etc. In order to always store accurate information in a memory cell, it is necessary to read out the information stored in the memory cell before it is lost, amplify it, and write it back into the same memory cell. It is necessary to perform a so-called refresh operation.

For example, as an automatic refresh method for memory cells in a 64-bit dynamic RAM, the automatic refresh circuit shown in "Electronic Technology 1 Magazine, Vol. 123, No. 3, pp. 3-33" is known. In the refresh circuit, a control signal must be supplied from the outside, and writing/reading is prohibited during the refresh period, making handling inconvenient.

On the other hand, a static RAM does not require the above-mentioned refresh operation, so it is easier to handle. However, since static type RAM uses static type flip-flop circuits as memory cells, it requires a relatively large number of elements (6), which is disadvantageous from the perspective of increasing storage capacity. Become.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device that has a large storage capacity and is easy to handle.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, an information storage capacitor and an address selection MO
A memory cell consisting of an SFET is provided with a refresh-only circuit for reading and rewriting the charge stored in the information storage capacitor, and has substantially the same function as a static RAM. It is something that can be done.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention. Each circuit in the figure is formed on a semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

In the example circuit shown in the figure, the O3FE between N channels
I G F E T (I n5ula
tedGate Field Effect Tra
This will be explained using ``nsistor'' as an example.

The 1-bit memory cell MC, as shown as a representative, has an address selection MOS FET Qm, and an information storage whose one electrode is coupled to Qm and the other electrode is maintained at the circuit power supply voltage level. It consists of a capacitor C3 and is logic "1".

Information of "0" is stored in correspondence with whether the capacitor Cs has a charge or not.

To read information, turn on the MOS FET Qm, connect the capacitor C3 to the common data line DL, and check how the potential of the data line DL changes depending on the amount of charge accumulated in the capacitor Cs. This is done by sensing what happens.

Although not particularly limited, a dummy cell DC is provided as a reference for detecting such a minute signal.

This dummy cell DC is manufactured under the same manufacturing conditions and the same design constants as the memory cell MC, except that the capacitance value of the capacitor Cd is approximately half that of the capacitor C3 of the memory cell MC. The capacitor Cd receives a timing signal φd generated prior to addressing, and is connected to a MOSFE placed between the capacitor Cd and the ground point of the circuit.
It is charged to the power supply voltage by TQd'.

As described above, since the capacitor Cd is set to have a capacitance value that is approximately half that of the capacitor C3, it forms a reference voltage that is equal to half the read signal from the memory cell MC.

In the same figure, SA is a sense amplifier that expands the difference in potential change caused by the above-mentioned addressing into a sensing period determined by a timing signal (sense amplifier control signal) Its input and output nodes are coupled to lines DL and DL. This sense amplifier SA consists of a pair of cross-wired MOSFETs.
E.T.Q.I.

Q2, and the positive feedback action of these differentially amplifies minute signals appearing on the complementary data lines DL, DL.

The numbers of memory cells coupled to complementary data lines DL, DL are made equal to increase detection accuracy, and one dummy cell is coupled to each of DL, DL. Also,
Each memory cell MC is coupled between one word line WL and one of a complementary pair of data lines. Since each word line WL crosses both data line pairs, even if a noise component generated on the word line WL is transferred to the data line due to capacitive coupling, the noise component will be transmitted to both data line pairs DL, DL. appear equally,
This is canceled out by the differential sense amplifier SA.

In the above addressing, complementary data line pair DL, D
When a memory cell MC coupled to one of the data lines L is selected, one of the pair of dummy word lines DWL, DWL is selected so that the dummy cell DC is always coupled to the other data line.

During the above-mentioned addressing, the stored information in the memory cell MC, which is about to be destroyed, is recovered by directly receiving the high-level or low-level potential obtained by this sensing operation. However, as described above, when the high level drops by a certain level or more with respect to the power supply voltage Vcc, a malfunction occurs in which the data is read as a logic "0" while reading and rewriting are repeated several times. An active restore circuit AR is provided to prevent this malfunction. The active restore circuit AR has the function of selectively boosting only the high level signal to the potential of the power supply voltage Vcc without affecting the low level signal in any way based on the timing signal φrs.

The data line shown as a representative in the figure
A pair of DL and DL are MOSFETQ3.DL that constitute the column switch CW. It is connected to the common complementary data line pair CDL, CDL via Q4. This common complementary data line pair CDL, CDL is connected to one terminal of an input/output circuit I10 consisting of a data output cover sofa and a data input cover sofa including a main amplifier and an output circuit, as will be described later.

The row decoder and column decoder R, C-DCR have a row address buffer and a column address buffer R, C.
-Receives the internal complementary address signal formed by ADB,
Addressing of memory cells and dummy cells is performed by forming one word line, a dummy word line, and a column switch selection signal. That is, in synchronization with the timing signal φar generated by the row address strobe signal qRAS, the row address buffer R-ADH takes in address signals AXO to AXl supplied through external terminals, holds them, and outputs them to the row decoder R-DCH. tell to. The row decoder R-DCR decodes the transmitted address signal and outputs the word line selection timing signal φ.
A predetermined word line and dummy word line selection operation is performed by X.

On the other hand, the column address buffer C-ADH is constituted by a static type circuit which is activated by a timing signal φac generated by a column address strobe signal CAS, although this is not particularly limited. This causes the address signals AYO to A supplied through the external terminals to
An internal complementary address signal according to YI is formed and transmitted to the column decoder C-DCH, which is similarly configured by a static type circuit, although this is not particularly limited. The column decoder C-DCR decodes the transmitted address signal and performs a data line selection operation based on the data line selection timing signal φy.

The timing control circuit TC receives a row address strobe signal RAS supplied through an external terminal.

In response to the column address strobe signal CAS and write enable signal WE, the various internal timing signals described above are generated.

In this embodiment, the following refresh-only circuit is provided in order to completely automate the refresh operation of the dynamic memory cell so that it can be treated from the outside in substantially the same manner as a static RAM.

One end of the refresh MOSFET Q m ′ is connected to the connection point between the information storage capacitor Cs and the address selection MOSFET Qm that constitute the memory cell. This refresh MOSFETQm'
The other end is connected to refresh data lines DL'' and DL' corresponding to the memory cells.

Each DL' is provided with a dummy cell DC' similar to the above.

The refresh data lines DL", DL' are connected to an amplifying MOSFET Ql' similar to the sense amplifier SA.
, Q2'. In addition, the refresh data line DL'
, DL' is provided with an active restore circuit AR' similar to the above in order to compensate for the read high level that has once dropped due to the amplification operation of the amplification circuit.

In the figure, only one column of memory array is shown, but refresh MOSFETs arranged in the same row
The gate of Qm is coupled to the refresh word line WL". That is, the refresh complementary data line D
L", DL' and the refresh word line WL" are
They are arranged adjacent to corresponding complementary data lines DL, DL and word lines WL of the memory array.

The refresh word line WL' and the refresh dummy word lines DWL'' and DWL' are as follows.

A decoder for freshier R-OCR' is constructed of circuits similar to or similar to the above row address decoder R-DCR.
selected by

This refresh decoder R-DCR' is supplied with a refresh address signal generated by a refresh address counter C0UNT. One cycle of the refresh address counter C0UNT is set to the time required to refresh the memory cells.
lRefresh control circuit R
EFC is the refresh address counter C0UN mentioned above.
The step pulse supplied to T and the refresh amplifier circuit and active restore circuit A according to this pulse.
Timing signal φpa' + φrs supplied to R°
' to form.

Note that, although not shown, the refresh control circuit REFC is provided with an address comparison circuit in order to avoid conflict between the refresh operation and the read/write operation. When this address comparison circuit obtains a match output between the row address signal supplied from the external terminal and the address signal formed by the address counter C0UNT, the refresh operation at the address is prohibited and the address counter C0UNT is The children will be asked to walk on the sidewalk. This is because the reading/writing described above substantially refreshes the address. Furthermore, if a read/write access is made to an address that is being refreshed, execution of the read/write access is delayed until the refresh is completed. In order to eliminate the above-mentioned limitations on write/M-extraction operations, the above-mentioned refresh complementary data iJl!
DL'DL' is also provided with a column switch circuit,
When a read/write access is made to an address during a refresh operation, a selection operation may be performed on the column switch circuit according to a column address signal, and the read/write may be executed.

〔effect〕

(1) A dynamic memory cell composed of two elements, a capacitor and a MOSFET, is
A memory cell can be configured with a relatively small number of elements, 3 elements in total by adding an OS FET.

Therefore, even if peripheral circuits such as refresh amplifier circuits, decoder circuits, and address counter circuits are included, the total number of elements can be reduced compared to static RAM, resulting in a large storage capacity. It will be done.

(2) Since a dedicated refresh circuit is used, as long as the refresh address and the read/write address do not overlap, both operations can be performed in parallel, so when viewed from the outside, it is equivalent to a static RAM. The effect is that it can be handled.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the row/column address signals may be supplied from independent external terminals. In this case, changes in the address signals are detected to form a time-series timing signal for the internal dynamic circuit. Just do it. Furthermore, the read reference voltage may be one using a dummy cell or a voltage of Vcc/2 formed by shorting the high level and low level of the complementary data line. The refresh amplifier circuit can take various embodiments, such as one using a latch-type CMOS inverter circuit to which an operating voltage is supplied by a timing signal.

[Application field]

The present invention can be widely used as a semiconductor memory device.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. MC...Memory cell, DC...Dummy cell, CW...Column switch, SA...Sense amplifier, AR, AR'
・・Active restore circuit, RlC-DCR・・Row/column decoder, R-DCR゛・・Refresh decoder, C0UNT・・Refresh address counter, REFC・・Refresh control circuit, R,C−
ADB...Row/column address buffer, DOB...
Data output buffer, DIB... data input buffer,
TC...timing control circuit

Claims (1)

[Claims] 1. Information storage capacitor and address selection MOSFE
a memory array in which memory cells are arranged in a matrix, a refresh MOSFET having one end connected to a connection point between the information storage capacitor and the address selection MOSFET, and the refresh MOSFET.
A semiconductor memory device comprising: a refresh-only amplifier circuit whose input/output terminal is connected to the other end of the ET; and a refresh control circuit that controls the selection operation of the refresh MOSFET and the operation of the amplifier circuit. . 2. The refresh-only amplifier circuit described above is provided in common with the refresh data line to which the other ends of the refresh MOSFETs arranged in the same column are commonly connected, and the gates of the refresh MOSFETs arranged in the same row are The refresh control circuit includes an address counter that generates a refresh address, and decodes the output signal of this address counter to control the refresh MOS.
Claim 1, characterized in that the refresh decoder circuit is comprised of a refresh decoder circuit that selects a refresh word line to which a gate of an FET is coupled, and a timing generation circuit that generates an operation timing signal for an amplifier circuit. The semiconductor storage device described above.