JPH04129088A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase operational speed of a sense amplifier, to increase resistance against unbalance of characteristic and to prolong the data holding time by providing cell counter-electrode lines and a supply potential control circuit to return the levels of cell counter-electrode lines to the specified level between a 1st and a 2nd power source potentials. CONSTITUTION:The cell counter-electrode lines PL1-PLM are provided for every column of a memory cell array 1, and after the sense amplifiers SA1-SAN are activated, the cell counter-electrode lines PL1-PLM are made to the 1st power source potential at the column unit from the intermediate level between the 1st and 2nd power source potentials. Next, word lines WL1-WLM are made to the intermediate level between the 1st and 2nd power source potentials from a selection level, and also the supply potential control circuit 2 to return the cell counter-electrode lines PL1-PLM to the intermediate level is provided. By this arrangement, the high level potential of memory cell can be made higher than the power source potential at the high potential side. Thus, the operational speed of sense amplifier and the resistance for unbalance of characteristic can be improved, and also a retention time of data can be prolonged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a dynamic semiconductor memory device having a configuration in which one-transistor, one-capacitor type memory cells are arranged.

[Conventional technology]

An example of a conventional semiconductor memory device of this type is shown in FIG.

MC11 to MCyrN are connected to one transistor Ql.

NKI to NKN are memory cells M CKI - M CKN
The node between capacitor CI and transistor Ql in PL
is a cell counter electrode line that commonly connects the counter electrodes of the capacitors CI of each memory cell MCI, to MCMN, and is supplied with a voltage VPL of Vcc/2 level.

WL1-WLM are word lines, and WD1-WDM indicates a word driver circuit that drives the word lines WL1-WLM.

Next, the operation of this example will be explained.

FIG. 4 shows typical operating waveforms of the semiconductor memory device shown in FIG. 3.

During the reset cycle during which the row address strobe [number RAS is a high level precharge period]
BL, -BLN, and BLN are precharged to, for example, an intermediate potential Vcc/2 between the power supply potential VCC and the ground potential (vas=OV).

When the row address strobe signal RAS becomes a low-level active cycle, one of the word lines W L 1 to W L M is selected by an externally applied address signal.
This word line, for example, WLK, is selected and the power supply potential vc
c K rises. Then, each transistor Ql of the memory cells MCKI to MCKN connected to the word line WLK is turned on, so that charge is exchanged between the capacitor C1 of each memory cell array to MCKN and the bit line BLl""'BLN. As a result, the potential of each bit line BLl-BLN changes minutely.

Next, sense amplifier 8A! ~SAN is activated and the paired bit line BL1. The minute difference signal between BL1 to BLN and BL is amplified, and for example, the potential of the bit line BLL rises to the power supply potential VCC, and the bit line BLL rises to the ground potential Vs.
s (=OV).

On the other hand, the memory cells MCK, ~MCKN are connected to the bit lines BLl-BLN through the transistors Ql, and the nine nodes NK1 = NKN are the threshold voltage V of the transistor Ql - step drop, that is, (Vcc - Vt) , or amplified to ground potential VSS.

When the row address strobe signal 几As rises and a limit set cycle begins, the selected word line WLK, whose power supply potential VCC has been rising, falls to the ground potential VSS, turning off each transistor Ql of the memory cells MCK, ~MCKN. Therefore, each node NKI to NKN is (VCC-v
(D) or VSS level, and data is written.

In addition, each capacitor C of memory cells MCI1-MCMN
A voltage VPL is applied to the counter electrode of cell counter electrode 1 via the cell counter electrode line PL, and is precharged to a constant level, for example, Vcc/2, throughout the reset, to cycle, and active cycles.

[Problem to be solved by the invention]

In this conventional semiconductor memory device, the cell counter electrode line PL is at a constant level, and the potential of the word line in the selected state is the power supply potential VCC, so the data written to the memory cell is at the potential of the word line. Even when the paired bit lines are amplified to the power supply potential VCC and the ground potential vss, the maximum on the high level side (■cc-vT) The drawback was that it could only be written up to the level of . When ■τ of transistor Q1 of each memory cell becomes approximately 1.5 V due to the substrate bias effect, the above write level becomes ■cc=5. At OV, it is 3.5V.

Therefore, there are disadvantages in that the sense amplifier operates slowly, has low resistance to unbalanced characteristics, and has a short data retention time.

[Means to solve the problem]

A semiconductor memory device of the present invention includes a plurality of 1-transistor l-capacitor type memory cells arranged in a matrix in a row direction and a column direction, and writes and reads data to and from the memory cells in a selected state. provided corresponding to a cell array and each column of this memory cell array,
first and second bit lines connected to each memory cell in the corresponding column to supply data to the memory cell in the selected state and transmit data from the memory cell; A word line is provided corresponding to each row of the cell array and selects each memory cell in the corresponding row, and a word line is provided corresponding to each of the first and second bit lines and between the corresponding bit lines. a sense amplifier for amplifying the differential potential of the memory cell array, a cell counter electrode line provided corresponding to each row of the memory cell array and connected to the counter electrode of the capacitor of each memory cell in the corresponding row, and for each row of the memory cell array, The word line becomes a selection level and becomes a first voltage during the amplification operation of the potential difference between the first and second throat lines by the sense amplifier, and the word line becomes a selection level with a second tie. a supply potential control circuit that maintains a predetermined potential between the first and second power supply potentials for a predetermined period of time and returns the level of the cell counter electrode line to a predetermined level between the first and second power supply potentials; have.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

This embodiment includes a plurality of 1-transistor capacitor type memory cells MC11-MCN arranged in a matrix in 9 columns in the row direction, and allows writing and reading of data to and from a selected memory cell. Memory cell array 1
and a mutual circuit provided corresponding to each column of this memory cell array l, and connected to each memory cell of this corresponding column to supply an annotator to a memory cell in a selected state and to transmit data from this memory cell. A pair of first and second bit lines BL□, BL, ~BNN, BLN and a word line WLl- which is provided corresponding to each row of the memory cell array and selects each memory cell in the corresponding row. WLM
and each first and second bi.

G line BL1. Sense amplifiers 8Al-8AN are provided corresponding to BL, ~BLN, and BLN, which amplify the potential difference between the T lines, and sense amplifiers 8Al-8AN are provided corresponding to each row of the memory cell array l, and the sense amplifiers 8Al-8AN are provided corresponding to each row of the memory cell array l. Cell counter electrode line P connected to the counter electrode of the capacitor (CI) of each memory cell
For each row of Ll-PLM and memory cell array l, word lines (WLl to WLM); 6Q[level (Vcc)
The first and second bit lines (BLl, BL, ~BLN, BLN) are connected by the sense amplifier (SAI-8AN).
) At the first timing during the amplification operation of the potential difference between a predetermined potential, e.g. Vcc/2
to the first power supply potential Vss (=OV), and at the second timing, the word line (
WL1 to WLM) for a predetermined period from the selection level (Vcc) to a predetermined potential between the power supply potentials ■ss and ■cc, for example, Vc.
c/2 and returns the level of the cell counter electrode line (PL, to PLM) to a predetermined level (Vcc/2) between power supply potentials Vss and Vcc (hereinafter, VSS is referred to as ground potential); , and word line driver circuits WDl to WDM which set word lines WL to WLM to selection levels in response to external address signals.

Next, the operation of this embodiment will be explained.

FIG. 2 is an operational waveform diagram of each part signal for explaining the operation of this embodiment.

Bits 1BLl, E3I, 1-BL on reset cycle
N and BLN are, for example, the power supply potential VCC and the ground potential Vss.
(=OV) and is precharged to an intermediate potential Vcc/2.

In the active cycle, one word line, for example, WLK, is selected from among the word lines WL, -WLM by an externally applied address signal, and is raised to the power supply potential VCC. Memory cell MC connected to word line WLK
Since each transistor Q1 of K1 to MCKN is turned on, the capacitor C of each memory cell Mcx1 to MCKN is turned on.
Charges are exchanged between the bit lines BL□ to BLN, and the potential of each bit line BL, to BLN changes minutely.

Next, the sense amplifiers 8A1 to 8AN are activated, and the minute difference signal between them is amplified, so that, for example, the potential of the bit line BLL rises to the power supply potential VCCt, and the bit line BLL rises to the ground potential VCCt.
Descend to ss (=OV).

On the other hand, the nodes NK1 to NKN connected to the bit lines BLl to BLN via each transistor Q1 of the memory cells MCK and MCKN have the threshold voltage V of the transistor Ql.
- step drop, i.e. (Vcc-VT), or amplified to ground potential V8B.

Paired bit lines BL1. After amplification between BL□-BLN and BLN, Φ2 of the control signals Φ12-ΦM2 drops to the ground potential V88, and Φ1. of the control signals Φ13-Φ punishment.
By rising to the power supply potential VCC, the cell counter electrode line PLK of the selected memory cells MCK1 to MCKN falls from the intermediate potential Vcc/2 to the ground potential V8B. At this time, each node NKI of memory cells MCK1 to MCKN
~NKN drops for a moment due to the force caused by the drop of the cell counter electrode line PLK and the pulling noise, but returns to (Vcc -7) or the battery potential V8S.

When the row address strobe signal RA8 rises and a reset cycle begins, OKl of the control signals Φ11 to ΦM1
increases, and word 4IWLK, which has been selected and whose power supply potential ccK has been rising, falls to the intermediate potential Vcc/2 of voltage VPL. At this time, for example, if the node NKL of the memory cell MCKL is at a high level potential, that is, (vcc-vd), the transistor Ql of the memory cell MCKL is turned off. ; the node NKL is at a low level, that is, the ground potential Vss'
Transistor QI remains on.

Next, when the control signal Φ3 drops to the ground potential VSS and the control signal yoke 2 rises to the power supply potential ■cc, the cell counter electrode line P
LK rises to intermediate potential Vcc/2.

At this time, if the node NKL is at a high level, its level rises to (Vcc - Vcc/2), and if it is a low level, it momentarily rises from the ground potential VSS, but the transistor Ql is turned on. Therefore, it drops to the ground potential VSg again. The potential of node NKL is (VCCVT +VCC/2) or ground potential VS
After the control signal Φ becomes S, 1 drops to the ground potential ■ss, the word driver circuit WDK is reset, and if the word line WLK drops to the ground potential VSS, the memory cell MC
The write operation of K, ~MCKN is completed, and the write potential is finally on the high level side (V((-V7 + V((/
2) Ic becomes the ground potential VSS on the low level side. For example, when Vcc=5V and Vt=1sv, the high level side is about 6V, and data can be written at a potential higher than the power supply potential VCC.

〔Effect of the invention〕

As explained above, in the present invention, the power supply potential is changed from the intermediate level of the second power supply potential to the first power supply potential, and then the word line is changed from the selected level to the first and second power supply potentials. By providing a supply potential control circuit that returns the cell counter electrode line to an intermediate level while setting it to an intermediate level, the high level potential of the memory cell can be made higher than the power supply potential on the high potential side. This has the effect of improving the operating speed and resistance to unbalanced characteristics of the sense amplifier, and lengthening the data retention time.

[Brief explanation of the drawing]

1 and 2 are a circuit diagram showing an embodiment of the present invention and operation waveform diagrams of each current signal to explain the fabrication of this embodiment, and FIGS. 3 and 4 are respectively diagrams of conventional semiconductors. 2 is a circuit diagram showing an example of a memo IJ device and an operation waveform diagram of each current signal for explaining the operation of this example. FIG. 1... Memory cell array, 2... Supply potential control circuit, BL, BL, ~BLN, BLN...
...Bit line, CI-...Capacitor, MC11
~MCMN...--Memory cell array, PL1~P
LM...Cell counter electrode M, Q 1 e Q10 e
Qtz t Q13～QMI s QMz t QM
3...-transistor, 8A1~SAN...
...Sense amplifier, WD, ~WDM-...-Word line driver circuit, WL. ~WLM---word line. Agent: Susumu Uchihara, patent attorney

Claims (1)

[Claims] A memory cell array comprising a plurality of one-transistor, one-capacitor type memory cells arranged in a matrix in the row and column directions, and for writing and reading data to and from the memory cells in a selected state, and each of the memory cell arrays. A pair of first and second memory cells provided corresponding to a column and connected to each memory cell of the corresponding column to supply data to a memory cell in a selected state and transmit data from this memory cell. a second bit line, a word line provided corresponding to each row of the memory cell array and for setting each memory cell in the corresponding row in a selected state, and a word line provided corresponding to each of the first and second bit lines; a sense amplifier for amplifying the potential difference between the corresponding bit lines; a cell counter electrode line provided corresponding to each row of the memory cell array and connected to the counter electrode of the capacitor of each memory cell in the corresponding row; For each row of the memory cell array, the word line is set to a selection level and the first bit line is at a selection level during the amplification operation of the potential difference between the first and second bit lines by the sense amplifier.
The level of the cell counter electrode line is set to the first and second levels at the timing of
from a predetermined potential between power supply potentials to the first power supply potential, and at a second timing, set the word line from a selection level to a predetermined potential between the first and second power supply potentials for a predetermined period; A semiconductor memory device comprising: a supply potential control circuit that returns the level of the cell counter electrode line to a predetermined level between the first and second power supply potentials.