JPH0616353B2 - Dynamic RAM - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM (Random Accum Memory) and, for example, to a technique effectively used for a write circuit thereof.

[Background technology]

1-bit memory cell M in dynamic RAM
C is an information storage capacitor Cs and an address selection MOS
The information of logic "1" and "0" is stored in the form of whether the capacitor Cs has a charge or not.
To read information, the MOSFET Qm is turned on, the storage capacitor Cs is connected to the common data line DL, and it is sensed how the potential of the data line DL changes according to the amount of charge accumulated in the capacitor Cs. Done by.

The memory cell MC is formed small and the common data line D
Since many memory cells are connected to L to form a highly integrated and large capacity memory matrix, the capacitor Cs and
The relationship with the stray capacitance Co of the common data line DL is Cs / Co
The ratio of is very small. Therefore, the change in the potential of the data line DL due to the amount of charges accumulated in the capacitor Cs is a very small signal.

Therefore, before the sense amplifier is put into operation, it is necessary for the data input to put the buffer (write circuit) into non-operation. This is because when the data input buffer is activated, the potential of the common data line coupled to its output changes greatly. This level change of the common data line may cause an undesired level change in the data line DL due to capacitive coupling due to the parasitic capacitance of the column switch MOSFET, and a minute read signal from the memory cell may be destroyed. Because. Therefore, using the operation timing signal of the sense amplifier,
The input of the write control signal input before that is invalidated. Therefore, the dynamic RA
In the access of M, a certain restriction is set on the input timing of the write control signal supplied from the external terminal, which causes a difficulty in handling.

As for the dynamic RAM, there is, for example, Japanese Patent Laid-Open No. 57-82282.

[Object of the Invention]

An object of the present invention is to provide a dynamic RAM that is easy to handle.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM, a latch circuit for holding a write control signal for instructing writing to a dynamic memory cell after chip selection, and a first output signal of the latch circuit and a first synchronization with activation of a sense amplifier are provided. Timing control including a logic circuit for forming a second timing signal that defines the output timing of the write data from the data input buffer to the common complementary data line based on the timing signal after activation of the sense amplifier. Provide a circuit.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a dynamic RAM according to the present invention. Although not particularly limited, each circuit element or circuit block in the figure is formed on a single semiconductor substrate such as single crystal silicon by a well-known semiconductor integrated circuit manufacturing technique.

In the embodiment circuit shown in the figure, N-channel MOSFE is used.
IGFET (Insulated-Gate Field Eff) represented by T
ect Transistor) as an example.

The 1-bit memory cell MC has an information storage capacitor Cs and an address selection M as shown as a representative.
Information of logic "1" and "0" is stored in the form of whether the capacitor Cs has a charge or not. To read information, the MOSFET Qm is turned on, the capacitor Cs is connected to the common data line DL, and it is sensed how the potential of the data line DL changes according to the amount of charge accumulated in the capacitor Cs. Done by Since the memory cell MC is formed small and many memory cells are connected to the common data line DL to form a highly integrated and large capacity memory matrix, the capacitor Cs and the stray capacitance Co of the common data line DL (not shown). As for the relationship with (1), the ratio of Cs / Co has a very small value. Therefore, the change in the potential of the data line DL due to the amount of charges accumulated in the capacitor Cs is a very small signal.

A dummy cell DC is provided as a reference for detecting such a minute signal. This dummy cell DC is
Except that the capacitance value of the capacitor Cd is about half that of the capacitor Cs of the memory cell MC, the memory cell MC
It is made with the same manufacturing conditions and the same design constants. Prior to its addressing, the capacitor Cd is charged to the ground potential by the MOSFET Qd ′ receiving the timing signal φd. As described above, since the capacitance value of the capacitor Cd is set to about half the capacitance value of the capacitor Cs, the reference voltage equal to almost half of the read signal from the memory cell MC is formed.

In the figure, SA is a sense amplifier for expanding such a difference in potential change caused by the addressing into a sense period determined by a timing signal (sense amplifier control signal) φpa (the operation thereof will be described later). The input / output node is coupled to the complementary data lines DL, ▲ ▼ arranged in parallel. The number of memory cells coupled to the complementary data lines DL, ▲ is equal to increase the detection accuracy, and one dummy cell is coupled to each of DL and ▲. In addition, each memory cell MC is
They are connected at the intersection of one word line WL and one of the complementary pair data lines. Since each word line WL intersects both data line pairs, even if a noise component generated in the word line WL is on the data line due to electrostatic coupling, the noise component is generated in both data line pairs DL, ▲ ▼. , And are canceled by the differential sense amplifier SA.

In the above addressing, complementary data line pair DL, ▲
One of the pair of dummy word lines DWL, ▲ ▼ is selected so that when the memory cell MC coupled to one of the ▼ is selected, the dummy cell DC is always coupled to the other data line.

The sensor amplifier SA is a pair of cross-connected MOSs.
It has FETs Q1 and Q2, and by these positive feedback action,
The minute signals appearing on the complementary data lines DL, ▲ ▼ are differentially amplified. This positive feedback operation is based on the timing signal φpa
Is started at the same time when the MOSFET Q7 starts conducting, and the complementary data line DL,
Based on the potential difference given to ▼, the higher data line potential is slower and the lower data line potential is faster, and the difference spreads while the difference spreads. Thus, when the lower potential drops below the threshold voltage of the cross-coupled MOSFET, the positive feedback operation ends, and the lower potential drops due to the power supply voltage V.
The potential remains lower than cc and higher than the threshold voltage, and the lower potential finally reaches the ground potential (0V).

During the above addressing, the stored information of the memory cell MC which is about to be destroyed is recovered by directly receiving the high level or low level potential obtained by the sensing operation. However, as described above, if the high level drops to a certain level with respect to the power supply voltage Vcc, a malfunction occurs where the logic level is read as "0" while the reading and rewriting are repeated several times. The active store circuit AR is provided to prevent this malfunction. The active restore circuit AR has the function of selectively boosting the high level signal to the potential of the power supply voltage Vcc without affecting the low level signal. Since the specific circuit configuration of the active restore circuit AR is not directly related to the present invention, its detailed description is omitted.

A data line pair DL, which is shown as a representative in FIG.
▲ ▼ is a MOSFE that constitutes the column switch CW
Common complementary data line pair CDL, TQ3, Q4
Connected to ▼. The data line pair shown as another representative is also connected to the common complementary data line pair CDL, ▲ ▼ through similar MOSFETs Q5 and Q6. The common complementary data line pair CDL, ▲ ▼ is connected to the input terminal of the data output buffer DOB including the output amplifier and the output terminal of the data input buffer DIB.

The row decoder and column decoders R and C-DCR receive the internal complementary address signal formed by the address buffer ADB, form one word line and dummy word line, and form a column switch selection signal, thereby forming a memory cell and a dummy cell. Perform addressing. That is, the external address signals X0 to AXi are fetched into the address buffer R-ADB in synchronization with the timing signal .phi.ar generated by the row address strobe signal (), and the row decoder R
-During the transmission to the DCR, a predetermined word line and a dummy word line are selected according to the output of the address decoder by the word line selection timing signal φx.

Further, the external address signals AY0 to AYi are taken into the address buffer C-ADB in synchronization with the timing signal φac generated by the column address strobe signal ▲ ▼, transmitted to the column decoder C-DCR, and the data line selection timing signal φy is used. Performs data line selection operation.

The timing control circuit TC has a row address strobe signal ▲ ▼, a column address strobe signal ▲ ▼ and a write enable signal ▲ supplied from an external terminal.
In response to ▼, in addition to the timing signals exemplarily shown as the above-mentioned representative, various other timing signals necessary for the memory operation are formed.

FIG. 2 shows a circuit diagram of an embodiment of the operation timing signal generator of the data input buffer included in the timing control circuit TC.

Write enable signal supplied from the external terminal ▲ ▼
Although not particularly limited, the row address strobe signal ▲ ▼ is supplied to the input of the NOR gate circuit G1. The output of the NOR gate circuit G1 is supplied to the input of the inverter circuit IV2. The output N1 of the inverter circuit IV2 is input to the next latch circuit on the one hand. That is, the NAND gate circuits G2 and G3 are
A latch circuit is formed by cross-connecting between one input and one output. The output N1 of the inverter circuit IV2 is supplied to the other input of the NAND gate circuit G2. Although not particularly limited, the other input of the NAND gate circuit G3 is supplied with the timing signal ▲ ▼ a formed by inverting and delaying the operation timing signal φpa of the sense amplifier SA as a clock signal.

The output N1 of the inverter circuit IV2 and the output N2 of the NAND gate circuit G3 forming the latch circuit are supplied to the input of the NAND gate circuit G4. The output N3 of the NAND gate circuit G4 is supplied to one input of the NAND gate circuit G5. The operation timing signal φ of the sense amplifier SA is applied to the other input of the NAND gate circuit G5.
pa is supplied, and from the output of the NAND gate circuit G5,
Data input buffer DI via inverter circuit IV3
The B operation timing signal φrw is formed. Here, the operation timing signal φpa which is the other input of the NAND gate circuit G5 is an example of the first timing signal which is synchronized with the activation of the sense amplifier SA, and the operation which is output from the inverter circuit IV3. Timing signal φ
The second rw defines the output timing of the write data from the data input buffer DIB to the common complementary data line CDL, ▲ ▼ after the activation of the sense amplifier SA.
Is used as an example of the timing signal. Further, the combination circuit of the NAND gate circuits G4 and G5 and the inverter circuit IV3 is an example of a logic circuit for forming the second timing signal.

Next, the operation of the embodiment circuit shown in FIG. 2 will be described with reference to the timing chart shown in FIG.

The operation timing signal φpa of the sense amplifier is changed from the high level to the low level during the chip non-selection period in which the row address strobe signal ▲ ▼ is set to the high level. The timing signal pa formed by inverting and delaying the timing signal φpa is changed from the low level to the high level with a delay. Further, if the previous operation cycle is a read operation, the output N2 of the latch circuit holds the high level state, and therefore the output N3 of the NAND gate circuit G4 is at the low level according to the high level of the write enable signal ▲ ▼. Therefore, in the previous read cycle, the timing signal φrw remains low level.

The chip is brought into the selected state by the low level of the row address strobe signal (), and the row address signal is fetched in synchronization with this (not shown). At this time, if the write enable signal ▲ ▼ is set to low level,
The output N1 of the inverter circuit IV2 is set to low level. The low level of the output N2 and the timing signal
The output N2 of the latch circuit changes from the high level to the low level depending on the high level of pa. That is, the latch circuit takes in the write enable signal ▲ ▼ and holds it. Output N1 of the inverter circuit IV2
Output of the NAND gate circuit G4 is set to the high level.

As a result, the operation timing signal φ of the sense amplifier SA
When pa is at the low level, in other words, the timing signal φrw is set to the low level before the operation is started, whereby the operation of the data input buffer DIB is prohibited. The sense amplifier SA starts its operation by the high level of the timing signal φpa. Due to the high level of the timing signal φpa, the write control signal φrw output through the NAND gate circuit G5 and the inverter circuit IV3 is set to the high level with a slight delay, and activates the data input buffer DIB.

At this time, the write enable signal ▲ ▼ may be in a high level state as shown by the solid line in FIG. This is because even if the output N1 of the inverter circuit IV2 returns to the high level due to the high level of the write table signal {circle around (1)}, the latch circuit holds the output N2 at the low level. When the write enable signal ▲ ▼ is returned to the high level at such an early timing, the output N2 of the latch circuit is changed due to the low level of the timing signal pa formed by inverting and delaying the operation timing signal φpa of the sense amplifier SA. High level. Due to the high level of the output N2 and the high level of the output N1 which has already been set to the high level, the output of the NAND gate circuit G4 becomes the low level, the timing signal φrw is set to the low level, and the write operation is completed. Therefore, the pulse width of the write pulse φrw in this case is set by the time difference between the timing signal φpa and its inverted delay timing signal pa, that is, the delay time.

As indicated by the broken line in the figure, when the write enable signal ▲ ▼ is delayed in returning to the high level, the output N1 of the inverter circuit IV2 is synchronized with the rising edge of the write enable signal ▲ ▼. Since it is set to the high level, the write pulse φrw is set to the low level. That is, the rising edge of the write pulse φrw is the operation timing signal φ of the sense amplifier SA.
It is defined by pa and the fall is defined by the write enable signal ▲ ▼.

[Effect]

(1) By holding the write instruction by the write enable signal in the chip selected state in the latch circuit, it is possible to perform the write operation without being restricted by the complicated timing constraint for the write operation.

(2) Since the write pulse width can be specified by the signal held in the latch circuit and the timing signal formed internally, the external control signal should be given a certain time margin in consideration of the variation in the operation timing of the internal circuit. There is an effect that it is not necessary to supply the power, and a reliable write operation can be performed at the optimum timing.

Although the invention made by the present inventor has been described with reference to specific examples based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, as the chip selection signal, the column address strobe signal ▲ ▼
May be used. Further, in a dynamic RAM that supplies a row address signal and a column address signal from independent external terminals, a chip selection signal ▲ ▼ or ▲ ▼ is provided, so that this is used instead of the address strobe signal. Is. Furthermore, ▲ ▼, ▲ ▼, ▲ ▼, ▲ ▼
It may be a signal after level conversion processing for matching the external input level such as with the power supply voltage level of the RAM.

As described above, the chip selection signal may have any name as long as it substantially puts the RAM in the selected state. The timing signal used as the clock signal of the latch circuit may be any operation timing signal of the sense amplifier SA, as long as it performs the timing control as described above, for example, the column address strobe signal ▲ ▼. It is possible to use a signal to be synchronized or a signal whose level has been converted in order to match the external input level of ▲ ▼ with the power supply voltage level of the RAM. Further, the specific circuit configuration of the latch circuit can adopt various embodiments.

The reference voltage for reading the memory cell that constitutes the dynamic RAM uses not only a dummy cell but also an intermediate level formed by short-circuiting the high-level and low-level complementary data lines in a high impedance state. And so on. Further, peripheral circuits such as an address buffer, an address decoder and the like are constituted by a CMOS static type circuit, and further, as described above, the X address signal and the Y address signal are supplied from independent external terminals, respectively, and the change of the address signal. A timing detection circuit is provided and various timing signals necessary for the operation of the internal circuit are generated by the detection output. Various embodiments such as an internal synchronous dynamic RAM can be adopted. Also, various refresh circuits may be incorporated.

[Field of application]

The present invention can be widely used for dynamic RAM.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of a timing control circuit for forming the write pulse, and FIG. 3 is for explaining its operation. FIG. MC ... Memory cell, DC ... Dummy cell, CW ... Column switch, SA ... Sense amplifier, AR ... Active restore circuit, R, C-DCR ... Row / column decoder, ADB ... Address buffer, DOB ... … Data signal buffer, DIB …… Data input buffer, TC
... Timing control circuit, G1 ... NOR gate circuit, G
2-G5: NAND gate circuit, IV2-IV3: Inverter circuit

Claims (2)

[Claims] 1. A plurality of dynamic memory cells for storing data, a sense amplifier for detecting and amplifying a signal read to a complementary data line in a selected state,
A dynamic RAM including a common complementary data line to which the complementary data line is commonly connected via a column switch, and a data input buffer for supplying write data from the outside to the common complementary data line. Based on a latch circuit for holding a write control signal for instructing writing to a memory cell after chip selection and an output signal of the latch circuit and a first timing signal synchronized with activation of the sense amplifier, And a logic circuit for forming a second timing signal for defining the output timing of the write data from the data input buffer to the common complementary data line after activation of the sense amplifier, and a timing control circuit including: A dynamic RAM, characterized by comprising: 2. The logic circuit causes the data input buffer to output write data in response to a second timing signal, and then outputs the write control signal in accordance with whether the end timing of the write control signal is early or late. 2. The dynamic RAM according to claim 1, wherein the pulse width of the second timing signal is controlled in order to change the output end timing of the write data from the memory.