JPS6196592A - Dynamic type ram - Google Patents

Abstract

PURPOSE:To write at a high speed by stopping selectively a data line precharging circuit when a refreshing action is executed. CONSTITUTION:While a column address strobe signal inversion CAS is L, a low address strobe signal inversion RAS is set to H temporarily, and then, a refreshing mode condition is obtained. In this condition, when FF of a data line DL and inversion DL selected through column data is reset, a Q output of FF is inverted to L and transistor Q3, etc., of the precharging circuit are turned off. Thus, a precharging pulse phiPC is not supplied, a precharging circuit of the selected bit line DL and inversion DL stops operation, the bit line DL and inversion DL are not precharged, and the writing to the memory cell connected to the bit line AL inversion DL by a parasitic capacity in accordance with the writing signal which is remaining at these lines are executed at a high speed.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a dynamic RAM (random access memory), and 1/1E is a technique that is effective when used in a dynamic RAM with multiple addresses. It is related to.

[Background technology]

For example, a high-speed write (read) method called page mode is known as an operating function of dynamic RAM (for example,
(See Hitachi IC Memory Data Book 1, pages 291 to 320).

However, in the page mode described above, the row address is fixed and the column address signal is sequentially switched to perform 1-bit (7) H reading, so the selection operation of the memory cell in the hole is However, it takes a long time in the rear operation, as it requires writing to all memory cells.

The inventor of the present application has proposed that in a dynamic RAM, a memory cell uses a capacitor whose capacitance is set to a very small value with respect to the parasitic capacitance of the data line to which it is connected, and the memory cell has a logic value depending on the presence or absence of charge accumulated in the capacitor. Focusing on holding storage information of "1" and logic "O", we considered performing high-speed writing.

[Purpose of the invention]

An object of the present invention is to provide a dynamic RAM that realizes a high-speed write operation of the same information.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by stopping precharging of the data line during a refresh operation using a signal supplied from an external terminal, the level of the data line is written into the memory cell as is.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a dynamic RAM according to the present invention. Each circuit element in the same figure is
It is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using known semiconductor integrated circuit manufacturing techniques.

In the example circuit shown in the figure, an N-channel MOSFE
I G F E T (I n5ula
tedGate Field Effect Trans
istor) will be explained as an example.

A 1-bit memory cell MC, as shown as a representative, has an address selection MOS FETQm and two electrodes, one electrode of which is coupled to Qm, and the other electrode maintained at the circuit power supply voltage level. Information storage capacitor C
Consisting of s and logic "1".

Information of "0" is stored in correspondence with whether the capacitor Cs has a charge or not.

To read information, turn on MOSFETQm, connect capacitor Cs to common data line DL, and sense how the potential of data line DL changes depending on the amount of charge accumulated in capacitor Cs. carried out by.

Although not particularly limited, a dummy cell DC is provided as a reference for detecting such a minute signal.

This dummy cell DC is manufactured under the same manufacturing conditions and the same design constants as the memory cell MC, except that the capacitance value of the capacitor Cd is approximately half that of the capacitor Cs of the memory cell MC. The capacitor Cd receives a timing signal φd generated prior to addressing, and is connected to a MOSFE placed between the capacitor Cd and the ground point of the circuit.
It is charged to the power supply voltage by TQd'.

As mentioned above, capacitor Cd is set to approximately half the capacitance value of capacitor C5, so memory cell MC
This will form a reference voltage approximately equal to half of the read signal from the .

In the same figure, SA is a sense amplifier that expands the difference in potential change caused by the above-mentioned addressing into a sensing period determined by a timing signal (sense amplifier control signal) Its input and output nodes are coupled to lines DL and DL. This sense amplifier SA consists of a pair of cross-wired MOS
FETQ 1.

Q2, and the positive feedback action of these differentially amplifies minute signals appearing on the complementary data lines DL, DL.

The numbers of memory cells coupled to the complementary data lines DL, DL are made equal to increase the detection efficiency, and one dummy cell is coupled to each of the complementary data lines DL, DL. Furthermore, each memory cell MC is coupled between one word line WL and one of the complementary pair data lines. Since each word line WL crosses both data line pairs, even if a noise component generated on the word line WL is transferred to the data line due to capacitive coupling, the noise component will be transmitted to both data line pairs DL, DL. They appear equally and are canceled by the differential sense amplifier SA.

In the above addressing, complementary data line pair DL, D
When a memory cell MC coupled to one of the data lines L is selected, one of the pair of dummy word lines DWL, DWL is selected so that the dummy cell DC is always coupled to the other data line.

During the above-mentioned addressing, the stored information in the memory cell MC, which is about to be destroyed, is recovered by directly receiving the high-level or low-level potential that has been violated by this sensing operation. However, as described above, when the high level drops by a certain level or more with respect to the power supply voltage Vcc, a malfunction occurs in which the data is read as a logic "0" while reading and rewriting are repeated several times. An actuator/event restore circuit AR is provided to prevent this malfunction. This active restore circuit AR selectively boosts only the high level signal to the potential of the power supply voltage Vcc without affecting the low level signal in any way using the timing signal φrs.
There is a function to do that.

A data line pair DL, which is shown as a representative in the figure,
DL is MOSFETQ that constitutes the column switch CW
3. Common complementary data line pair CDL, CDL via Q4
connected to. Similar MOSFET Q5. It is connected to the common complementary data line pair CDL, CDL via Q6. This common complementary data line pair CDL, CDL is connected to one terminal of an input/output circuit I10 consisting of a data output cover sofa and a data input cover sofa including a main amplifier and an output circuit, as will be described later.

The row decoder and column decoder R, C-DCR have a row address buffer and a column address buffer R, C.
-Receives the internal complementary address signal formed by ADB,
Addressing of memory cells and dummy cells is performed by forming one word line, a dummy word line, and a column switch selection signal. That is, in synchronization with the timing signal φar generated by the row address strobe signal RAS, the row address buffer R-ADH takes in address signals AXO to AXi supplied through external terminals, holds them, and outputs them to the row decoder R-DCH. tell to. The row decoder R-DCR8 decodes the transmitted address signal and performs a predetermined word line and dummy word line selection operation based on the word line selection timing signal φX.゛-Meanwhile, column address buffer 1C-AD
H is constituted by a static type circuit that is activated by a timing signal φac generated by a column address strobe signal CAS. As a result, the address signals AYO~, AYi supplied through the external terminals
A column decoder C-D, which is also configured by a static type circuit, forms an internal complementary address signal according to the following.
Tell CR. The column decoder C-DCR decodes the transmitted address signal and performs a data line selection operation in accordance with the ζ data 1Iit selection timing signal φy.

The timing control circuit 'rC receives a row address strobe signal RAs supplied through an external terminal.

In response to the column address strobe signal CAS and write enable signal WE, the various internal timing signals described above are generated.

In this embodiment, the following circuits are added in order to realize a high-speed write operation of the same storage information to the memory cell. That is, complementary data line D L .

The precharge circuit PC provided in the DL is a control circuit formed based on a control signal supplied from an external terminal.
In response to the signal S and the output signal of the column address decoder C-DCH, the precharge operation performed by the precharge pulse φpc is selectively stopped.

FIG. 2 shows a circuit diagram of a specific embodiment of the precharge circuit PC.

Complementary data lines DL, DL are MO3FE, TQIO, Q
Precharging is performed each time the power supply voltage terminal Vcc is supplied by ll.

In addition, the complementary data lines DL, DL are connected to the precharge MOSFET Q i O, Q 11,
In order to equalize the precharge levels of the complementary data lines DL and DL, an MO connecting the complementary data lines DL and DL is used.
SFETQ12 is provided.

The above-mentioned similar M
O5I''ETQ15 to Q17 are provided.

In the figure, only the precharging MOSFETs provided for the two pairs of complementary data lines DL and DL are given the above circuit symbols.

These precharge λ10sFETQ10~Q12
The gates of (Q15 to Q17) are shared, and a precharge pulse ψpc is selectively supplied by the next control circuit. That is, each set S of latch circuits FF provided for each complementary data line has a row address strobe signal RAS supplied from an external terminal, a column address strobe signal C, A S, and a row address strobe signal RAS supplied from an external terminal. A control signal S formed by an AND (A N D) gate circuit receiving the signals is commonly supplied. Furthermore, the output signal of the column address decoder C-DCR is supplied to the reset terminal R of each of the latch circuits FF. The output Q of each of the latch circuits FF is connected to a cut MOSFET Q14. Transmission gate MOSFET Q1 shown as representative via Q19 etc.
3. This will be communicated to the gate of Q18. These transmission gate MOSFETQ13. Q18 etc. respectively connect the above precharge pulse φpc to the above precharge MOSFET.
Q10-Q12. This is to be transmitted to the gates of Q15 to Q17.

An example of the operation of this embodiment circuit will be explained with reference to the timing diagram shown in FIG.

First, writing to a plurality of complementary data lines is performed using the above-mentioned well-known page mode.

Lower (sets the narrow stroke signal RAS to low level and sends the row address signal x1 to the row address decoder R-
Import and save in ADB. As a result, row address decoder R-DCR performs a selection operation for one word line. Next, the column address strobe signal CAS is set to low level, and the address signal Y1 supplied from the same terminal is transferred to the column address buffer C-/1. One column switch is selected from the column address decoder C-DCR. And, although not shown,
When the write enable signal WE is at a low level, a write signal DI is supplied from an external terminal to perform writing to one memory cell. Thereafter, the row address strobe signal RAS is kept at a low level, and in synchronization with the column address strobe signal CAS', the address signal Y2. Y
3... and the respective address signals Y2. A write operation is performed to the memory cell selected by Y3.

In the above operation, all of the precharge circuits
The child circuit FF receives the address strobe signals R, A S
and CAS are both set at a high level (logical ff'l'') during a non-selection period.Then, those selected by the column address decoder C-DCH are sequentially reset. Latch circuit F
Since the transmission gate MOSFET Q13 and the like transmitting the precharge pulse φpc are turned off by the low level of the output Q of F, the precharging operation of the selected complementary data lines DL and DL is thereafter stopped. As a result, the complementary data lines DL, DL are connected to the write signals DI, D2 . D3 etc. are held.

Next 1. Column address strobe signal CAS is set to low 1
．．・Bell's surrender remains ζ, Russiado 1/Susu draw 7'! Temporarily set % RA S to high level °ζ, C
This refresh mode, in which the refresh mode is shifted to the AS BIF f-1-RA S refresh mode, is well known from the above-mentioned ``Hitachi IC Memory Data Book'', so a detailed explanation thereof will be omitted. Even in this refresh L mode, the precharge operation of the complementary data line of the selected column address remains stopped, and the precharge operation continues according to the write cIJ signal.
He is left holding the bell. Therefore, the word coupled to these complementary data lines (the complementary data lines corresponding to the latch circuits set above) and selected by the row address signal X 2 + X 3 etc. resulting from the above refresh operation. The memory cells of the lines are written with the levels remaining on their respective complementary data lines. Note that since the complementary data line corresponding to the latch circuit placed in the sent state is subjected to a precharge operation, the memory cells coupled thereto are refreshed.

Note that in the write/read operation for each hint (2), both address strobe signals RAS and CAS are once set to high level. As a result, the latch circuit FF is always kept in the cent state, so that a precharge operation is performed on each of the complementary data lines DL, i)L. As a result, it is possible to write/read bits one by one as in the conventional case. Also, CA
When S-before RAS refresh is performed, the latch circuit iFF is not reset tc' because the column selection operation is not performed unless the preceding page mode write is performed. Thereby, a refresh operation similar to the conventional one can be performed.

Further, when the precharge level to the complementary data lines DL and DL is set to the power supply voltage Vcc, the precharge pulse φpc is boosted to a high level by the bootstrap circuit. In the embodiment shown in FIG. 2, if the output of the latch circuit FF is at a high level, in other words, if the complementary data line is to be precharged, the transmission gate M is
The OS F' E TQ 13 and the like are turned on before the arrival of the precharge pulse φpc. Therefore, when the precharge pulse ψpc is set to high level, its gate.

The gate voltage is boosted by self-foot-strap due to the MO3 capacitance between the channels. by this,
Since the precharge pulse φpc:Z is transmitted to the gates of the precharge MOS FE'I'Q10 to Q12 without any level loss, the Vcc precharge described above can be realized. Above cut M OS F E
T Q 14 is the above 'rA OS F E T Q
The cell knob strap 1 pressure at 13 is for preventing latch circuit failure.

〔effect〕

(11) By selectively stopping the precharge operation of the complementary data lines, simultaneous writing to all memory cells coupled to the word line can be performed using the level Lm of the parasitic capacitance of the complementary data lines. This allows the same signal to be written at high speed.

(2) By selectively stopping the precharge operation for each complementary data line, it is possible to realize high-speed writing of the same signal to memory cells in any area.

(3) By using the address strozo signal and the output of the column address decoder as a signal to selectively stop the brinayage operation for each complementary data line, "ζ, fl Ii'!I i can be added very easily. By simply doing this, it is possible to realize high-speed writing to memory cells in a certain area using page mode and CAS before RAS resetting.

Above, the invention made by the inventor has been specifically explained based on the examples, but it should be noted that this invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist of the invention. Not even. For example, the precharge operation may be selectively stopped by an appropriate external control signal. In this case, high-speed writing can be performed by word line selection for all memory cells in the data line direction. Also, the above column -? The circuit that selectively stops the precharging of the complementary data lines based on the output of the address decoder can be modified in various ways. For example, one that sets the precharge level of the complementary data line to Vcc-Vth (7);
Alternatively, in the case of half pre-nage (Vcc/2), the precharge pulse can be selectively supplied to the precharge MOSFET via an AND gate circuit.

Furthermore, the X-system and Y-system address signals may be supplied from external terminals, respectively.

[Application field]

This invention can be widely used in dynamic RAM.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a dynamic RAM according to the present invention, - FIG. 2 is a circuit diagram showing an embodiment of the precharge circuit, and FIG. 3 is a circuit diagram showing an embodiment of the precharge circuit. FIG. 3 is a timing chart showing an example. MARY...Memory array, MC...Memory cell, DC
・・Dummy cell, CW・・Column switch, SA・・Sense amplifier, AR・・Active restore circuit, R, C
-DCR・Row/column decoder, R, C-ADB・
・Row/column address buffer, DOB...Data output buffer, DIB...Data driver cover, TC...
Timing control circuit, PC...precharge circuit, FF
...Latch circuit diagram 1 ^YO~^Yl

Claims (1)

Claims: 1. A dynamic RAM comprising a data line precharge circuit whose operation is selectively stopped during a refresh operation by a signal supplied from an external terminal. 2. The precharge circuit includes a latch circuit in which the AND output of the row address strobe signal and the column address strobe signal is supplied to the set terminal, and the output of the column address decoder is supplied to the reset terminal, and the output of this latch circuit. 2. The dynamic RAM according to claim 1, further comprising a gate circuit that selectively transmits a precharge pulse to a precharge MOSFET according to a signal. 3. The gate circuit is a transmission gate MOSFET whose gate is supplied with the output of the latch circuit via a cut MOSFET and which transmits the precharge pulse to the gate of the precharge MOSFET. Dynamic RAM according to item 2.