JPS5760588A - Memory controller - Google Patents

Memory controller

Info

Publication number
JPS5760588A
JPS5760588A JP55134079A JP13407980A JPS5760588A JP S5760588 A JPS5760588 A JP S5760588A JP 55134079 A JP55134079 A JP 55134079A JP 13407980 A JP13407980 A JP 13407980A JP S5760588 A JPS5760588 A JP S5760588A
Authority
JP
Japan
Prior art keywords
refresh
memory
memstart
delay
sent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55134079A
Other languages
Japanese (ja)
Inventor
Kazuyuki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55134079A priority Critical patent/JPS5760588A/en
Publication of JPS5760588A publication Critical patent/JPS5760588A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To prevent the delay of memory cycle and at the same time to realize a long-time initialize from outside, by subjecting a refresh control circuit to a DMA function and also synchronizing the external clear signal. CONSTITUTION:An access is given to a memory 22 according to the MEMSTART sent from a CPU21 based on the DMAREQ sent from a DMA device 23. At the same time, a control part A24 that forms a refresh control circuit is also started. The DMA device 23 according to a refresh clock is subjected to an apparent functional operation via a refresh counter of the part A24, therefore the memory 22 is refreshed by the REFMODE without competing against the MEMSTART. Accordingly, a racing circuit can be eliminated to prevent the delay of the memory cycle. On the other hand, the external CLEAR signal is synchronized with the refresh clock through a control part B25 to clear the CPU21. Thus the refresh is carried out writhout fail.
JP55134079A 1980-09-26 1980-09-26 Memory controller Pending JPS5760588A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55134079A JPS5760588A (en) 1980-09-26 1980-09-26 Memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55134079A JPS5760588A (en) 1980-09-26 1980-09-26 Memory controller

Publications (1)

Publication Number Publication Date
JPS5760588A true JPS5760588A (en) 1982-04-12

Family

ID=15119902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55134079A Pending JPS5760588A (en) 1980-09-26 1980-09-26 Memory controller

Country Status (1)

Country Link
JP (1) JPS5760588A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182598A (en) * 1984-02-27 1985-09-18 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Memory refresh system
US5694619A (en) * 1993-09-20 1997-12-02 Fujitsu Limited System for exclusively controlling access of a semiconductor memory module using a backup memory and compression and decompression techniques

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182598A (en) * 1984-02-27 1985-09-18 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Memory refresh system
US5694619A (en) * 1993-09-20 1997-12-02 Fujitsu Limited System for exclusively controlling access of a semiconductor memory module using a backup memory and compression and decompression techniques
US5925111A (en) * 1993-09-20 1999-07-20 Fujitsu, Limited System for alotting logical path number to logical interfaces and permitting logical interface to access selected I/O using logical path number when selected I/O is not in use
US6338101B1 (en) 1993-09-20 2002-01-08 Fujitsu Limited Memory initialization method for volatile memory

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