JPH0267613A - Clock signal generating circuit - Google Patents

Abstract

PURPOSE:To attain the control of clock generation in each clock cycle in all operation timing without synchronizing operation by a device to which a clock is supplied by changing the frequency of a clock signal by an external synchronizing signal and supplying the frequency-changed clock signal to a microprocessor or the like. CONSTITUTION:An oscillation circuit 1 forms a pulse signal having the resonance frequency of a crystal oscillator 4 connected to the external. When the signal is outputted as an auxiliary clock signal CL1 from an auxiliary clock signal output terminal 7 to the external, the frequency of the signal is divided into 1/2 frequency by a frequency dividing circuit 2 and supplied as a clock signal CL2 from a clock signal output terminal 6 to a microprocessor or the like. On the other hand, a synchronizing signal SY inputted from a synchronizing signal input terminal 8 to the circuit 2 through a synchronizing circuit 3. Namely, the frequency dividing operation of the circuit 2 is stopped to reduce the frequency of the signal CL2 during the high level of the signal SY. Thereby, the microprocessor or the like can omit a function for executing synchronization.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock signal generation circuit, and more particularly to a clock signal generation circuit configured as a digital integrated circuit.

[Conventional technology]

In a conventional microcomputer system, when a microprocessor reads or writes data to a memory or peripheral circuit, the operation timing of the microprocessor is as shown in Figure 3. A common method for synchronizing with a circuit is to input a synchronization signal to the microprocessor and extend the address and control signals output by the microprocessor while the synchronization signal is inactive. there were.

In FIG. 3, T1 to T3 (-T for boat fishing) are internal states of the microprocessor. For example, a synchronization signal is detected in the T2 state, and if the synchronization signal is at a high level, the T2 state is repeated. If the level is low, proceed to the T3 state.

[Problem to be solved by the invention]

In the conventional clock signal generation circuit described above, data read or write operations can be synchronized between the microprocessor and the memory or peripheral circuits only by extending the active period of the read control signal or write control signal. Therefore, due to the influence of other characteristics of the memory and peripheral circuits (for example, the setting time of the address signal for successive control signals, the interval time between the end of a write operation and the start of the next write operation, etc.), the speed may be faster than necessary. The disadvantage is that it requires the use of memory and peripheral circuits.

[Means to solve the problem]

The clock signal generation circuit of the present invention includes a crystal oscillation circuit that outputs an auxiliary clock signal of a predetermined period, a frequency dividing circuit that divides the auxiliary clock signal at a predetermined frequency division ratio and outputs a clock signal, and an external and a synchronization circuit that varies the frequency of the clock signal based on a synchronization signal input from the clock signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

As shown in FIG. 1, an oscillation circuit 1 generates a pulse signal having the resonance frequency of an externally connected crystal oscillator 4.

The generated pulse signal is outputted to the outside from the auxiliary clock signal output terminal 7 as the auxiliary clock signal CL, and the frequency is divided by 1/2 by the frequency dividing circuit 2, and the clock signal output terminal 6 is also output as the clock signal CL2. The signal is supplied to the microprocessor, etc.

Further, the synchronization signal SY input from the synchronization signal input terminal 8 passes through the synchronization circuit 3 and controls the frequency dividing circuit 2. That is, while the synchronizing signal SY is at a high level, the frequency dividing operation of the frequency dividing circuit 2 is stopped and the frequency of the clock signal CL2 is lowered.

FIG. 2 is a waveform diagram for explaining the embodiment of FIG. 1 and the operation of a microprocessor using the embodiment.

In FIG. 2, T1 to T3 are internal states of an external microprocessor, and address signals, data signals, and write control signals are examples of microprocessor signals.

As shown in FIG. 2, the synchronization signal SY is input so that the times of the T1 state and the T2 state are longer.

〔Effect of the invention〕

As explained above, the present invention changes the frequency of a clock signal using a synchronization signal input from the outside and supplies it to a microprocessor, etc., thereby eliminating the need to provide a function for synchronizing operations in the microprocessor, etc. Furthermore, there is an effect that the operation timing of a microprocessor etc. can be controlled every clock cycle.

...Clock signal, SY...Synchronization signal.

Claims (1)

[Claims] a crystal oscillator circuit that outputs an auxiliary clock signal with a predetermined cycle; a frequency divider circuit that divides the auxiliary clock signal at a predetermined frequency division ratio and outputs a clock signal; A clock signal generation circuit comprising: a synchronization circuit that varies the frequency of a signal.