JP2789755B2 - Synchronous semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous semiconductor memory device, and more particularly, to a synchronous semiconductor memory device having an internal circuit for performing a data processing operation in accordance with a clock pulse level, and controlling a current supply to the internal circuit. And a low power consumption synchronous semiconductor memory device.

[Conventional technology]

Conventionally, this type of synchronous semiconductor memory device performs a data processing operation only when a chip select signal CS is at an active level (low level) and a clock pulse CK is at a high level, as shown in FIG. 5 as an example. An input circuit 1 for transmitting a chip select signal CS to an output terminal in synchronization with a clock pulse CK and outputting the same as a chip select signal CSS, and a chip select signal CSS from the input circuit 1.
And the current control circuit 3 that controls the internal circuit 4 to be activated when the active level is at a low level and to supply a current to the internal circuit 4.

FIG. 6 is a timing chart of signals at various parts for explaining the operation of this example.

As can be seen from FIG. 6, the internal circuit 4 is activated when the chip select signal CSS is at a low level, and the current I is supplied to the internal circuit 4 from the current source circuit. When the chip select signal CSS goes into a high-level standby state, the chip select signal CSS goes into an inactive state, and the supply of the current I to the internal circuit 4 is stopped.

Therefore, power is not consumed in the standby state, so that power consumption can be reduced.

[Problems to be solved by the invention]

The conventional synchronous semiconductor memory device described above has a configuration in which the supply of the current I to the internal circuit 4 is stopped when the chip select signal CSS is in a standby state at a high level to reduce power consumption. As shown in FIG. 7, the circuit 4 performs the data processing operation only when the clock pulse CK is at a high level, and does not perform the data processing operation when the clock pulse CK is at a low level. There is a disadvantage that current flows through the internal circuit 4 even during the level period and wasteful power is consumed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronous semiconductor memory device capable of eliminating waste of power consumption and further reducing power consumption.

[Means for solving the problem]

A synchronous semiconductor memory device according to the present invention includes an input circuit that outputs a chip select signal in synchronization with a clock pulse signal, wherein the chip select signal is at an active level and the clock pulse signal is one of a first signal and a second signal. An internal circuit that performs a data processing operation only at one of the active levels, the clock pulse signal and a delayed pulse signal obtained by delaying the phase of the clock pulse signal, and the start of the active level of the clock pulse is advanced. An adjustment circuit that outputs an adjustment signal that delays the termination of the active level; a logic circuit that outputs an active level control signal when the chip select signal and the adjustment signal are at the active level; And a current control circuit that controls so that current is supplied to the internal circuit only when

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment is different from the conventional synchronous semiconductor memory device shown in FIG. 5 in that the chip select signal CSS from the input circuit 1 is at a low active level and the clock pulse CK is A logic circuit 2 that outputs a control signal CNT that is at an active low level only when the control signal CNT is at an active level when the data processing operation is performed at a high level. 4 is controlled so that the current I is supplied.

 Next, the operation of this embodiment will be described.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of this embodiment.

A period during which the clock pulse CK is at a high level is a data processing operation period T _A of the internal circuit 4, and a period during which the clock pulse CK is at a low level is a data non-processing period T _NA .

Therefore, in the logic circuit 2, the chip select signal
The control signal CNT is set to the low active level only when the CSS is at the low level and the clock pulse CK is at the high level, and the current I is supplied to the internal circuit 4 only during this period.

In the conventional example shown in FIG. 5, the current I is supplied to the internal circuit 4 even during the data non-processing period _TNA of the internal circuit 4 in which the clock pulse CK is at a low level. Since no current I is consumed in the _TNA , the power consumption is reduced to T _A / (T _A + T _NA ) compared to the conventional example.

 FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, when the internal circuit 4 has a part that the data processing operation must be performed simultaneously with the rising of the clock pulse CK, the control signal CNT is set to the active level simultaneously with the rising of the clock pulse CK. Since the supply of the current I to the circuit 4 may be delayed and malfunction, the adjustment circuit is set so that the start point of the active level period of the control signal CNT is a predetermined period (T _PA ) before the rise of the clock pulse CK. 5 is provided.

FIG. 4 is a timing chart of signals of respective parts for explaining the operation of this embodiment.

The adjusting circuit 5 controls the clock pulse CK by the delay element DI1.
Is delayed by the time T _D and inverted (CKD1), and the OR gate G1 causes the rise of the clock pulse CK to cause the time T _DA
Occurs only a rising time is fast clock pulse CKD2, by supplying the clock pulse CKD2 the logic circuit 2, and the active level as fast control signal CNT time T _PA by the rising of the clock pulse CK.

In this embodiment, the starting point of the active level of the control signal CNT is advanced with respect to the rising edge of the clock pulse CK, but the switching time from the active level to the inactive level of the control signal CNT is shifted with respect to the falling edge of the clock pulse CK. , And the data processing operation by the falling edge of the clock pulse CK of the internal circuit 4 can be performed reliably.

〔The invention's effect〕

As described above, according to the present invention, a current is supplied to an internal circuit by a control signal which is at an active level when a chip select signal is at an active level and a clock pulse is in a period for performing a data processing operation of the internal circuit. With the configuration in which control is performed, current does not flow to the internal circuit during the data non-processing period, so that power consumption can be reduced.

[Brief description of the drawings]

1 and 2 are a circuit diagram of a first embodiment of the present invention and timing diagrams of signals of respective parts for explaining the operation of this embodiment, respectively. FIGS. 3 and 4 are diagrams of a first embodiment of the present invention, respectively. FIG. 5 is a circuit diagram of the second embodiment, and FIG. 5 is a timing chart of signals of respective parts for explaining the operation of this embodiment.
FIG. 1 is a block diagram of an example of a conventional synchronous semiconductor memory device, and FIG. 2 is a timing chart of signals of respective parts for explaining the operation of this example. 1 ... input circuit, 2 ... logic circuit, 3 ... power control circuit, 4 ... internal circuit, 5 ... adjustment circuit, DI1 ... delay element, G1 ... OR gate.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/41 G11C 11/419

Claims (2)

(57) [Claims] 1. An input circuit for outputting a chip select signal in synchronization with a clock pulse signal, wherein the chip select signal is at an active level and the clock pulse signal is at one of a first active level and a second active level. An internal circuit that performs a data processing operation only when the clock pulse signal is combined with a delayed pulse signal obtained by delaying the phase of the clock pulse signal to advance the start of the active level of the clock pulse or to terminate the active level An adjustment circuit that outputs an adjustment signal delayed by a delay, a logic circuit that outputs an active level control signal when the chip select signal and the adjustment signal are at an active level, and the internal circuit only when the control signal is at an active level. And a current control circuit for controlling a current to be supplied to the synchronous semiconductor memory device. 2. The control circuit according to claim 1, wherein the adjusting circuit includes an inverting circuit for delaying and inverting the clock pulse signal, and an OR circuit for performing an OR operation on an output signal of the inverting circuit and the clock pulse signal. 2. The synchronous semiconductor memory device according to claim 1, comprising a NAND circuit of an inverted signal of said chip select signal and said adjustment signal output.