JPS60195778A - Demodulator of digital information - Google Patents

Abstract

PURPOSE:To prevent remaining data from being accumulated in a RAM by writing a reproduced/demodulated digital signal in order to prevent jitters and by phase-synchronizing a read clock for reading it with a reproduction clock. CONSTITUTION:A digital audio reproduction signal such as a PCM, which is reproduced by a video disk player, etc., is demodulated in a demodulator 8 and written in a RAM11 by a clock through a reproduction clock extraction circuit 9, a frequency divider circuit 14, etc. The RAM11 is read out by a read clock synchronous with a reproduction clock through the circuit 9, frequency divider circuits 15 and 16, a PLL circuit of a phase comparator, an LPF18, a voltage control oscillator 19, etc., and a frequency divider 20, and becomes a demodulated output after jitters are removed. By the constitution employing the read clock synchronous with the reproduction clock, frequency errors of the read clock never occur, and data will not remain in a RAM; therefore the accumulation of remaining data can be prevented.

Description

[Detailed Description of the Invention] 111 The present invention provides digital information wI! Regarding the pupil, especially the PC
The present invention relates to a digital information recovery II device that reproduces a recording disk on which an M digital signal is recorded by a reproducing device and extracts and reproduces a PCM digital signal from the reproduced RF signal.

1) When demodulating a reproduced PCM digital signal, it contains jitter, which is a time axis fluctuation component, so it is written to the -H memory using a write clock synchronized with the reproduced clock signal, and then a read clock of a constant cycle is used to demodulate the reproduced PCM digital signal. It is common to read from memory to remove jitter.

However, the oscillation frequency and phase of the oscillator for controlling the rotation of the recording disk, which determines the frequency and phase of the reproduced clock signal, are subject to errors due to the frequency and phase of the oscillator for generating the readout clock signal and density changes, etc. mentioned above. If the frequency of the read clock becomes slightly lower, the stored data will remain in that portion of the memory. Therefore, it is necessary to increase the memory capacity accordingly.
The larger the error, the larger the memory capacity must be.

Summary of the Invention The present invention provides a digital information system that can remove jitter from a reproduced signal without increasing memory capacity.
The purpose is to provide equipment.

The digital information VI modulation device according to the present invention includes an I modulation means for demodulating a reproduced digital signal, a writing means for writing this demodulation equipment into a memory in synchronization with a reproduction output signal included in the reproduced digital signal, and a memory. clock generating means for generating a read clock signal for reading stored information from the
The present invention is characterized in that it includes phase synchronization means for phase-synchronizing the output of the output clock generation means with the reproduced clock signal, and that the output from the memory is converted into an analog signal and derived.

! LJLJL Embodiments of the present invention will be described below with reference to the drawings.

In the figure, the left side of the chain 130 is a video disc player, and the right side is a digital audio signal all device according to an embodiment of the present invention. The information read by the pickup 1 is demodulated by the video demodulator 2 and becomes a reproduced video signal output. A playback synchronization signal is output from this playback signal to the separator 3.
The signal is separated by the reference signal generator 4, and its phase is compared with the reference signal from the reference signal generator 4 by the phase comparator 5. This comparative output becomes a servo signal that controls the rotation of a spindle motor (not shown).
The rotation of the recording disk is controlled.

The read information from the pickup 1 is input to an LPF (low pass filter) 6 to extract PCM audio information. This audio information is, for example, an EFM signal and is passed through the de-emphasis circuit 7 to Ii1! It is derived as an output.

This output signal is input to the EFMtl modulation circuit 8 and the reproduced clock extraction circuit 9, and is demodulated into a PCM digital signal using the extracted reproduced clock.

This demodulated signal 1 is written into the RAM 11 via the tRAM (random access re-memory) controller 10, but at this time it is written by the output of the frequency divider 14 of the reproduced clock.

Reading from this RAM 11 is performed by the VCO (voltage controlled oscillator) 19 of the PLL (phase locked loop) circuit.
This is done by dividing the output of the frequency divider 20. The PLL circuit includes a PD (phase comparator) 17 that manually generates the frequency-divided output from the frequency divider 15 of the reproduced clock and the frequency-divided output from the frequency divider 16 of the VCO 19;
It consists of an LPF (D-pass filter) 18 which receives this comparison output as an input, and the VCO 19 mentioned above. Therefore, this read clock is phase-synchronized with the reproduced clock by the PLL circuit.

The digital signal thus read out is converted into an audio signal by a D/A (digital analog) converter 12 and an LPFI 3, and becomes a reproduced audio output.

Effect By doing this, the read clock from the RAM 11 is synchronized with the reproduction D clock at the time of writing, so there is no frequency difference between the two clocks, so the RA
No residual data will be accumulated in M. Therefore, the capacity of the RAM 11 does not need to be large.

Further, since jitter is removed from the readout clock by the band limiting action of the loop filter 18 in the PLL circuit, a good reproduced signal can be obtained.

If the block on the right side of the dashed line 30 in the figure is constructed as a 1U11 circuit adapter for digital audio, the adapter input can be simply connected to the digital audio output line of the video disc playback device, resulting in increased versatility.

[Brief explanation of drawings]

The figure is a circuit block diagram of an embodiment of the present invention. Explanation of symbols of main parts 8... Demodulation circuit 9... Regenerated clock extraction circuit 11...RAM 17...PD 18...LPF 19...VCO Applicant: Pioneer Corporation Agent Patent Attorney Motohiko Fujimura

Claims (3)

[Claims] (1) demodulating means for demodulating a reproduced digital signal; writing means for writing the demodulated output into a memory in synchronization with a reproduced clock signal included in the reproduced digital signal; and a read clock signal for reading stored information from the memory. and phase synchronization means for phase-synchronizing the output of the clock generation means with the reproduced clock signal, and the output from the memory is converted into an analog signal and derived. Information demodulator. (2) The control loop of the phase synchronization means has a band till.
Device f according to claim 1, characterized in that a limited loop filter is inserted. (3) The apparatus according to claim 1 or 2, wherein the reproduced digital signal is a digital information signal extracted from a reproduced signal by a video reproduction apparatus.