JPS58212242A - Clock regenerating circuit in digital signal transmission - Google Patents

Abstract

PURPOSE:To extract a regenerative clock with less shift from a PLL with a simple constitution, by adding an RF level detecting circuit and the like to the titled circuit so as to make an input signal to the PLL zero or small even if a part of transmitted time series digital signal is missing. CONSTITUTION:An RF digital signal from a regenerative digital input terminal 7 is demodulated at a demodulating circuit 8, applied to an edge detecting circuit comprising an exclusive OR circuit 12 and a delay circuit 13 via an LPF 10 for detecting edge parts respectively. A frequency being a natural number multiple of its edge detecting signal is extracted at a capacitor C1 and a film L1 for tank circuit and applied to the PLL17 via an amplifier 14 and the like. Further, a signal from a terminal 7 is applied to the RF level detecting circuit 9 to detect the signal level for discriminating the consecution time below a prescribed level not demodulated at the circuit 8 normally at a time discriminating circuit 15. Further, an output of the circuit 15 is applied to a variable impedance element 16 to decrease an input impedance of the PLL17, allowing to extract a prescribed clock signal frequency from the PLL17.

Description

[Detailed Description of the Invention] The invention relates to a clock h main circuit in digital signal transmission.
By making the input signal of the locked loop (PLL) zero or extremely small, the above P can be achieved with a simple and inexpensive configuration.
It is an object of the present invention to provide a clock recovery circuit that can extract a recovered clock signal with little deviation from T and L.

Conventionally, digital video signals related to still images or partial moving images have been added as additional information to digital audio signals, and recorded on the same track on an information recording disk (hereinafter referred to as "disk") in chronological order. It is known that (2) the disc is recorded as a series of intermittent pits, and the disc is read and reproduced using changes in capacitance or changes in the intensity of light. In this case, the digital signal to be transmitted is, for example, as schematically shown in FIG.
The digital data of the four 6-bit child channels (data of the digital audio signal and/or digital video signal) are placed in chronological order at the positions indicated by D1 to D4, and the subsequent P1, P2 of the song is Each 16-bit error correction code is placed in the position indicated by , and the 23-bit error correction code is placed in the position indicated by CRC.
A bit error check code (cyclic retency check code) is placed respectively. For example, in the position indicated by Adr of the last 3 bits, all 19
One data bit of the 6-bit control signal is allocated, and the remaining 0 bits are called user's bits, and 2 bits for blanks are allocated.゛The digital signal that constitutes one frame with a total of 130 bits from 5YNC to U mentioned above has a repetition frequency (3) of 44.1 kHz, which is the same as the sampling frequency.
The signals are synthesized and transmitted in time series in frame units at a transmission bit rate of 5.733 M11/s. This time-series composite digital signal MLt, Nll, Z (non-return-to-zero) signal is used for self-clockable digital signals such as MPM (modified sophistication modulation) and 3PM (three-position modulation). Frequency modulation is performed after modulation, or frequency modulation is performed without manual digital modulation, and then a light beam or the like is used to record the disc as an intermittent series of pits. Here, for convenience of explanation, a disk on which frequency modulation is immediately performed and recorded will be described.

In the P1 reproduction device m of this disc, the frequency demodulation of the signal reproduced from the disc is performed to obtain a 41:, li1 raw digital signal having a frame configuration as shown in FIG. Round number (e.g. 5.73
3Mllz) clock (number N) is regenerated using a clock regeneration circuit, and based on the obtained clock signal, detects a synchronization signal in the reproduced digital signal and writes data to the memory circuit. etc.

FIGS. 2 and 3 show block diagrams of the conventional clock recovery circuit, respectively. In both figures, the same constituent parts are labeled with the same city name. In FIG. 2, a reproduced digital signal having a frame structure as shown in FIG. 1 that has entered an input terminal 1 is supplied to an edge detection circuit 2, where rising and falling edges are detected. A signal is supplied to the tank circuit 3. The tank circuit 3 is configured to tune to a frequency that is a natural number multiple of the transmission bit rate (therefore, 5.733 MHz in the case of 1 times the transmission bit rate), and its output signal (sine S) is supplied to the limiter 4. Here, the amplitude is limited and converted into a rectangular wave, and then outputted to the output terminal 5 as a clock signal.

However, the digital signal played back from the disc has
Time axis fluctuations (jitter) are included due to causes such as uneven rotation of the disk, and in circuit (5) shown in Figure 2, frequency fluctuations in the clock signal appear as they are at output terminal 5. Therefore, bit misalignment is likely to occur. Conventionally, as shown in FIG. 3, a T'LL 6 has been used in place of the limiter 4 to absorb the jitter component and output the clock signal to the output terminal 5.

By the way, during the dropout period, the internal data in the playback signal from the disk will generally be different from the one at the time of recording due to defects on the disk or poor recording, or the internal data will be different from the one at the time of recording. Since code errors are detected by the check code, at this time, by using the above-mentioned two-pole error correction code and performing modulo 2 addition for each corresponding bit together with the digital data of the four channels,
Most code errors can be corrected and restored to the original data. However, these signal processes are based on the premise that the clock signal is stably and accurately reproduced.

However, if the above-mentioned dropout time length is long, the clock information obtained from the reproduced digital signal also contains irregular noise components, and the Q of the tank circuit 3 is reduced.
Since also has a finite value, it may output a frequency that deviates considerably from the tuning center frequency. on the other hand,
PLL 6 has a fairly wide lock range when the input level is large.

For example, when NE564 manufactured by Shida Futakus is used as a commercially available IC-based PI, L, its lock range characteristics are shown by the curve "it" when the power supply voltage is ±12V, as shown in Figure 4, and ±6 When it is ■, it is indicated by a curve ■. Therefore, no matter which power source 111 is used, if the input level is 100 mV or higher, the input level is 10 mV.
? ? It can be seen that it has a wide lock range from lV to F.

For this reason, the PI and L6 are locked to a frequency that deviates considerably from the tuning center frequency from the tank circuit 3, which occurs when the dropout time described above is long.
Output clock signal of PLL6: l'', l.

The frequency also fluctuates significantly. When a large frequency fluctuation occurs in the clock signal, the error correction circuit adds the above-mentioned error correction code and the digital data of the four channels modulo t[11f+% to correct and restore the code error. Furthermore, since the addition operation is performed on data different from the data to which the addition operation should originally be performed, correct correction and restoration cannot be performed.

Therefore, the present applicant previously proposed in Japanese Patent Application No. 56-79890 a voltage controlled oscillator in the PLL 6 using, for example, a ground pressure controlled crystal IH generator (VCXO) with an extremely narrow range of output signal frequency change relative to the control voltage. By using a switch circuit that switches the output signal of the phase comparator in the PLL 6 to a substantially constant value, fluctuations in the clock frequency are suppressed within a range that does not cause bit slippage, thereby achieving the above. PLL when clock information cannot be obtained for a long time
We have proposed a clock recovery circuit that prevents the phenomenon of erroneous correction following false clock information from the tank circuit 3. However, this proposed clock recovery circuit is
■Components such as CXO are expensive, the circuit scale is large, and the frequency fluctuation of the clock signal actually generates abnormal noise that is perceived by the listener, which is higher than the practically acceptable range of the same wave number fluctuation. (8) The problem was that the clock regeneration circuit was not suitable for consumer use because the clock was kept too small.

The present invention eliminates the above-mentioned drawbacks and also solves the above-mentioned problems, and an embodiment thereof will be described below with reference to FIG. 5.

FIG. 5 shows a circuit system diagram of an embodiment of the clock recovery circuit according to the present invention. In the figure, a high-frequency frequency-modulated digital signal (RF digital signal) picked up and reproduced from the disk by a pickup and reproduction element (both not shown) is corrected for its frequency characteristics by an equalizer (not shown). After that, it is supplied to the demodulation circuit 8 from the input terminal 7,
Here, the reproduction signal is adjusted to have a frame structure as shown in FIG. 1, and is supplied to the RF level detection circuit 9.
Here, the FLE' level (envelope level) is detected. The demodulation circuit 8 is composed of a limiter, a multiplier, etc.
The reproduced signal extracted from this is converted into a squared cosine wave by the low finished filter 10 and then supplied to the comparator 11.
Here, it is converted to the original binary D(9) digital signal.

The output digital signal of the comparator 11 is applied to one input terminal of the exclusive OR circuit 12, and after being delayed by a delay circuit 13 for a time sufficiently smaller than its minimum inversion interval, the output digital signal is applied to the other input terminal of the exclusive OR circuit 12. is applied to the input terminal of That is, the exclusive OR circuit 12 and the delay circuit 13 constitute a known edge detection circuit, and the exclusive OR circuit 12 detects a phase at each rising and falling edge of the output digital signal of the comparator 11. An edge detection signal with a synchronized small pulse width (equal to the delay time of the delay line 13) is retrieved.

This edge detection signal is transmitted by the capacitor C1 and the coil L.
The clock frequency f. Only the clock signal components that are a natural number multiple of the edge detection signal frequency are extracted by the tank circuit tuned to the DC blocking capacitor C2,
The signal is supplied to a commercially available PLL 17 via an amplifier 14, a resistor R1, and a capacitor C1, respectively. Note that the connection point between the resistor R1 and the resistor C4 is grounded via the capacitor C3 and the variable impedance element (or switch circuit) 16.

On the other hand, the signal output from the RF level detection circuit 9 is supplied to the time discrimination circuit 15. This time discrimination circuit 15 is a circuit that discriminates whether the level of the input ItF digital signal from the input terminal 7 has decreased to a predetermined level or below that cannot be normally demodulated by the demodulation circuit 8, or whether it has continued for a certain period of time. It is.

The above-mentioned fixed time discriminated by the time discrimination circuit 15 is a time slightly shorter than the time length of dropout (for example, 20 frames of digital signal transmission period).

The time discrimination circuit 15 is usually a variable impedance element 16
When the impedance has a maximum value of 1' and continues for a certain period of time at the I(li'' level or below the predetermined level, the variable impedance element 16 Therefore, in the normal case where dropout does not occur, or when dropout occurs but the time length is less than the above fixed time, the PLL 17 outputs a signal that increases the impedance to approximately zero ohm. A clock signal component from the tank circuit 14 is supplied, and a clock signal with a frequency that follows that frequency is taken out at the output terminal 18.If the dropout time is long or short, a gradually attenuating signal is output from the tank circuit. Since the signal frequency does not deviate much from the tuning center frequency of the tank circuit, a clock signal with no problem of frequency fluctuation in practical use is taken out from PT and Li2.

On the other hand, when dropout continues for more than the above-mentioned certain period of time, the output signal of the amplifier 14 is AC grounded via the capacitor C3 and the a1 variable impedance element 16, and the input signal of P L It 17 is The level becomes zero or minimal. Here, when the input signal level of the PLL 17 becomes zero or minimum, as is well known, the voltage controlled oscillator in the PI and Li2 oscillates at a constant free-running oscillation frequency determined by the circuit constants of the capacitor C5 and the like. In this embodiment, this free-running oscillation frequency is selected in advance to be a natural number multiple or a natural number fraction of the clock signal frequency. 18
A clock signal of a predetermined clock signal frequency is extracted. As a result, even if the dropout time is long, significant frequency fluctuations of the clock signal are suppressed, and ■C
The operation of the correction circuit can be stabilized without using expensive parts such as an XO, and erroneous corrections can be minimized.

In addition, in Uemachi's example, the digital signal is recorded on a disk, and the case where it is applied to a device that reproduces this is explained, but it is also applicable to the case where it is recorded on other recording media such as magnetic tape. can.

As mentioned above, the clock regeneration circuit for digital signal transmission according to the present invention is capable of reproducing ILIi' from a recording medium.
After passing the digital signal through a demodulation circuit, each edge portion of the demodulated digital signal is detected. A phase-locked loop that outputs a reproduced clock signal phase-synchronized with the output signal of the RF digital signal, a level detection circuit that detects the level of the RF digital signal reproduced from the recording medium, and a phase-locked loop that supplies the output signal of the level detection circuit. 111i'
It is a means to reduce the input signal level of the phase-locked loop to zero or to a minimum when the level of the digital signal is at a low level that cannot be demodulated by the IE modulation circuit, or continues for a certain period of time. When the input signal level is zero or minimum, the voltage controlled oscillator in the phase-locked loop is made to run freely at a frequency that is a natural number multiple or a natural number multiple of the frequency of the clock nit to be reproduced. Since it is configured to extract a constant signal frequency from the phase-locked loop,
In the event of a long-duration dropout, the phase-locked loop can output a constant frequency clock signal with no frequency variation, and therefore
14) When clock information cannot be obtained for a long time, it is possible to minimize the error correction caused by the phase-locked loop following false clock information from the tank circuit. The above phase-locked PLL-IC can be used without using any special parts.
Since it can be used in a loop, it can have an inexpensive circuit configuration, and therefore has the advantage of being particularly suitable for consumer use.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing an example of the configuration of one frame of a digital signal, FIGS. 2 and 3 are block diagrams showing each side of a conventional circuit, and FIG. Figure 5, which is a diagram showing an example of input level vs. lock range characteristics, is a circuit system diagram showing an embodiment of the circuit of the present invention. 6 ・ 1 7 see 7 Z X
° ” / '? and ° '' -bu (Pi, T,)
・7... Square raw digital signal input terminal, 9・Φ・RF
Level detection circuit, 11... Comparator, 13...
Delay circuit, 15... Time discrimination circuit, 16... Variable impedance element, 18.Φ.Clock signal output terminal,
C1Φ medium fist tank circuit capacitor, L1Φ...tank circuit coil. /R3'/Minute

Claims (1)

[Claims] After passing the RF digital signal reproduced from the recording medium through a demodulation circuit, an edge detection signal obtained by detecting each edge portion of the demodulated digital code is supplied, and the edge detection signal is supplied with a frequency that is a natural number multiple of the edge detection signal. A tank circuit that takes out a signal, a phase-locked loop that is supplied with the output signal of the tank circuit and outputs a regenerated clock signal that is phase-synchronized therewith;
A level detection circuit detects the level of the RF digital signal, and when the output signal of the level detection circuit is supplied and the level of the RF digital signal is at a low level that cannot be properly demodulated by the demodulation circuit or continues for a certain period of time, the phase is detected.・It is a means for reducing the input signal level of the locked loop to zero or to a minimum, and when the input signal level of the phase-locked loop is reduced to zero or to a minimum, (1) voltage control within the phase-locked loop is performed. A constant clock signal frequency is extracted from the phase-locked loop by free-running oscillation at a frequency that is a natural number multiple or a fraction of a natural number of the clock signal frequency to be reproduced. Clock recovery circuit for digital signal transmission.